TL082CPNOPB - NATIONAL SEMICONDUCTOR

SCANSTA112

SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer

Literature Number: SNLS161H

SCANSTA112

7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer

General Description

The SCANSTA112 extends the IEEE Std. 1149.1 test bus

into a multidrop test bus environment. The advantage of a

multidrop approach over a single serial scan chain is im-

proved test throughput and the ability to remove a board

from the system and retain test access to the remaining

modules. Each SCANSTA112 supports up to 7 local

IEEE1149.1 scan chains which can be accessed individually

or combined serially.

Addressing is accomplished by loading the instruction regis-

ter with a value matching that of the Slot inputs. Backplane

and inter-board testing can easily be accomplished by park-

ing the local TAP Controllers in one of the stable TAP Con-

troller states via a Park instruction. The 32-bit TCK counter

enables built in self test operations to be performed on one

port while other scan chains are simultaneously tested.

The STA112 has a unique feature in that the backplane port

and the LSP0 port are bidirectional. They can be configured

to alternatively act as the master or slave port so an alternate

test master can take control of the entire scan chain network

from the LSP0 port while the backplane port becomes a

slave.

Features

nTrue IEEE 1149.1 hierarchical and multidrop

addressable capability

nThe 8 address inputs support up to 249 unique slot

addresses, an Interrogation Address, Broadcast

Address, and 4 Multi-cast Group Addresses (address

000000 is reserved)

n7 IEEE 1149.1-compatible configurable local scan ports

nBi-directional Backplane and LSP

ports are

interchangeable slave ports

nCapable of ignoring TRST of the backplane port when it

becomes the slave.

nStitcher Mode bypasses level 1 and 2 protocols

nMode Register

allows local TAPs to be bypassed,

selected for insertion into the scan chain individually, or

serially in groups of two or three

nTransparent Mode can be enabled with a single

instruction to conveniently buffer the backplane IEEE

1149.1 pins to those on a single local scan port

nGeneral purpose local port pass through bits are useful

for delivering write pulses for Flash programming or

monitoring device status.

nKnown Power-up state

nTRST on all local scan ports

n32-bit TCK counter

n16-bit LFSR Signature Compactor

nLocal TAPs can become TRI-STATE via the OE input to

allow an alternate test master to take control of the local

TAPs (LSP

0-3

have a TRI-STATE notification output)

n3.0-3.6V V

Supply Operation

nSupports live insertion/withdrawal

20051250

FIGURE 1. Typical use of SCANSTA112 for board-level management of multiple scan chains.

October 2005

SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer

Introduction

The SCANSTA112 is the third device in a series that enable

multi-drop address and multiplexing of IEEE-1149.1 scan

chains. The SCANSTA112 is a superset of its predecessors

- the SCANPSC110 and the SCANSTA111. The STA112 has

all features and functionality of these two previous devices.

The STA112 is essentially a support device for the IEEE

1149.1 standard. It is primarily used to partition scan chains

into managable sizes, or to isolate specific devices onto a

seperate chain (Figure 1). The benefits of multiple scan

chains are improved fault isolation, faster test times, faster

programiing times, and smaller vector sets.

In addition to scan chain partitioning, the device is also

addressable for use in a multidrop backplane environment

(Figure 2). In this configuration, multiple IEEE-1149.1 acces-

sible cards with an STA112 on board can utilize the same

backplane test bus for system-level IEEE-1149.1 access.

This approach facilitates a system-wide commitment to

structural test and programming throughout the entire sys-

tem life sycle.

Architecture

Figure 3 shows the basic architecture of the ’STA112. The

device’s major functional blocks are illustrated here.

The TAP Controller, a 16-state state machine, is the central

control for the device. The instruction register and various

test data registers can be scanned to exercise the various

functions of the ’STA112 (these registers behave as defined

in IEEE Std. 1149.1).

The ’STA112 selection controller provides the functionality

that allows the 1149.1 protocol to be used in a multi-drop

environment. It primarily compares the address input to the

slot identification and enables the ’STA112 for subsequent

scan operations.

The Local Scan Port Network (LSPN) contains multiplexing

logic used to select different port configurations. The LSPN

control block contains the Local Scan Port Controllers

(LSPC) for each Local Scan Port (LSP

, LSP

... LSP

). This

control block receives input from the ’STA112 instruction

port contains all four boundary scan signals needed to inter-

face with the local TAPs plus the optional Test Reset signal

(TRST).

The TDI/TDO Crossover Master/Slave logic is used to define

the bidirectional B0 and B1 ports in a Master/Slave

configuration.

20051251

FIGURE 2. Example of SCANSTA112 in a multidrop addressable backplane.

SCANSTA112

www.national.com 2

Block Diagram

20051202

FIGURE 3. SCANSTA112 Block Diagram

SCANSTA112

www.national.com3

Connection Diagrams

20051201

(BGA Top view)

SCANSTA112

www.national.com 4

Connection Diagrams (Continued)

20051260

TQFP pinout

SCANSTA112

www.national.com5

TABLE 1. Pin Descriptions

Pin Name Description

No.

Pins I/O

VCC 10 N/A Power

GND 10 N/A Ground

RESET 1 I RESET Input: will force a reset of the device regardless of the current state.

ADDMASK 1 I ADDRESS MASK input: Allows masking of lower slot input pins.

MPsel

B1/B0

1 I MASTER PORT SELECTION: Controls selection of LSP

or LSP

as the backplane port.

The unselected port becomes LSP

. A value of "0" will select LSP

as the master port.

SB/S 1 I Selects ScanBridge or Stitcher Mode.

LSPsel

(0-6)

7 I In Stitcher Mode these inputs define which LSP’s are to be included in the scan chain

TRANS 1 I Transparent Mode enable input: The value of this pin is loaded into the TRANSENABLE bit

of the control register at power-up. This value is used to control the presence of registers

and pad-bits in the scan chain while in the stitcher mode.

TLR_TRST 1 I Sets the driven value of TRST

0-5

when LSP TAPs are in TLR and the device is not being

reset. During RESET = "0" or TRST

= "0" (IgnoreReset = "0") TRST

= "0". This pin is to be

tied low to match the function of the SCANSTA111

TLR_TRST

1 I This pin affects TRST of LSP

only. This pin is to be tied low to match the function of the

SCANSTA111

TDI

, TDI

2 I BACKPLANE TEST DATA INPUT: All backplane scan data is supplied to the ’STA112

through this input pin. MPsel

B1/B0

determines which port is the master backplane port and

which is LSP

. This input has a 25KΩinternal pull-up resistor and no ESD clamp diode

(ESD is controlled with an alternate method). When the device is power-off (V

floating),

this input appears to be a capacitive load to ground (Note 1). When V

= 0V (i.e.; not

floating but tied to V

) this input appears to be a capacitive load with the pull-up to ground.

TMS

, TMS

2 I/O BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the

’STA112. Also controls sequencing of the TAPs which are on the local scan chains.

MPsel

B1/B0

determines which port is the master backplane port and which is LSP

. This

bidirectional TRI-STATE pin has 24mA of drive current, with a 25KΩinternal pull-up resistor

and no ESD clamp diode (ESD is controlled with an alternate method). When the device is

power-off (V

floating), this input appears to be a capacitive load to ground (Note 1). When

= 0V (i.e.; not floating but tied to V

) this input appears to be a capacitive load with the

pull-up to ground.

TDO

, TDO

2 I/O BACKPLANE TEST DATA OUTPUT: This output drives test data from the ’STA112 and the

local TAPs, back toward the scan master controller. This bidirectional TRI-STATE pin has

12mA of drive current. MPsel

B1/B0

determines which port is the master backplane port and

which is LSP

. Output is sampled during interrogation addressing. When the device is

power-off (V

= 0V or floating), this output appears to be a capacitive load (Note 1).

TCK

, TCK

2 I/O TEST CLOCK INPUT FROM THE BACKPLANE: This is the master clock signal that controls

all scan operations of the ’STA112 and of the local scan ports. MPsel

B1/B0

determines which

port is the master backplane port and which is LSP

. These bidirectional TRI-STATE pins

have 24mA of drive current with hysterisis. This input has no pull-up resistor and no ESD

clamp diode (ESD is controlled with an alternate method). When the device is power-off (V

floating), this input appears to be a capacitive load to ground (Note 1). When V

= 0V (i.e.;

not floating but tied to V

) this input appears to be a capacitive load to ground.

TRST

, TRST

2 I/O TEST RESET: An asynchronous reset signal (active low) which initializes the ’STA112 logic.

MPsel

B1/B0

determines which port is the master backplane port and which is LSP

. This

bidirectional TRI-STATE pin has 24mA of drive current, with a 25KΩinternal pull-up resistor

and no ESD clamp diode (ESD is controlled with an alternate method). When the device is

power-off (V

floating), this pin appears to be a capacitive load to ground (Note 1). When

= 0V (i.e.; not floating but tied to V

) this input appears to be a capacitive load with the

pull-up to ground.

SCANSTA112

www.national.com 6

TABLE 1. Pin Descriptions (Continued)

Pin Name Description

No.

Pins I/O

TRIST

, TRIST

TRIST

(01-03)

5 O TRI-STATE NOTIFICATION OUTPUT: This signal is asserted high when the associated

TDO is TRI-STATEd. Associated means TRIST

is for TDO

, TRIST

is for TDO

, etc.

This output has 12mA of drive current.

,A1

,A0

4 I BACKPLANE PASS-THROUGH INPUT: A general purpose input which is driven to the Y

a single selected LSP. (Not available when multiple LSPs are selected). This input has a

25KΩinternal pull-up resistor. MPsel

B1/B0

determines which port is the master backplane

port and which is LSP

,Y1

,Y0

4 O BACKPLANE PASS-THROUGH OUTPUT: A general purpose output which is driven from

the A

of a single selected LSP. (Not available when multiple LSPs are selected). This

TRI-STATE output has 12mA of drive current. MPsel

B1/B0

determines which port is the

master backplane port and which is LSP

(0-7)

8 I SLOT IDENTIFICATION: The configuration of these pins is used to identify (assign a unique

address to) each ’STA112 on the system backplane

OE 1 I OUTPUT ENABLE for the Local Scan Ports, active low. When high, this active-low control

signal TRI-STATEs all local scan ports on the ’STA112, to enable an alternate resource to

access one or more of the local scan chains.

TDO

(01-06)

6 O TEST DATA OUTPUTS: Individual output for each of the local scan ports . These

TRI-STATE outputs have 12mA of drive current.

TDI

(01-06)

6 I TEST DATA INPUTS: Individual scan data input for each of the local scan ports. This input

has a 25KΩinternal pull-up resistor.

TMS

(01-06)

6 O TEST MODE SELECT OUTPUTS: Individual output for each of the local scan ports. TMS

does not provide a pull-up resistor (which is assumed to be present on a connected TMS

input, per the IEEE 1149.1 requirement) . These TRI-STATE outputs have 24mA of drive

current.

TCK

(01-06)

6 O LOCAL TEST CLOCK OUTPUTS: Individual output for each of the local scan ports. These

are buffered versions of TCK

. These TRI-STATE outputs have 24mA of drive current.

TRST

(01-06)

6 O LOCAL TEST RESETS: A gated version of TRST

. These TRI-STATE outputs have 24mA

of drive current.

,A1

2 I LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the

backplane pin Y

. (Only on LSP

and LSP

. Only available when a single LSP is selected) .

These inputs have a 25KΩinternal pull-up resistor.

,Y1

2 O LOCAL PASS-THROUGH OUTPUT: General purpose outputs which can be driven from the

backplane pin A

. (Only on LSP

and LSP

. Only available when a single LSP is selected) .

These TRI-STATE outputs have 12mA of drive current.

Note 1: Refer to the IBIS model on our website for I/O characteristics.

Application Overview

ADDRESSING SCHEME

The SCANSTA112 architecture extends the functionality of

the IEEE 1149.1 Standard by supplementing that protocol

with an addressing scheme which allows a test controller to

communicate with specific ’STA112s within a network of

’STA112s. That network can include both multi-drop and

hierarchical connectivity. In effect, the ’STA112 architecture

allows a test controller to dynamically select specific portions

of such a network for participation in scan operations. This

allows a complex system to be partitioned into smaller

blocks for testing purposes. The ’STA112 provides two levels

of test-network partitioning capability. First, a test controller

can select individual ’STA112s, specific sets of ’STA112s

(multi-cast groups), or all ’STA112s (broadcast). This

’STA112-selection process is supported by a Level-1 com-

munication protocol. Second, within each selected ’STA112,

a test controller can select one or more of the chip’s seven

local scan-ports. That is, individual local ports can be se-

lected for inclusion in the (single) scan-chain which a

’STA112 presents to the test controller. This mechanism

allows a controller to select specific scan-chains within the

overall scan network. The port-selection process is sup-

ported by a Level-2 protocol.

HIERARCHICAL SUPPORT

Multiple SCANSTA112’s can be used to assemble a hierar-

chical boundary-scan tree. In such a configuration, the sys-

tem tester can configure the local ports of a set of ’STA112s

so as to connect a specific set of local scan-chains to the

active scan chain. Using this capability, the tester can selec-

tively communicate with specific portions of a target system.

The tester’s scan port is connected to the backplane scan

port of a root layer of ’STA112s, each of which can be

SCANSTA112

www.national.com7

Application Overview (Continued)

selected using multi-drop addressing. A second tier of

’STA112s can be connected to this root layer, by connecting

a local port (LSP) of a root-layer ’STA112 to the backplane

port of a second-tier ’STA112. This process can be continued

to construct a multi-level scan hierarchy. ’STA112 local ports

which are not cascaded into higher-level ’STA112s can be

thought of as the terminal leaves of a scan tree. The test

master can select one or more target leaves by selecting and

configuring the local ports of an appropriate set of ’STA112s

in the test tree.

STANDARD SCANBRIDGE MODE

ScanBridge mode refers to functionality and protocol that

has been used by National since the introduction of the

PSC110 in 1993. This functionality consists of a multidrop

addressable IEEE1149.1 switch. This enables one (or more)

device to be selected from many that are connected to a

parallel IEEE1149.1 bus or backplane. The second function

that ScanBridge mode accomplishes is to act as a mux for

multiple IEEE1149.1 local scan chains. The Local Scan

Ports (LSP) of the device creates a connection between one

or more of the local scan chains to the backplane bus.

To accomplish this functionality the ScanBridge has two

levels of protocol and an operational mode. Level 1 protocol

refers to the required actions to address/select the desired

ScanBridge. Level 2 protocol is required to configuring the

mux’ing function and enable the connection (UNPARK) be-

tween the local scan chain and the backplane bus via an

LSP. Upon completion of level 1 and 2 protocols the Scan-

Bridge is prepared for its operational mode. This is where

scan vectors are moved from the backplane bus to the

desired local scan chain(s).

STITCHER MODE

Stitcher Mode is a method of skipping level 1 and 2 protocol

of the ScanBridge mode of operation. This is accomplished

via external pins. When in stitcher mode the SCANSTA112

will go directly to the operational mode.

TRANSPARENT MODE

Transparent mode refers to a condition of operation in which

there are no pad-bits or SCANSTA112 registers in the scan

chain. The Transparent mode of operation is available in

both ScanBridge and Stitcher modes. Only the activation

method differs. Once transparent mode has been activated

there is no difference in operation. Transparent mode allows

for the use of vectors that have been generated for a chain

where these bits were not included.

Check with your ATPG tool vendor to ensure support of

these features.

For details regarding the internal operation of the SCAN-

STA112 device, refer to applications note AN-1259 SCAN-

STA112 Designers Reference.

SCANSTA112

www.national.com 8

Absolute Maximum Ratings (Note 2)

Supply Voltage (V

) −0.3V to +4.0V

DC Input Diode Current (I

)

= −0.5V −20 mA

DC Input Voltage (V

) −0.5V to +3.9V

DC Output Diode Current (I

)

= −0.5V −20 mA

DC Output Voltage (V

) −0.3V to +3.9V

DC Output Source/Sink Current (I

)±50 mA

DC V

or Ground Current ±50 mA

per Output Pin

DC Latchup Source or Sink Current ±300 mA

Junction Temperature (Plastic) +150˚C

Storage Temperature −65˚C to +150˚C

Lead Temperature (Solder, 4sec)

100L FBGA 220˚C

100L TQFP 220˚C

Max Package Power Capacity @

25˚C

100L FBGA 3.57W

100L TQFP 2.11W

Thermal Resistance (θ

)

100L FBGA 35˚C/W

100L TQFP 59.1˚C/W

Package Derating above +25˚C

100L FBGA 28.57mW/˚C

100L TQFP 16.92mW/˚C

ESD Last Passing Voltage

(HBM Min) 2500V

Recommended Operating

Conditions

Supply Voltage (V

)

’STA112 3.0V to 3.6V

Input Voltage (V

) 0VtoV

Output Voltage (V

) 0VtoV

Operating Temperature (T

)

Industrial −40˚C to +85˚C

Note 2: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, without

exception, to ensure that the system design is reliable over its power supply,

temperature, and output/input loading variables. National does not recom-

mend operation of SCAN STA products outside of recommended operation

conditions.

DC Electrical Characteristics

Over recommended operating supply voltage and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Max Units

Minimum High Input Voltage V

OUT

= 0.1V or 2.1 V

−0.1V

Maximum Low Input Voltage V

OUT

= 0.1V or 0.8 V

−0.1V

Minimum High Output Voltage I

OUT

= −100 µA V

- 0.2v V

All Outputs and I/O Pins V

or V

Minimum High Output Voltage I

OUT

= −12 mA 2.4 V

TDO

, TDO

, TRIST

,Y0

,Y1

, TDO

(01-06)

,Y0

,Y1

, TRIST

(01-03)

All Outputs Loaded

Minimum High Output Voltage I

OUT

= −24mA 2.2 V

TMS

, TMS

, TCK

, TRST

TMS

(01-06)

, TCK

(01-06)

, TRST

(01-06)

Maximum Low Output Voltage I

OUT

= +100 µA 0.2 V

All Outputs and I/O Pins V

or V

Maximum Low Output Voltage I

OUT

= +12 mA 0.4 V

TDO

, TDO

, TRIST

,Y0

,Y1

, TDO

(01-06)

,Y0

,Y1

, TRIST

(01-03)

Maximum Low Output Voltage I

OUT

= +24mA 0.55 V

TMS

, TMS

, TCK

, TRST

TMS

(01-06)

, TCK

(01-06)

, TRST

(01-06)

VIKL Maximum Input Clamp Diode Voltage IIK = -18mA -1.2 V

Maximum Input Leakage Current V

or GND ±5.0 µA

(non-resistor input pins)

SCANSTA112

www.national.com9

DC Electrical Characteristics (Continued)

Over recommended operating supply voltage and temperature ranges unless otherwise specified

Symbol Parameter Conditions Min Max Units

ILR

Input Current Low V

= GND -45 -200 µA

(Input and I/O pins with pull-up resistors: TDI

TDI

, TMS

, TRST

,A0

,A1

, TDI

(01-06)

,A0

,A1

)

Input High Current

(Input and I/O pins with pull-up resistors: TDI

TDI

, TMS

, TRST

,A0

,A1

, TDI

(01-06)

,A0

,A1

)

5.0 µA

OFF

Power-off Leakage Current

Outputs and I/O pins without pull-up resistors

= 0V, V

= 3.6V

(Note 3)

±5.0 µA

Outputs and I/O pins with pull-up resistors ±200 µA

Maximum TRI-STATE Leakage Current ±5.0 µA

Outputs and I/O pins without pull-up resistors

Maximum Quiescent Supply Current V

or GND 3.8 mA

CCD

Maximum Dynamic Supply Current V

or GND, Input

Freq = 25MHz

68 mA

Note 3: Guaranteed by equivalent test method.

AC Electrical Characteristics: Scan Bridge Mode

Over recommended operating supply voltage and temperature ranges unless otherwise specified (Note 5).

Symbol Parameter Conditions Typ Max Units

PHL

, Propagation Delay 8.5 13.5 ns

PLH

TCK

to TDO

or TDO

PHL

, Propagation Delay 8.5 14.0 ns

PLH

TCK

to TDO

or TDO

PHL

, Propagation Delay 7.5 12.5 ns

PLH

TCK

to TDO

(01-06)

PHL

, Propagation Delay 7.5 13.0 ns

PLH

TCK

to TDO

(01-06)

PHL