DS1202, DS1202S DS1202, DS1202S Serial Timekeeping Chip FEATURES PIN ASSIGNMENT * Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid up to 2100 * 24 x 8 RAM for scratchpad data storage * Serial I/O for minimum pin count NC 1 8 VCC X1 2 7 SCLK X2 3 6 I/O GND 4 5 RST 8-PIN DIP * 2.0-5.5 volt full operation 1 2 3 4 NC X1 X2 GND * Uses less than 300 nA at 2 volts * Single-byte or multiple-byte (burst mode) data trans- 8 7 6 5 VCC SCLK I/O RST 8-PIN SOIC (208 mil) fer for read or write of clock or RAM data * 8-pin DIP or optional 16-pin SOIC for surface mount * Simple 3-wire interface * TTL-compatible (VCC = 5V) * Optional industrial temperature range -40C to +85C (IND) ORDERING INFORMATION DS1202 DS1202S DS1202S-8 DS1202N DS1202SN DS1202SN-8 8-pin DIP 16-pin SOIC 8-pin SOIC 8-pin DIP (IND) 16-pin SOIC (IND) 8-pin SOIC (IND) NC 1 16 VCC NC 2 15 NC X1 3 14 SCLK NC 4 13 NC X2 5 12 I/O NC 6 11 NC NC 7 10 NC GND 8 9 RST 16-PIN SOIC PIN DESCRIPTION NC X1, X2 GND RST I/O SCLK VCC - - - - - - - No Connection 32.768 KHz Crystal Input Ground Reset Data Input/Output Serial Clock Power Supply Pin DESCRIPTION The DS1202 Serial Timekeeping Chip contains a real time clock/calendar and 24 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with less than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator. Interfacing the Copyright 1997 by Dallas Semiconductor Corporation. All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor data books. DS1202 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: (1) RST (Reset), (2) I/O (Data line), and (3) SCLK (Serial clock). Data can be transferred to and from the clock/ RAM one byte at a time or in a burst of up to 24 bytes. The DS1202 is designed to operate on very low power and retain data and clock information on less than 1 microwatt. 032697 1/11 DS1202, DS1202S OPERATION The number of clock pulses equals eight plus eight for byte mode or eight plus up to 192 for burst mode. The main elements of the Serial Timekeeper are shown in Figure 1: shift register, control logic, oscillator, real time clock, and RAM. To initiate any transfer of data, RST is taken high and eight bits are loaded into the shift register providing both address and command information. Data is serially input on the rising edge of the SCLK. The first eight bits specify which of 32 bytes will be accessed, whether a read or write cycle will take place, and whether a byte or burst mode transfer is to occur. After the first eight clock cycles have occurred which load the command word into the shift register, additional clocks will output data for a read or input data for a write. COMMAND BYTE The command byte is shown in Figure 2. Each data transfer is initiated by a command byte. The MSB (Bit 7) must be a logic 1. If it is zero, further action will be terminated. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits one through five specify the designated registers to be input or output, and the LSB (Bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0). DS1202 BLOCK DIAGRAM Figure 1 32.768 KHz X1 I/O X2 OSCILLATOR AND DIVIDER REAL TIME CLOCK INPUT SHIFT REGISTERS DATA BUS SCLK RST COMMAND AND CONTROL LOGIC 24 X 8 RAM ADDRESS BUS ADDRESS/COMMAND BYTE Figure 2 7 1 6 RAM CK 032697 2/11 5 4 3 2 1 A4 A3 A2 A1 A0 0 RD W DS1202, DS1202S RESET AND CLOCK CONTROL All data transfers are initiated by driving the RST input high. The RST input serves two functions. First, RST turns on the control logic which allows access to the shift register for the address/command sequence. Second, the RST signal provides a method of terminating either single byte or multiple byte data transfer. A clock cycle is a sequence of a falling edge followed by a rising edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on t he falling edge of clock. All data transfer terminates if the RST input is low and the I/O pin goes to a high impedance state. Data transfer is illustrated in Figure 3. DATA INPUT Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0. Due to the inherent nature of the logic state machine, writing times containing an absolute value of "59" seconds should be avoided. DATA OUTPUT Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as RST remains high. This operation permits continuous burst mode read capability. Data is output starting with bit 0. BURST MODE Burst mode may be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits one through five = logical one). As before, bit six specified clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 8 through 31 in the Clock/Calendar Registers or locations 24 through 31 in the RAM registers. When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 24 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 24 bytes are written or not. CLOCK/CALENDAR The clock/calendar is contained in eight write/read registers as shown in Figure 4. Data contained in the clock/ calendar registers is in binary coded decimal format (BCD). CLOCK HALT FLAG Bit 7 of the seconds register is defined as the clock halt flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1202 is placed into a low-power standby mode with a current drain of not more than 100 nanoamps. When this bit is written to logic 0, the clock will start. AM-PM/12-24 MODE Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10 hour bit (20-23 hours). WRITE PROTECT BIT Bit 7 of the control register is the write protect bit. The first seven bits (bits 0-6) are forced to zero and will always read a zero when read. Before any write operation to the clock or RAM, bit 7 must be zero. When high, the write protect bit prevents a write operation to any other register. CLOCK/CALENDAR BURST MODE The clock/calendar command byte specifies burst mode operation. In this mode the eight clock/calendar registers can be consecutively read or written (see Figure 4) starting with bit 0 of address 0. RAM The static RAM is 24 x 8 bytes addressed consecutively in the RAM address space. RAM BURST MODE The RAM command byte specifies burst mode operation. In this mode, the 24 RAM registers can be consecutively read or written (see Figure 4) starting with bit 0 of address 0. 032697 3/11 DS1202, DS1202S REGISTER SUMMARY pins. There is no need for external capacitors or resistors. Note: X1 and X2 are very high impedance nodes. It is recommended that they and the crystal be guard- ringed with ground and that high frequency signals be kept away from the crystal area. For more information on crystal selection and crystal layout considerations, please consult Application Note 58, "Crystal Considerations with Dallas Real Time Clocks". A register data format summary is shown in Figure 4. CRYSTAL SELECTION A 32.768 KHz crystal, can be directly connected to the DS1202 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (CL) of 6 pF. The crystal is connected directly to the X1 and X2 DATA TRANSFER SUMMARY Figure 3 SINGLE BYTE TRANSFER SCLK RST 0 R/W I/O 1 A0 2 A1 3 A2 4 A3 5 6 7 A4 R/C 1 0 1 2 ADDRESS COMMAND 3 4 5 6 7 DATA INPUT/OUTPUT BURST MODE TRANSFER SCLK RST I/O 0 1 R/W 1 2 3 4 5 6 7 1 1 1 1 R/C 1 ADDRESS COMMAND 1 DATA I/O BYTE 1 FUNCTION BYTE N SCLK n CLOCK 8 72 RAM 24 200 032697 4/11 0 2 4 5 6 DATA I/O BYTE N 7 DS1202, DS1202S REGISTER ADDRESS/DEFINITION Figure 4 REGISTER ADDRESS A. CLOCK 7 6 5 REGISTER DEFINITION 4 3 2 1 SEC 1 0 0 0 0 0 0 MIN 1 0 0 0 0 0 1 HR 1 0 0 0 0 1 0 DATE 1 0 0 0 0 1 1 MONTH 1 0 0 0 1 0 0 DAY 1 0 0 0 1 0 1 YEAR 1 0 0 0 1 1 0 CONTROL 1 0 0 0 1 1 1 CLOCK BURST 1 0 1 1 1 1 1 RAM 0 1 1 0 0 0 0 0 RAM 23 1 1 1 0 1 1 1 RAM BURST 1 1 1 1 1 1 1 0 RD 00-59 CH 10 SEC SEC 00-59 0 10 MIN MIN W 01-12 00-23 12/ 24 0 10 A/P W 01-28/29 01-30 01-31 0 0 10 DATE 01-12 0 0 0 10 M 01-07 0 0 0 0 W RD W RD RD RD W RD W RD W 10 YEAR 0-99 RD WP W HR HR DATE MONTH 0 DAY YEAR FORCED TO ZERO RD W B. RAM RD W RD W RAM DATA 0 RAM DATA 23 RD W 032697 5/11 DS1202, DS1202S ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability. (0C to 70C) RECOMMENDED DC OPERATING CONDITIONS PARAMETER MAX UNITS NOTES Supply Voltage VCC SYMBOL MIN 2.0 TYP 5.5 V 1 Logic 1 Input VIH 2.0 VCC+0.3 V 1 +0.3 VIL VCC=2.0V -0.3 Logic 0 Input V 1 VCC=5V -0.3 +0.8 (0C to 70C; VCC = 2.0 to 5.5V*) DC ELECTRICAL CHARACTERISTICS PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage ILI +500 A 6 I/O Leakage ILO +500 A 6 Logic 1 Output VOH V 2 V 3 mA 5 A 4 nA 10 Logic 0 Output Active Supply Current Timekeeping Current Leakage Current VOL ICC ICC1 ICC2 VCC=2V 1.6 VCC=5V 2.4 VCC=2V 0.4 VCC=5V 0.4 VCC=2V 0.4 VCC=5V 1.2 VCC=2V 0.3 VCC=5V 1 VCC=2V 100 VCC=5V 100 *Unless otherwise noted. (tA = 25C) CAPACITANCE PARAMETER Input Capacitance SYMBOL CONDITION TYP MAX UNITS CI 5 pF I/O Capacitance CI/O 10 pF Crystal Capacitance CX 6 pF 032697 6/11 NOTES DS1202, DS1202S AC ELECTRICAL CHARACTERISTICS PARAMETER Data to CLK Setup CLK to Data Hold CLK to Data Delay CLK Low Time CLK High Time CLK Frequency CLK Rise and Fall RST to CLK Setup CLK to RST Hold RST Inactive Time RST to I/O High Z (0C to 70C; VCC = 2.0 to 5.5V*) SYMBOL tDC tCDH tCDD tCL tCH fCLK tR, tF tCC tCCH tCWH tCDZ MIN VCC =2V 200 VCC=5V 50 VCC=2V 280 VCC=5V 70 TYP MAX VCC=2V 800 VCC=5V 200 VCC=2V 1000 VCC=5V 250 VCC=2V 1000 VCC=5V 250 VCC=2V VCC=5V UNITS NOTES ns 7 ns 7 ns 7 8, 8 9 7, ns 7 ns 7 12 7, MHz 7 12 7, 0.5 DC 2.0 VCC=2V 2000 VCC=5V 500 ns VCC=2V 4 VCC=5V 1 VCC=2V 1000 VCC=5V 250 VCC=2V 4 VCC=5V 1 VCC=2V 280 VCC=5V 70 s 7 ns 7 s 7 ns 7 *Unless otherwise noted. 032697 7/11 DS1202, DS1202S TIMING DIAGRAM: READ DATA TRANSFER Figure 5 RESET tCC CLOCK tCDH tCDD tDC tCDZ DATA INPUT/ OUTPUT 0 1 7 COMMAND BYTE TIMING DIAGRAM: WRITE DATA TRANSFER Figure 6 tCWH RESET tCC tCCH tR tCL tF CLOCK tCDH tCH tDC DATA INPUT/ OUTPUT 0 1 7 COMMAND BYTE NOTES: 1. All voltages are referenced to ground. 2. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at VCC=2V, VOH=VCC for capacitive loads. 3. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2V. 4. ICC1 is specified with I/O open, RST set to a logic 0, and clock halt flag=0 (oscillator enabled). 5. ICC is specified with the I/O pin open, RST high, SCLK=2 MHz at VCC=5V; SCLK=500 KHz, VCC=2V and clock halt flag=0 (oscillator enabled). 6. RST, SCLK, and I/O all have 40K pull-down resistors to ground. 7. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time. 8. Measured at VOH=2.4V or VOL=0.4V. 9. Load capacitance = 50 pF. 032697 8/11 DS1202, DS1202S 10. ICC2 is specified with RST, I/O, and SCLK open. The clock halt flag must be set to logic one (oscillator disabled). 11. At power-up, RST must be at a logic 0 until VCC2 volts. Also, SCLK must be at a logic 0 when RST is driven to a logic one state. 12. If tCH exceeds 100 ms with RST in a logic one state, then ICC may briefly exceed ICC specification. DS1202 SERIAL TIMEKEEPER 8-PIN DIP 8 5 PKG B 1 4 A C F K 8-PIN DIM MIN MAX A IN. MM 0.360 0.400 B IN. MM 0.240 0.260 C IN. MM 0.120 0.140 D IN. MM 0.300 0.325 E IN. MM 0.015 0.040 F IN. MM 0.110 0.140 G IN. MM 0.090 0.110 H IN. MM 0.320 0.370 J IN. MM 0.008 0.012 K IN. MM 0.015 0.021 E G D J H 032697 9/11 DS1202, DS1202S DS1202S SERIAL TIMEKEEPER 16-PIN SOIC K G F B H phi L J PKG DIM 1 A C E 16-PIN MIN MAX A IN. MM 0.500 12.70 0.511 12.99 B IN. MM 0.290 7.37 0.300 7.65 C IN. MM 0.089 2.26 0.095 2.41 E IN. MM 0.004 0.102 0.012 0.30 F IN. MM 0.094 2.38 0.105 2.68 G IN. MM H IN. MM 0.398 10.11 0.416 10.57 J IN. MM 0.009 0.229 0.013 0.33 K IN. MM 0.013 0.33 0.019 0.48 L IN MM 0.016 0.406 0.040 1.20 phi 032697 10/11 0.050 BSC 1.27 BSC 0 8 DS1202, DS1202S DS1202S8 8-PIN SOIC 200 MIL K G J B F H 0-8 deg. typ. L 1 PKG C E A 8-PIN DIM MIN MAX A IN. MM 0.203 5.16 0.213 5.41 B IN. MM 0.203 5.16 0.213 5.41 C IN. MM 0.070 1.78 0.074 1.88 E IN. MM 0.004 0.102 0.010 0.390 F IN. MM 0.074 1.88 0.84 2.13 G IN. MM 0.050 BSC 1.27 BSC H IN. MM 0.302 7.67 0.318 8.07 J IN. MM 0.006 0.152 0.010 0.254 K IN. MM 0.013 0.33 0.020 0.508 L IN. MM 0.19 4.83 0.030 0.762 032697 11/11