GANational Semiconductor General Description The 24-pin medium PAL tamily contains four of the most popular PAL architectures with speeds as fast as 4.5 ns maximum propagation delay. Series -7, -5 and -4 devices are manutactured using National Semiconductor's proprie- tary ASPECT II TTL process with highly reliable vertical- fuse programmabie cells. Vertical fuses are implemented using avalanche-induced migration (AiM) technology of- fering very high programming yields and is an extension of National's FAST logic famity. The 24-pin medium PAL fam- ily provides high-speed user-programmable replacements for conventional SS!/MSI logic with significant chip-count reduction. for a wide variety of application-specific functions, including random logic, custom decoders, state machines, etc. By programming the programmable cells to configure AND/OR gate connections, the system designer can implement cus- tom logic as convenient sum-of-products Boolean functions. System prototyping and design iterations can be performed quickly using these off-the-shelf products. A large variety of Programming units and software makes design develop- ment and functional testing of PAL devices quick and easy. The PAL logic array has a total of 20 complementary input Pairs and 8 outputs generated by a single programmable AND gate array with fixed OR-gate connections. Device out- puts are either taken directly from the AND-OR functions (combinatorial) or passd through D-type flip-flops (regis- 28-Lead PLCC Connection Conversion Diagram FAST, PAL and TRI-STATE are register a AM, ASPECT & and PLANTS are a S CG Programmable Array Logic (PAL) 24-Pin Medium PAL Series -7, -5, and -4 PRELIMINARY March 1991 tered). Registers allow the PAL device to implement se- Quential logic circuits. TRI-STATE outputs facilitate busing and provide bidirectiona! |/O capability. The medium PAL family offers a variety of combinatorial and registered output mixtures. On power-up series -7, -5 and -4 devices reset all registers ter preload is also provided to facilitate device testing. Secu- rity fuses can be programmed to prevent direct copying of proprietary logic patterns. Features @ 4.5 ns maximum propagation delay (combinatorial outputs) @ Pin compatible with existing PAL tamilies @ High programming yield and reliability of vertical-fuse AIM technology @ Fully supported by National PLAN software @ Power-up reset for registered outputs @ Register preload facilitates device testing @ User programmable replacement for high speed TTL Logic @ Security fuse prevents direct copying of logic patterns @ High noise immunity DIP package Block DiagramPAL20R8 c+ Hy GH iB) GH PO a Gy poi GH POs Sporn GH POs CH pout CH PO Ee PO) EH rs Be ue p- pue G- 7- S8U8S TW WNIPEW Uld-pz (AW) 9/607] Aesuy ajqeuwesBboig 1901 Newonal Semconductor Corporeton = TL/L/11143 ARO-B20M31/Prmed in U.S. AAbsolute Maximum Ratings (note 1) tf Military/Aerospace specified devices are required, Storage Temperature 65C to + 150C please contact the National Semiconductor Sales Ambient Temperature with Office/Distributors for availability and specifications. Power Applied 65C to + 125C Supply Voltage (Voc) (Note 2) 0.5V to +7.0V Junction Temperature ~65C to + 150C input Voltage (Note 2) 1.5V to +7.0V ESD Tolerance (Note 3) 2000V Off-State Output Voltage (Note 2) 1.5V to +5.5V Czap = 100 pF Input Current (Note 2) 30 mA to +5.0 mA Rzap = 15002 Output Current (Io1) +100 mA Test Method: Human Body Model Test Specification: NSC SOP-5-028 Recommended Operating Conditions Symbol Parameter -7 Commercial 7 Military Units Min Nom Max Min Nom Max Voc Supply Voltage 4.75 5 .25 45 5 .5 Vv Ta Operating Free-Air Temperature 0 25 75 55 125 c tw Clock Pulse Width Low 4 5 ns High 4 ns S| erteodback to Cock 6s 7 ns ty Hold Time of Input after Clock 0 0 ns fox Clock Frequency With Feedback 77 74 MHz (Note 4) Without Feedback 125 100 | MHz Vz Register Preload Control Voitage 9.5 9.75 10.0 9.5 9.75 10.0 Vv Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbol Parameter Test Conditions Min Typ Max Units ViL Low Level Input Voltage (Note 6) 0.8 Vv Vin High Level input Voltage (Note 6) 2 Vv Vic Input Ciamp Voltage Voc = Min, | = 18mA 1.2 Vv Mit Low Level input Current (Note 7) Voc = Max, V; = 0.4V 250 pA lie High Level input Current (Note 7) Voc = Max, V; = 2.4V 25 pA {; Maximm Input Current Voc = Max, V; = 5.5V 100 pA Voi Low Level Output Voltage Voc = Min, Ilo. = 24 mA 0.5 Vv Vou High Level Output Vottage Voc = Min, lon = ~3.2 mA 2.4 Vv lozt Low Level Off-State Output Voc = Max, Vo = 0.4V -50 yA Current (Note 7) lozH High Level Off State Output Voc = Max, Vo = 2.4V 50 wA Current (Note 7) los Output Short-Circuit Comm Voc = 5.0V, Vo = 0.5V 50 130 mA Current (Note 8) Mil Voc = 5.5V, Vo = 0.5V 50 ~200 ioc Supply Current Voc = Max, Outputs Open 125 210 mA Cc Input Capacitance Voc = 5.0V, V; = 2.0V pF Co Output Capacitance Voc = 5.0V, Vo = 2.0V pF Cio 1/0 Capacitance Voc = 5.0V, Vizo = 2.0V pFElectrical Characteristics over Recommended Operating Conditions (Continued) Note 1: Absolute maximum ratings are those values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the Note 2: Some device pins may be raised above these limits during programming and preload operations according to the applicable specification. Note 3: Vo must not exceed Voc + 1V. Note 4: {o.x with feedback is derived as (ic.x + tgy) 1. fo.K without feedback is derived as (2 t,) 1. Note S: All typical values are for Voc = 5.0V and T, = 25C. Note 6: These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. Note 7: Leakage current for bidirectional i/O pins is the worst case between Ik. and loz, or between iy, and iozH. Note &: To avoid invalid readings in other parameter tests it is preferable to conduct the Igg test last To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 sec. each. Prolonged shorting of a high output may rarse the chip temperature above normal and permanent damage may resuit. Switching Characteristics over Recommended Operating Conditions Symbol! Parameter Test Conditions -7 Commercial 7 Military Units Min | Typ | Max | Min | Typ | Max tep Input or Feedback to Cy = 50 pF, | 4 Output Switching (DIP) 7 ns Combinatorial Output S1 Closed 8 Output Switching (DIP) 7 75 ns PLCC 7 ns tok Clock Input to Registered, C, = 50 pF, S1 Closed Output or Feedback 3 6.5 6.5 ns tezxg | G Pinto Registered C. = 50 pF, Active High: $1 Open, 7 75 ns Output Enabled Active Low: S1 Closed . tpxza | G Pin to Registered CL = 5 pF, From Voy: S1 Open, 7 75 | ns Output Disabled From Vo,: $1 Closed . tpzx) Input to Combinatorial Output | C_ = 50 pF, Active High: S1, Open, 7 75 ns Enabled via Product Term Active Low: S1 Closed . texz| Input to Combinatorial Output | C_ = 5 pF, From Vox: Si Open, 7 75 ns Disabled via Product Term From Vo: S1 Closed , treset | Power-Up to Registered Output Low 1000 1000 ns Test Load vo" oo $1 OUTPUT rs AAA we = = A > * L i " _ TL/L/11443~-3 MIL COMM R1 = 3900 Ri = 2000 R2 = 7500 R2 = 390Schematic of Inputs and Outputs EQUIVALENT INPUT TYPICAL OUTPUT Yee oO 0 Yor 12kQ NOM. S400 Now. q , ~ OUTPUT Xai _ A TU/L/11143-4Absolute Maximum Ratings (note 1) Hf Milltary/Aerospace specified devices are required, Storage Temperature 65C to + 150C please contact the National Semiconductor Sales Ambient Temperature with Office/Distributors for avaliability and specifications. Power Applied 65C to +125C Supply Voltage (Vcc) (Note 2) 0.5V to +7.0V Junction Temperature -~65C to + 150C Off-State Output Voltage (Note 2) 1.5V to + 5.5V Czap = 100 pF input Current (Note 2) 30 mA to +5.0 mA Rzap = 15002 Output Current (Io,) +100 mA Test Method: Human Body Model Test Specification: NSC SOP-5-028 Recommended Operating Conditions -5 Com <4 mercial Symbol Parameter 5 mercial Commercial | Units Min Nom Max Min Nom Max Voc Supply Voltage 4.75 5 .25 4.75 5 .25 Vv Ta Operating Free-Air Temperature 0 25 75 0 25 75 c tw Clock Pulse Width Low 4 4 ns High 4 4 ns tsu Setup Time from Input 4 4 ns or Feedback to Clock ty Hold Time of input after Clock 0 0 ns fox Clock Frequency With Feedback 111 118 MHz (Note 4) Without Feedback 125 125 | MHz Vz Register Preload Control Voltage 9.5 9.75 10.0 9.5 9.75 10.0 Vv Electrical Characteristics over Recommended Operating Conditions (Note 5) Symbo! Parameter Test Conditions Min Typ Max Units Vit Low Level Input Voltage (Note 6) 0.8 Vv Vin High Level Input Voltage (Note 6) 2 Vv Vic input Clamp Voltage Voc = Min, | = -18mA 1.2 Vv hie Low Level tnput Current (Note 7) Voc = Max, V; = 0.4V 250 pA lie High Level Input Current (Note 7) Voc = Max, V; = 2.4V 25 pA I Maximum Input Current Voc = Max, V; = 5.5V 100 pA VoL Low Level Output Voltage Voc = Min, lo, = 24 mA 0.5 Vv VoH High Level Output Voltage Voc = Min, low = 3.2mA 2.4 Vv Joze Low Level Off-State Output Voc = Max, Vo = 0.4V ~50 mA Current (Note 7) lozH High Level Off State Output Voc = Max, Vo = 2.4V 50 Current (Note 7) pA los Output Short-Circuit Voc = 5.0V, Vo = 0.5V _ _ Current (Note 8) 50 130 mA loc Supply Current Voc = Max, Outputs Open 125 210 mA Ci Input Capacitance Voc = 5.0V, V; = 2.0V pF Co Output Capacitance Voc = 5.0V, Vo = 2.0V pF Cvo \/O Capacitance Voc = 5.0V, Vivo = 2.0V pFElectrical Characteristics over Recommended Operating Conditions (Continued) Note 1: Absolute maximum ratings are thoes values beyond which the device may be permanently damaged. Proper operation is not guaranteed outside the epeciied recommended operating conditions. Mote 2: Some device pins may be raised above these limits during programming end preiced operations according to the applicable specification. Note 2: Vo must not exceed Voc + 1V. Note 4: (o. x with feedback is derived a3 (icix + tgu)'. io.x without feedback is derived as (2 ty)-'. Mote S: All typical values are for Voc = 5.0V and Ta = 25C. Mote 6: These are absolute voltages with respect to the ground pin on the device and include all overshoots dus to system and/or tester noise. Do not attempt to teat these values without suitable equipment. Note 7: Leakage current for bidirectional 1/O pins is the worst case between iy, and io7, or between ly, and lozn. Note 8: To avoid invalid readings in other parameter tests i is preferable to conduct the igs test last. To minimize internal heating, only one output should be shorted at a time with a maximum duration of 1.0 sec. each Prolonged shorting of a high output may raise the chip temperature above normel and permanent damage may reeutt. Switching Characteristics over Recommended Operating Conditions Symbol Parameter Test Conditions 5 4 orcs Units Min | Typ | Max | Min | Typ | Max tep input or Feedback to "| C. = 50pF, | 4 Output Switching (DIP) 5 ns PLCC 5 45 ns tok Clock input to Registered C. = 50 pF, S1 Closed 5 4s ns Output or Feedback . tezxg | G Pin to Registered Cy = 50 pF, Active High: S1 Open, 5 as | ns Output Enabled Active Low: S1 Closed . texzq | G Pin to Registered CL = 5 pF, From Voy: S1 Open, 5 4s ns Output Disabled From Vo,: $1 Closed . tpzx! input to Combinatorial Output | C_ = 50 pF, Active High: S1, Open, 5 45 ns Enabled via Product Term Active Low: S1 Closed . texzi Input to Combinatorial Output | C, = 5 pF, From Vqy: S1 Open, 5 45 ns Disabled via Product Term From Vo,: S1 Closed . tacser | Power-Up to Registered 0 Low 1000 1000] ns Test Load Schematic of inputs and Outputs EQUIVALENT INPUT TYPICAL OUTPUT vo te 0 Ye 3 RI , > > 3 120 NOM. > 400 Nou. 4 om $+ , , Tl i no TL/L/11143-5 R1 = 2000 R2 = 2000 PO OUTPUT TLL/11143-6 V 8 ult tlfTest Waveforms Set-Up and Hold Pulee Width wv 3v CLOCK Ky, HIGH@LEVEL wy. ov PULSE INPUT T , tgetaup two by DATA yV av sv ov PULSE INPUT an TL/L/11943-7 ow TL/L/11143-9 Propagation Delay Enable and Disable 3v wp wPUT v; ENABLE Vr DISABLE UT ENABLING x T 7 ov IN-PHASE WORMALLY HIGH Voy, 7 i Osv (S1 CLOSED) (st OPEN) 2 ' No OUT OF PHASE NORMALLY LOW 7 po fez, fouz OUTPUT OUTPUT KYr asv (S1 CLOSED) (st cuosen) You | TLUL/11143-8 TL/L/11143-10 Notes: Vy = 1.5V C, includes probe and jig capacitance. in the examples above, the phase reiationships between inputs and outputs have been chosen arbitrarily. Switching Waveforms . weurs KOK _VaLo wPUT_ KRXKKKKVAD PUTER KK KKK VALD MPUTR KKK ORRIN ty ot ty-- REGISTERED xX PROGRAMMED us osasus XK _VALID ENABLE FOR TRIESTATE CONTROL ] ten ean le torn OUTPUTS K \ eel oe TL/L/11143~-11 Power-Up Set/Reset Waveform ov REGISTERED ouTPuTs EL (6 Low) INTERNAL REGISTERS RESET TO LOGIC 0 Vou tser coon XLT Vv . TLUL/11143-12 *The clock input should not be switched trom low to high until after time tgescr oF tect.Functional Description All of the 24-pin medium PAL logic arrays consist of 20 com- plementary input fines and 64 product-term lines with a pro- grammabie cell at each intersection (2560 cells). The prod- uct terms are organized into eight groups of eight each. Seven or eight of the product terms in each group connect into an OR-gate to produce the sum-of-products logic func- tion, depending on whether the output is combinatorial or registered. In the National Series -7, -5 and -4 vertical fuse (AIM) PAL devices, a programmed vertical fuse cell establishes a con- nection between an input line and a product term. A product term is satisified (logically true) while all of the input lines connected to it (via unprogrammed fuses for the fuse-tink devices, or by programming the corresponding cells for the vertical fuse devices) are in the high logic state. Therefore, if both the true and complement of at least one array input is connected to a product fine, that product term is always held in the low logic state (which is the state of all product terms in an unprogrammed fuse-link device). Conversely, if all input lines are disconnected from a product line, the Product term and the resulting logic function would be held in the high state (which is the state of all product terms in an unprogrammed National -7, -5 and -4 PAL device). For more information on vertical fuse technology, consult our applica- tion note #594. The medium PAL family consists of four device types with differing mixtures of combinatorial and registered outputs. The 20L8, 20R4, 20R6 and 20R8 architectures have 0, 4, 6 and 8 registered outputs respectively, with the balance of the 8 outputs combinatorial. All outputs are active-low and have TRI-STATE capability. Each combinatorial output have a seven product-term logic function, with the eighth product term being used for TRI- STATE control. A combinatorial output is enabled while the TRI-STATE product term is satisfied (true). Combinatorial outputs also have feedback paths from the device pins into the logic array (except for two outputs on the 20L8). This allows a pin to pertorm bidirectional I/O or, if the associated TRI-STATE contro! product term were programmed to re- main unsatisified (always false), the output driver would re- main disabled and the pin could be used as an additional dedicated input. Voc 3.0V Registered outputs each have an eight product-term logic function feeding into a D-type flip-flop. All registers are trig- gered by the high-going edge of the clock input pin. All reg- istered outputs are controlled by a common output enable (G) pin (enabled while low). The output of each register is also fed back into the logic array via an intemal! path. This provides for sequential logic circuits (state machines, count- ers, etc.) which can be sequenced even while the outputs are disabled. Series -7, -5 and -4 medium PAL devices reset all registers to a low state upon power-up (active-low outputs assume high logic levels if enabled). This may simplify sequentia! circuit design and test. To ensure successful power-up re- set, Voc must rise monotonically until the specified operat- ing voltage is attained. During power-up, the clock input should assume a valid, stable logic state as early as possi- ble to avoid interfering with the set or reset operation. The clock input should also remain stable until after the power- up reset operation is completed to allow the registers to capture the proper next state on the first high-going clock transition. During power-up, all outputs are held in the high-impedance state until DC power supply conditions are met (Voc approx- imatety 3.0V), after which they may be enabled by the TRI- STATE control product terms (combinatorial outputs) or the G pin (registered outputs). Whenever Voc goes below 3V (at 25C), the outputs are disabled as shown in Figure 7 below. In an unprogrammed National Series -7, -5 and -4 PAL de- vices, no array inputs are connected to any product-term lines. Therefore, all combinatorial outputs would be enabled and driving low logic levels (after power-up is completed). All registers would still initialize to the low state, but would become permanently set (low-level outputs, if enabled) fol- As with any TTL logic circuits, unused inputs to a PAL de- vice should be connected to ground, Vo_. Vou, or resistive- ly to Voc. However, switching any input not connected to a product term or logic function has no effect on its output logic state. > wm FIGURE 1. Power-Up TRI-STATE Waveform TELS 11143-1324-Pin Medium PAL Family Block DiagramsDIP Connections PAL20L8 wT GAA Thal [a}= LIER LGR CIEE IG PIER CER fl G- CER PIER 3} [] | I >12] [=] al [2] al [+] al [2] poeple amen lee FO Bh Poet > bE rd fv] | [] EU a {) | eee I PAL20R6 TUU/11143~14 ww LG > ad fa) DIGH LGR GIGK PIER CER =o 0] EH fe 7oloe WG Pegs bo lee lop Lop yey yy Y | [3] {>} : 2] [=] [a] [=] [=] [24] fe} [2] he] [x] [7] {x} 6} [] [2] Gi PD | 3] [uJ] b) EE Ld ~[) Bi fo) Leta] [1] # eee TL/L/11143-16 cg> CGH | Fay fs} GH DIGE CEH bIGH O1EK Sh > fal le fo fH WG [el EH 3) [) | fz} [x] nok pts) pte [x] fal [+] re) [0] rs) [re] fo] GE [4] Gh [>] Leta fu) Lyd TL/L/11143-15 LoS Thad fa} PIER | 7oloe bIEE C1EK DIGE C]EE i GK hGH HEH PI EK [4 Gf me po [=] peta] [=] peta] [] petal [x] Lp-tal [+] petal [x] tpt] [1] pa) [] a fo) <piis {vs] Ace Fe ERS, TLL/11943-17Functional Description (continued) Typical Registered Logic Function without Feedback TL/L/11143-18 Typical Registered Logic Function with Feedback Clock Frequency Specification The clock frequency (fc_x) parameter specifies the maxi- mum speed at which a registered PAL device is guaranteed to operate. Clock frequency is defined differently for the two cases in which register feedback is used versus when it is not in a data-path type application, where the logic func- tions fed into the registers are not dependent on register feedback from the previous cycle (i.e., based only on exter- nal inputs) the minimum required cycle period (fo. ~ 1 with- out feedback) is defined as the greater of the minimum clock period (ty high + t, low) and minimum data win- dow period (tsy + t). This assumes optimal alignment between data inputs and the clock input. In sequential logic applications such as state machines, the minimum required cycle period (fcoix1 with feedback) is defined as toy, + tgy. This provides sufficient time for outputs from the regis- ters to feed back through the logic array and set-up on the inputs to the registers before the end of each cycle. Output Register Preload This feature simplifies device testing since any state may be loaded into the registers at any time during the functional test sequence. This allows complete verification of sequen- tial logic circuits, including states that are normally impossi- ble or difficult to reach. Register preload is not an operation- al mode and is not intended for board level testing because elevated voltage levels are required. The programming sys- tem normally provides the preload capability as part of its functional! test facility. The preload function allows the registers to be loaded di- rectly and asynchronously with any desired pattern. These vertical-fuse devices provide two register preload opera- tions: 1. All registers can be reset to the low state (high-level out- puts) by applying the elevated control voltage (Vz) to input pin 2 for time to (Figure 2a). TL/L/11143~19 2. Selected registers can be set to the high state (low-level! outputs) as follows (Figure 2b). a. All registered outputs are disabled by raising G input pin 1 to Vin. b. After time tp, the selected registered output pins are raised to the elevated contro! voltage (Vz) for time tp to set the corresponding register. Security Fuse Security fuses are provided on all National PAL devices of verifying operations. This feature prevents direct copying of proprietary logic patterns. The security fuses should be programmed only after programining and verifying all other _ device fuses. Register preload is not affected by the securi- ty fuses. Design Development Support A variety of software tools and industry standard program- ming hardware is available to support the development of designs using PAL products. Typical software packages ac- cept Boolean togic equations to define desired functions. Most are available to run on personal computers and gener- ate JEDEC-compatibie fuse maps. The industry-standard JEDEC format ensures that the resutting fuse-map files can be down-loaded into a variety of programming equipment. Many software packages and programming units support a multitude of programmable logic products as well. PLAN software package from National Semiconductor supports all of our programmable logic products and is fully JEDEC- compatible. 10Design Development Support (Continued) In National Series -7, -5 and -4 devices, logical and physical fines are established when vertical fuse cells are pro- grammed. This is opposite to other PAL products based on fusible links in which connections are established when fus- es are left unprogrammed (intact). This difference is com- pensated by the vertical-fuse PAL programming algorithm so that the user's design development process looks the same. (The only functional difference due to vertical-fuse technology is the behavior of unprogrammed devices.) The JEDEC programming maps produced by PAL develop- ment software for all Medium PAL devices denote a con- nection with a o", and a non-connection with a 1. The programming algorithms for most fuseink PLDs pro- gram fuses where ones are located in the map to remove corresponding connections, whereas the algorithm for Na- tional Series PAL -7, -5 and -4 products automatically com- pensates by programming vertical-fuse cells where zeroes are located in the map to establish connections. Therefore, the same JEDEC map representing the user's desired logic Functional Description (Continued either PAL technology. The user need only provide the ap- propriate device code and/or adapter for the programming equipment to invoke the proper programming aigorithm. PAL programming algorithm should be used to program these vertical-fuse devices. Detailed logic diagrams showing all JEDEC fuse-map ad- dresses for the 24-pin medium PAL family are provided for direct map editing and diagnostic purposes. The DIP and PLCC package for -7, -5 and -4 series are pin for pin re- placements for all slower 24-pin medium PAL devices (A, B and D Series). The non-connected (NC) pins on the PLCC package are utilized in the -4 series as extra power and ground pins (Vcc and GND) to provide better noise immuni- ty at high switching speeds. For a list of current software and programming support tools available for theses devic- es, please contact your local National Semiconductor sales representative or distributor. if detailed specifications of the PAL programming algorithm are needed, please contact the partment. PIN 2 Va t ALL REGISTERED Vou OUTPUTS / / / Yo. : TL/L/11143-20 a) To Reset All Registers Vu G (PIN 11) ty AA Va SELECTED reGisTeReD YOH / \ OUTPUT PINS y OL le ty o TL/L/11143-21 b) To Set Selected Registers Note: Vz = 9.5V to 10.0V, tp min. = 500 ns FIGURE 2. Register Preioad Waveforms 11Ordering Information PAL 20 AR 8 Programmable Array Logic Family Number of Array inputs Output Type L = Active Low R = Registered Number of Registered Outputs (or Total Outputs if Non-Registered) Speed Version: 7 =7ns 5 = 5ns -4 = 4.5 ns (PLCC Only) Packaging Type N = 24-Pin Plastic DIP J = 24-Pin Ceramic DIP V = 26-Lead Plastic Chip Carrier M = Military (55C to + 125C) Temperature Range [ C = Commercial (0C to + 75C) N Cc 12Logic DiagramPAL20L8 OP PIN NUMBERS INPUT LUNE DIP PIN NUMBERS PRODUCT LINE FIRST CELL NUMBERS NUMBERS } Vv ce 1 CH 0 2 46 8 10 1214 1618 2022 2426 2830 36 1 17 1 9 1 23 21 19 18 17 16 15 10 14 11 13 ol2i4 12hal1 2] 135 7 9 14 1315 1719 2123 2527 2931 3335 3739 TL/L/11149-22 JEDEC Logic Array Cel Number = Product Line First Cell Number + input Line Number 13Logic DiagramPAL20R4 DIP PIN NUMBERS INPUT UNE OP PIN NUMBERS PRODUCT LINE FIRST CELL NUMBERS NUMBERS Vec | C21. 0 2 4 6 8 10 1214 1618 2022 2426 2830 34517 1 9 { 23 21 20 18 17 16 15 10 "1 14 416 { 2 12. 135 7 9 14 1315 1719 2123 2527 2931 3335 3739 1s TL/L/11143=23 JEDEC Logic Array Cell Number = Product Line First Cell Number + input Line Number 14Logic DiagramPAL20R6 DIP PIN NUMBERS WNPUT LINE DIP PIN NUMBERS { PRODUCT LINE FIRST CELL NUMBERS NUMBERS Vec 2 ' 0 2 4 6 8 10 1214 1618 2022 2426 2830 3234 3638 143 95,7 [9911 5 9 1 23 22 21 20 19 18 17 16 15 10 11 14 ol2) all slrol rivals 2 12)_ 135 7 9 11 1315 1719 2123 2527 2931 3335 3739 1S TL/L/11143-24 JEDEC Logic Array Cell Number = Product Line First Cell Number + input Line Number 15Logic Diagram-PAL20R8 DIP PIN NUMBERS ~ WPUT LINE DIP PIN NUMBERS { PRODUCT LINE FIRST CELL NUMBERS NUMBERS Vv, } 1 Sto 02-46 8 10 12 14 16.18 20.22 2426 28 30 3234 36.38 23 21 20 19 18 17 16 15 10 11 14 101 12I14l 1 2 12". 13-57 911 1315 1719 2123 2527 29 31 3335 3739 1s TL/L/11143-25 JEDEC Logic Array Cell Number = Product Line First Cell Number + input Line Number 16Physical Dimensions inches (mitimeters) ans 1280 ins) 9 Gar PL fez) [25] fee) fie) fie] fr] fie) fis] fra] i) 0318 max 0.285 (2.901) GLASS (7.483) MAX 4d A. (ta7e2-1.397) RAO TvP GLASS 0.956 18.005 O290-6.328 an iizesanm | smears (7386-4.128) (0.Se8 1.778) im { 0.275 (4872) (6.715) MAX MAX 7 t eke TTT fe& esm-en2 TvP) Typ gees MAX 100 se.010 | acts :0.083 tra aeo || A125 L 0310-0410 | BOTH 79 GA ob Dai - an 2TH L cm aaa (eas) c8.078 aim a8) (77-1041) aera 24-Pin Narrow Ceramic Dual-in-Line Package (J) NS Package Number J24F 8.200+0.005 (e0o0ze.iz7) 0.300-6.320 (7.62 ~8.128) 0.1307 6.005 (3.502 6.127) | 020 0.1450.208 (sos) (3.683 6.008) 0.985 ! 0.125 -0.145 : (7. 6.018 + 0.003 1753588 35 vans mn imsiesn | L aasrze: sae + (28 15) 8.10020.010 90 TP 2.546.256) We 24-Pin Narrow Piastic Dual-in-Line Package (N) NS Package Number N24C 170.410-0.698 (aan 10.82) (CONTACT paexsiOn Physical Dimensions inches (mitimeters) (Continued) 0.028 0.0138.018 ecsz0.0e (8.508) a 7 8.165-0.108 {0.513 -1.618) mm 7 oe (en 4572) prt 3 6. oa (12.32 - 12.87) SQUARE LIFE SUPPORT POLICY Programmable Array Logic (PAL) 24-Pin Medium PAL Series -7, -5, and -4 SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when property used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury (0.127 -0.381) Pawo. + il 0.075 0.822, t 0.164 -0.118 eaneny (2.662 2.997) VaBA (REV 28-Lead Plastic Chip Carrier Package (V) NS Package Number V28A NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. to the user. National Semicenducter Netonal Semicenducter Melienal Semicenducter ational Semicenduster National Semicondteres National Semicenducter Corporation Gna dapen Lad. Heng Heng Lod. Deo Greeti Lode. (Asstraiia) PTY, Lod. 2900 Semiconductor Orive (ndusticstresse 10 Seneeide Bldg. SF Suhe 613, Sh) Floor Av. Brig. Faria Lima, 1383 tat Floor, 441 St Kade Ad. P.O. Box $8000 . 0.8080 Furstenteidbruck 4-15 Nishi Shinju Ctinachem Golden Plaza, 6.0 Andor-Conj. 2 Melbourne, 3004 Santa Clara, CA 95052-6000 West Germany Srinkte-Ku, 7? Mody Road, Temmehatei East, 01451 Sao Pato, SP, Brasil Victory, Austraie Tet 1(800) 272-0060 Tek (0-81-41) 103-0 Tokyo 100, Japan Keatoon, Hong Kang Tet (S5/11} 212-5086 Tet (2%) 267-4000 TWX: (910) 330-0240 Tole: 527-648 Tet 3200-7001 Tet 3-7231290 Fac (55/11) 211-1181 NSBR BR | Fax 61-3-2877488 Fac 08141) 109654 FAX: 3-290-7000 Telex: S2006 NSSEA HX Fax 33112538 National Goss not assume any reeponsibility for wee of any cirowiry described, no circuit patent onphed and the right at any tine without notce w change eaid clroulty and specifications.