CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
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SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
CD74HCT4052, CD54/74HC4053, CD54/74HC54053
HIGH-SPEED CMOS LOGIC ANALOG MULTIPLEXERS/DEMULTIPLEXERS
Check for Samples: CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
1FEATURES Direct LSTTL Input Logic Compatibility
VIL = 0.8 V Max, VIH = 2 V Min
Wide Analog Input Voltage Range. . ±5 V Max
CMOS Input Compatibility
Low ON Resistance II1μA at VOL, VOH
70 ΩTypical (VCC VEE = 4.5 V)
40 ΩTypical (VCC VEE = 9 V) DESCRIPTION
Low Crosstalk Between Switches These devices are digitally controlled analog switches
Fast Switching and Propagation Speeds which utilize silicon gate CMOS technology to
Break-Before-Make Switching achieve operating speeds similar to LSTTL with the
low power consumption of standard CMOS integrated
Wide Operating Temperature Range circuits.
55°C to 125°CThese analog multiplexers/demultiplexers control
CD54HC/CD74HC Types analog voltages that may vary across the voltage
Operation Control Voltage . . . . . . 2 V to 6 V supply range (i.e., VCC to VEE). They are bidirectional
SwitchVoltage..............0Vto10V switches thus allowing any analog input to be used as
«an output and vice-versa. The switches have low ON
resistance and low OFF leakages. In addition, all
CD54HCT/CD74HCT Types three devices have an enable control which, when
Operation Control Voltage . . . 4.5 V to 5.5 V high, disables all switches to their OFF state.
SwitchVoltage...............0Vto10
VORDERING INFORMATION(1)
TEMP. RANGE
PART NUMBER PACKAGE
(°C)
CD54HC4051F3A 55 to 125 16 Ld CERDIP
CD54HC4052F3A 55 to 125 16 Ld CERDIP
CD54HC4053F3A 55 to 125 16 Ld CERDIP
CD54HCT4051F3A 55 to 125 16 Ld CERDIP
CD74HC4051E 55 to 125 16 Ld PDIP
CD74HC4051M 55 to 125 16 Ld SOIC
CD74HC4051MT 55 to 125 16 Ld SOIC
CD74HC4051M96G3 55 to 125 16 Ld SOIC
CD74HC4051NSR 55 to 125 16 Ld SOP
CD74HC4051PWR 55 to 125 16 Ld TSSOP
CD74HC4051PWT 55 to 125 16 Ld TSSOP
CD74HC4052E 55 to 125 16 Ld PDIP
CD74HC4052M 55 to 125 16 Ld SOIC
CD74HC4052MT 55 to 125 16 Ld SOIC
CD74HC4052M96G3 55 to 125 16 Ld SOIC
CD74HC4052NSR 55 to 125 16 Ld SOP
CD74HC4052PW 55 to 125 16 Ld TSSOP
CD74HC4052PWR 55 to 125 16 Ld TSSOP
(1) When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of
250.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. ©19972011, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
ORDERING INFORMATION(1) (continued)
TEMP. RANGE
PART NUMBER PACKAGE
(°C)
CD74HC4052PWT 55 to 125 16 Ld TSSOP
CD74HC4053E 55 to 125 16 Ld PDIP
CD74HC4053M 55 to 125 16 Ld SOIC
CD74HC4053MT 55 to 125 16 Ld SOIC
CD74HC4053M96G3 55 to 125 16 Ld SOIC
CD74HC4053NSR 55 to 125 16 Ld SOP
CD74HC4053PW 55 to 125 16 Ld TSSOP
CD74HC4053PWRG3 55 to 125 16 Ld TSSOP
CD74HC4053PWT 55 to 125 16 Ld TSSOP
CD74HCT4051E 55 to 125 16 Ld PDIP
CD74HCT4051M 55 to 125 16 Ld SOIC
CD74HCT4051MT 55 to 125 16 Ld SOIC
CD74HCT4051M96 55 to 125 16 Ld SOIC
CD74HCT4052E 55 to 125 16 Ld PDIP
CD74HCT4052M 55 to 125 16 Ld SOIC
CD74HCT4052MT 55 to 125 16 Ld SOIC
CD74HCT4052M96 55 to 125 16 Ld SOIC
CDHCT4053E 55 to 125 16 Ld PDIP
CDHCT4053M 55 to 125 16 Ld SOIC
CDHCT4053MT 55 to 125 16 Ld SOIC
CDHCT4053M96 55 to 125 16 Ld SOIC
CDHCT4053PWR 55 to 125 16 Ld TSSOP
CDHCT4053PWT 55 to 125 16 Ld TSSOP
2Submit Documentation Feedback ©19972011, Texas Instruments Incorporated
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
CD54HC4051, CD54HCT4051
(CERDIP)
CD74HC4051
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4051
(PDIP, SOIC)
TOP VIEW
CD54HC4052
(CERDIP)
CD74HC4052
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4052
(PDIP, SOIC)
TOP VIEW
CD54HC4053
(CERDIP)
CD74HC4053
(PDIP, SOIC, SOP, TSSOP)
CD74HCT4053
(PDIP, SOIC, TSSOP)
TOP VIEW
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
A4
A6
A
A7
A5
E
GND
VEE
VCC
A1
A0
A3
S0
S1
S2
A2
CHANNEL
IN/OUT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
COM OUT/IN
ADDRESS
SELECT
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B0
B2
BN
B3
B1
E
GND
VEE
VCC
A1
AN
A0
A3
S0
S1
A2 CHANNEL
IN/OUT
CHANNEL
IN/OUT
CHANNEL
IN/OUT
COM OUT/IN
CHANNEL
IN/OUT
COM OUT/IN
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
B1
B0
C1
CN
C0
E
GND
VEE
VCC
AN
A1
A0
S0
S1
S2
BN
CHANNEL
IN/OUT
IN/OUT
COM OUT/IN CHANNEL
IN/OUT
COM OUT/IN
COM OUT/IN
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
www.ti.com
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
TG
TG
TG
TG
TG
TG
TG
3A
COMMON
OUT/IN
BINARY
TO
1 OF 8
DECODER
WITH
ENABLE
11
10
9
6E
S2
S1
S0
LOGIC
LEVEL
CONVERSION
8 7
GND VEE
16
VCC
131415121524
A7A6A5A4A3A2A1A0
CHANNEL IN/OUT
TG
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
FUNCTIONAL DIAGRAM OF HC/HCT4051
Table 1. TRUTH TABLE
'HC/CD74HCT4051(1)
INPUT STATES ON CHANNELS
ENABLE S2S1S0
L L L L A0
L L L H A1
L L H L A2
L L H H A3
L H L L A4
L H L H A5
L H H L A6
L H H H A7
H X X X None
(1) X = Don't care
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Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
TG
TG
TG
TG
TG
TG
TG
TG
13 COMMON A
OUT/IN
BINARY
TO
1 OF 4
DECODER
WITH
ENABLE
10
9
6E
S1
S0
LOGIC
LEVEL
CONVERSION
16
VCC
4251
B0B1B2B3
B CHANNELS IN/OUT
3COMMON B
OUT/IN
8 7
GND VEE
12141511
A3A2A1A0
A CHANNELS IN/OUT
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
www.ti.com
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
FUNCTIONAL DIAGRAM OF HC4052, CD74HCT4052
Table 2. FUNCTION TABLE
'HC4052, CD74HCT4052(1)
INPUT STATES ON CHANNELS
ENABLE S1S0
L L L A0, B0
L L H A1, B1
L H L A2, B2
L H H A3, B3
H X X None
(1) X = Don't care
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
TG
TG
TG
TG
TG
TG
14
11
10
9
6E
S2
S1
S0
7
GND VEE
16
VCC
15
C COMMON
OUT/IN
4
B COMMON
OUT/IN
A COMMON
OUT/IN
LOGIC LEVEL
CONVERSION
BINARY TO
1 OF 2
DECODERS
WITH ENABLE 12132153
C1C0B1B0A1A0
IN/OUT
8
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
FUNCTIONAL DIAGRAM OF 'HC4053, CD74HCT4053
Table 3. FUNCTION TABLE
'HC4053, CD74HCT4053(1)
INPUT STATES ON CHANNELS
ENABLE S0S1S2
L L L L C0, B0, A0
L H L L C0, B0, A1
L L H L C0, B1, A0
L H H L C0, B1, A1
L L L H C1, B0, A0
L H L H C1, B0, A1
L L H H C1, B1, A0
L H H H C1, B1, A1
H X X X None
(1) X = Don't care
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SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
Absolute Maximum Ratings(1) (2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VCC VEE DC supply voltage 0.5 10.5 V
VCC DC supply voltage 0.5 7 V
VEE DC supply voltage 0.5 7 V
IIK DC input diode current VI< 0.5 V or VI>VCC + 0.5 V ±20 mA
IOK DC switch diode current VI<VEE 0.5 V or VI>VCC + 0.5 V ±20 mA
DC switch current VI>VEE 0.5 V or VI<VCC + 0.5 V ±25 mA
ICC DC VCC or ground current ±50 mA
IEE DC VEE current 20 mA
E (PDIP) package 67
M (SOIC) package 73
θJA Package thermal impedance(3) °C/W
NS (SOP) package 64
PW (TSSOP) package 108
Maximum junction temperature 150 °C
Maximum storage temperature range 65 150 °C
Maximum lead temperature (soldering 10 s) 300 °C
(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to GND unless otherwise specified.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
For maximum reliability, nominal operating conditions should be selected so that operation is always within the following
ranges. PARAMETER MIN MAX UNIT
CD54/74HC types 2 6
Supply voltage range
VCC (1) V
(TA= full package temperature range) CD54/74HCT types 4.5 5.5
Supply voltage range CD54/74HC types, CD54/74HCT types
VCC VEE 2 10 V
(TA= full package temperature range) (see Figure 1)
Supply voltage range CD54/74HC types, CD54/74HCT types
VEE (2) 06 V
(TA= full package temperature range) (see Figure 2)
VIDC input control voltage GND VCC V
VIS Analog switch I/O voltage VEE VCC V
TAOperating temperature 55 125 °C
2 V 0 1000
tr, tfInput rise and fall times 4.5 V 0 500 ns
6 V 0 400
(1) All voltages referenced to GND unless otherwise specified.
(2) In certain applications, the external load resistor current may include both VCC and signal line components. To avoid drawing VCC
current when switch current flows into the transmission gate inputs, the voltage drop across the bidirectional switch must not exceed
0.6 V (calculated from rON values shown in Electrical Specifications table). No VCC current will flow through RLif the switch current flows
into terminal 3 on the HC/HCT4051; terminals 3 and 13 on the HC/HCT4052; terminals 4, 14, and 15 on the HC/HCT4053.
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
HCT
VCC − GND (V)
VCC − VEE (V)
8
6
4
2
00 2 4 6 8 10 12
HC
HCT
VCC − GND (V)
VEE − GND (V)
8
6
4
2
00 −2 −4 −6 −8
HC
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
Recommended Operating Area as a Function of Supply Voltages
Figure 1. Figure 2.
DC Electrical Specifications AMBIENT TEMPERATURE, TA
TEST CONDITIONS 40°C to 55°C to
25°C
PARAMETER 85°C 125°C UNIT
VIS VIVEE VCC MIN TYP MAX MIN MAX MIN MAX
(V) (V) (V) (V)
HC Types
2 1.5 1.5 1.5
VIH High-level input voltage 4.5 3.15 3.15 3.15 0 V
6 4.2 4.2 4.2
2 0.5 0.5 0.5
VIL Low-level input voltage 4.5 1.35 1.35 1.35 V
6 1.8 1.8 1.8
0 4.5 70 160 200 240
VCC or VEE 0 6 60 140 175 210
IO= 1 mA 4.5 4.5 40 120 150 180
rON ON resistance (see VIL or VIH Ω
0 4.5 90 180 225 270
Figure 11) VCC to VEE 0 6 80 160 200 240
4.5 4.5 45 130 162 195
0 4.5 10
Maximum ON resistance
ΔrON 0 6 8.5 Ω
between any two channels 4.5 4.5 5
1 and 2 For switch OFF: 0 6 ±0.1 ±1±1
channels When VIS = VCC,
VOS = VEE ,
4053 5 5 ±0.1 ±1±1
When VIS = VEE,
Switch ON/OFF VOS = VCC,
4 channels 0 6 ±0.1 ±1±1
IIZ leakage VIL or VIH μA
For switch ON:
current 4052 5 5 ±0.2 ±2±2
All applicable
combinations of
8 channels 0 6 ±0.2 ±2±2
VIS and VOS
4051 5 5 ±0.4 ±4±4
voltage levels
VCC or
IIL Control input leakage current 0 6 ±0.1 ±1±1μA
GND
When VIS = VEE,0 6 8 80 160 μA
Quiescent VOS = VCC VCC or
ICC device IO= 0 GND
When VIS = VCC,
current 5 5 16 160 320 μA
VOS = VEE
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www.ti.com
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
DC Electrical Specifications (Continued) AMBIENT TEMPERATURE, TA
TEST CONDITIONS 40°C to 55°C to
25°C
PARAMETER 85°C 125°C UNIT
VIS VIVEE VCC MIN TYP MAX MIN MAX MIN MAX
(V) (V) (V) (V)
HCT Types
4.5 to
VIH High-level input voltage 2 2 2 V
5.5
4.5 to
VIL Low-level input voltage 0.8 0.8 0.8 V
5.5
0 4.5 70 160 200 240
VCC or VEE -
IO= 1 mA 4.5 4.5 40 120 150 180
VIL or
rON ON resistance (see Ω
VIH 0 4.5 90 180 225 270
Figure 15) VCC to VEE -
4.5 4.5 45 130 162 195
0 4.5 10
Maximum ON resistance
ΔrON -Ω
between any two channels 4.5 4.5 5
1 and 2 For switch OFF: 0 6 ±0.1 ±1±1
channels When VIS = VCC,
VOS = VEE,
4053 5 5 ±0.1 ±1±1
When VIS = VEE,
Switch ON/OFF VOS = VCC VIL or
4 channels 0 6 ±0.1 ±1±1
IIZ μA
leakage current For switch ON: VIH
4052 5 5 ±0.2 ±2±2
All applicable
combinations of
8 channels 0 6 ±0.2 ±2±2
VIS and VOS
4051 5 5 ±0.4 ±4±4
voltage levels
IIL Control input leakage current (1) 5.5 ±0.1 ±1±1μA
When VIS = VEE,0 5.5 8 80 160 μA
Quiescent VOS = VCC VCC or
ICC device IO= 0 GND
When VIS = VCC,
current 4.5 5.5 16 160 320 μA
VOS = VEE
Additional quiescent VCC 4.5 to
ΔICC (2) device current per input pin: ΔICC (2) 100 360 450 490 μA
2.1 5.5
1 unit load
(1) Any voltage between VCC and GND
(2) For dual-supply systems, theoretical worst-case (VI= 2.4 V, VCC = 5.5 V) specification is 1.8 mA.
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
Table 4. HCT INPUT LOADING TABLE
TYPE INPUT UNIT LOADS(1)
4051, 4053 All 0.5
4052 All 0.4
(1) Unit load is ΔICC limit specified in DC Specifications table, e.g., 360 mA MAX at 25°C.
Switching Specifications
VCC = 5 V, TA= 25°C, input tr, tf= 6 ns TYPICAL
CL
PARAMETER TEST CONDITIONS 4051 4052 4053 UNIT
(pF) HC HCT HC HCT HC HCT
tPHL, tPLH Switch IN to OUT 15 4 4 4 4 4 4
tPHZ, tPLZ Propagation delay Switch turn-off (S or E) 15 19 19 21 21 18 18 ns
tPZH, tPZL Switch turn-on (S or E) 15 19 23 27 29 18 20
Power dissipation
CPD (1) 50 52 74 76 38 42 pF
capacitance
(1) CPD is used to determine the dynamic power consumption, per package.
PD= CPD VCC 2fI+(CL+ CS) VCC 2fO
fO= output frequency
fI= input frequency
CL= output load capacitance
CS= switch capacitance
VCC = supply voltage
10 Submit Documentation Feedback ©19972011, Texas Instruments Incorporated
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www.ti.com
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
Switching Specifications
CL= 50 pF, input tr, tf= 6 ns AMBIENT TEMPERATURE, TA
25°C40°C to 85°C55°C to 125°C
VEE VCC
PARAMETER UNIT
(V) (V) HC HCT HC HCT HC HCT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
0 2 60 75 90
0 4.5 12 12 15 15 18 18
tPLH, Propagation delay, ns
tPHL switch in to out 0 6 10 13 15
4.5 4.5 8 8 10 10 12 12
0 2 225 280 340
0 4.5 45 45 56 56 68 68
4051 0 6 38 48 57
4.5 4.5 32 32 40 40 48 48
0 2 250 315 375
Maximum switch turn 0 4.5 50 50 63 63 75 75
tPHZ,OFF delay from S or E to 4052 ns
tPLZ 0 6 43 54 65
switch output
4.5 4.5 38 38 48 48 57 57
0 2 210 265 315
0 4.5 42 44 53 55 63 66
4053 0 6 36 45 54
4.5 4.5 29 31 36 39 44 47
0 2 225 280 340
0 4.5 45 55 56 69 68 83
4051 0 6 38 48 57
4.5 4.5 32 39 40 49 48 59
0 2 325 405 490
Maximum switch turn 0 4.5 65 70 81 68 98 105
tPZL,ON delay from S or E to 4052 ns
tPZH 0 6 55 69 83
switch output
4.5 4.5 46 48 58 60 69 72
0 2 220 275 330
0 4.5 44 48 55 60 66 72
4053 0 6 37 47 56
4.5 4.5 31 34 39 43 47 51
Input (control)
CI10 10 10 10 10 10 pF
capacitance
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
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SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
Analog Channel Specifications
Typical values at TA= 25°CVEE VCC
PARAMETER TEST CONDITIONS HC/HCT TYPES HC/HCT UNIT
(V) (V)
CISwitch input capacitance All 5 pF
4051 25
CCOM Common output capacitance 4052 12 pF
4053 8
4051 145
4052 2.25 2.25 165
Minimum switch frequency 4053 200
fMAX response at 3 dB See Figure 3 (1) (2) MHz
4051 180
(see Figures 12, 14, 16) 4052 4.5 4.5 185
4053 200
All 2.25 2.25 0.035
Sine-wave distortion See Figure 5 %
All 4.5 4.5 0.018
4051 2.25 2.25 73
4052 65
4053 64
Switch OFF signal feedthrough See Figure 7(2) (3) dB
(see Figures 13, 15, 17) 4051 4.5 4.5 75
4052 67
4053 66
(1) Adjust input voltage to obtain 0 dBm at VOS for fIN = 1 MHz
(2) VIS is centered at (VCC VEE)/2.
(3) Adjust input for 0 dBm
12 Submit Documentation Feedback ©19972011, Texas Instruments Incorporated
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VIS 0.1µF
VCC
50
VCC/2
10pF
VOS
SWITCH
ON
dB
METER
VIS 10µF
VCC
10k
VCC/2
50pF
VOS
SWITCH
ON
DISTORTION
METER
SINE−
WAVE
VI = VIH VIS
fIS = 1kHz TO 10kHz
VIS
0.1µF
VCC
VCC/2
C
VOS1
SWITCH
ON
R
R
fIS = 1MHz SINEWAVE
R = 50
C = 10pF
VCC
R
VCC/2
C
SWITCH
OFF
R
INPUT
VCC/2
VOS2
dB
METER
VIS
0.1µF
VCC
R
VCC/2
C
VOS
SWITCH
OFF
dB
METER
R
VCC/2
VC = VIL
fIS 1MHz SINEWAVE
R = 50
C = 10pF
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
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SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
APPLICATION INFORMATION
Figure 3. Frequency Response Test Circuit Figure 5. Sine-Wave Distortion Test Circuit
Figure 6. Control to Switch Feedthrough Noise
Test Circuit
Figure 4. Crosstalk Between Two Switches
Test Circuit
Figure 7. Switch OFF Signal Feedthrough
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
FIGURE 8A.
FIGURE 8B. HC TYPES FIGURE 8C. HCT TYPES
50%
10%
90%
VCC
SWITCH INPUT
tr = 6ns tf = 6ns
tPHL
tPLH VEE
50%
10%
90%
SWITCH OUTPUT
50% 10%
90%
GND
VCC
10%
90% 50%
50%
E OR Sn
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
SWITCH ONSWITCH OFF
1.3 0.3
2.7
GND
3V
10%
90% 50%
50%
E OR Sn
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
SWITCH ON
6ns 6ns
tPZH
tPHZ
tPZL
tPLZ
SWITCH ONSWITCH OFF
trtf
OUT
50pF
TG
IN
OUT
VCC FOR
VEE FOR
RL = 1k
CL
50pF
TG
VEE FOR
VCC FOR IN
tPLZ AND tPZL
tPHZ AND tPZH
tPLZ AND tPZL
tPHZ AND tPZH
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
APPLICATION INFORMATION
Figure 8. Switch Propagation Delay, Turn-On, Turn-Off Times
Figure 10. Switch In to Switch Out
Figure 9. Switch ON/OFF Propagation Delay Propagation Delay Test Circuit
Test Circuit
14 Submit Documentation Feedback ©19972011, Texas Instruments Incorporated
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
120
100
80
60
40
20
1 2 3 4 5 6 7 8 9
ON RESISTANCE ()
INPUT SIGNAL VOLTAGE (V)
VCC − VEE = 4.5V
VCC − VEE = 6V
VCC − V
EE = 9V
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
−10
−2
0
−4
−6
−8
VCC = 4.5V
GND = −4.5V
VEE = −4.5V
RL = 50
PIN 4 TO 3
VCC = 2.25V
GND = −2.25V
VEE = −2.25V
RL = 50
PIN 4 TO 3
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
−80
−100
VCC = 4.5V
GND = −4.5V
VEE = −4.5V
RL = 50
PIN 4 TO 3
VCC = 2.25V
GND = −2.25V
VEE = −2.25V
RL = 50
PIN 4 TO 3
−20
0
−40
−60
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
−4
−6
−8
−10
−2
0
VCC = 4.5V
GND = −4.5V
VEE = −4.5V
RL = 50
PIN 12 TO 3
VCC = 2.25V
GND = −2.25V
VEE = −2.25V
RL = 50
PIN 12 TO 3
FREQUENCY (Hz)
10K 100K 1M 10M 100M
dB
VCC = 4.5V
GND = −4.5V
VEE = −4.5V
RL = 50
PIN 12 TO 3
VCC = 2.25V
GND = −2.25V
VEE = −2.25V
RL = 50
PIN 12 TO 3
−80
−100
−20
0
−40
−60
dB
0
−1
−2
−3
−4
FREQUENCY (Hz)
10K 100K 1M 10M 100M
VCC = 2.25V
GND = −2.25V
VEE = −2.25V
RL = 50
PIN 5 TO 4
VCC = 4.5V
GND = −4.5V
VEE = −4.5V
RL = 50
PIN 5 TO 4
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
www.ti.com
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
TYPICAL PERFORMANCE CURVES
Figure 11. Typical ON Resistance
vs Input Signal Voltage Figure 14. Channel ON Bandwidth (HC/HCT4052)
Figure 15. Channel OFF Feedthrough
Figure 12. Channel ON Bandwidth (HC/HCT4051) (HC/HCT4052)
Figure 13. Channel OFF Feedthrough Figure 16. Channel ON Bandwidth (HC/HCT4053)
(HC/HCT4051)
©19972011, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
FREQUENCY (Hz)
10K 100K 1M 10M 100M
−80
−100
VCC = 2.25V
GND = −2.25V
VEE = −2.25V
RL = 50
PIN 5 TO 4
0
−40
−60
−20
VCC = 4.5V
GND = −4.5V
VEE = −4.5V
RL = 50
PIN 5 TO 4
dB
CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
SCHS122J NOVEMBER 1997REVISED FEBRUARY 2011
www.ti.com
TYPICAL PERFORMANCE CURVES
Figure 17. Channel OFF Feedthrough (HC/HCT4053)
16 Submit Documentation Feedback ©19972011, Texas Instruments Incorporated
Product Folder Link(s): CD/74HC4051, CD54/74HCT4051, CD54/74HC4052,
PACKAGE OPTION ADDENDUM
www.ti.com 5-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
5962-8775401EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-8855601EA ACTIVE CDIP J 16 1 TBD Call TI Call TI
5962-9065401MEA ACTIVE CDIP J 16 1 TBD Call TI Call TI
CD54HC4051F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC4051F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC4052F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC4052F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC4053F ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HC4053F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD54HCT4051F3A ACTIVE CDIP J 16 1 TBD A42 N / A for Pkg Type
CD74HC4051E ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC4051EE4 ACTIVE PDIP N 16 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
CD74HC4051M ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4051M96 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4051M96E4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4051M96G3 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM
CD74HC4051M96G4 ACTIVE SOIC D 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4051ME4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
CD74HC4051MG4 ACTIVE SOIC D 16 40 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM