FEDR27V6452L-002-03
Issue Date: Oct. 01, 2008
MR27V6452L
4M–Word × 16–Bit or 8M–Word × 8–Bit Page Mode P2ROM
FEATURES
· 4,194,304-word × 16-bit / 8,388,608-word × 8-bit electrically switchable configuration
Bit
...................90 ns MAX
me ..........................30 ns MAX
· Operating current ..........................50 mA MAX (5MHz)
urrent.............................10 µA MAX
· Input/Output TTL compatible
t
PACKAGES
nology utilizes
test equipment for pr ogra mming the customers code into the P2ROM prior to final production testing.
OM and has many
llowing;
at the final stage of the produ ction process , a larg e P2ROM
inventory "bank system" of un-programmed packaged products are maintained to provide an aggressive
lead-time and minimize liability as a custom product.
· No mask charge, since P2ROMs do not utilize a custom mask for storing customer code, no mask charges
apply.
· No add i tion al p rogramming charge, unlike Flash an d OTP that require additional programming an d handling
costs, the P2R OM already has the code loaded at the factory with minimal effect on the production throughpu t.
The cost is included in the uni t price.
· Custom Marking is available at no additional charge.
· Pin Compatible w ith Mask ROM and some FLASH products.
· Page size of 8-word x 16-Bit or 16-word x 8-
· 3.0 V to 3.6 V power supply
· Random Access time..
· Page Access ti
· Standby c
· Three-state outpu
MR27V6452L-xxxMA 44-pin plastic SOP (SOP44-P-600-1.27-K)
·MR27V6452L-xxxTN 48-pin plastic TSOP (TSOP I 48-P-1220-0.50-1K)
MR27V6452L-xxxTA 56-pin plastic TSOP (TSOP I 56-P-1420-0.50-K)
P2ROM ADVANCED TECHNOLOGY
P2ROM stands for Production Programmed ROM. This exclusive LAPIS Semiconductor tech
factory
Advancements in this technology allows production costs to be equivalent to MASKR
advantages and added b e nefits over the other non-volatile technolo gies, which include the fo
· Short lead time, since the P2ROM is programm ed
1/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
PIN CONFIGURATION (TOP VIEW)
48TSOP(Type-I)
(Unit: mm)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
A21
NC
NC
A7
A6
A5
A4
A3
A2
A1
1
6
1
1
1
1
1
1
18
19
20
21
22
23
24
E#
/A
D1
D8
D0
OE#
VSS
CE#
A0
A18
A17 16
17
2
3
4
5
7
8
9
0
1
2
3
4
5
A16
BYT
–1
VSS
D15
D7
D14
D6
D13
D5
D12
D4
VCC
D11
D3
D10
D2
D9
56TSOP(Type-I)
NC
NC
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
NC
NC
A21
NC
NC
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
NC
NC
A16
BYTE#
VSS
D15/A-1
D7
D14
D6
D13
D5
D12
D4
VCC
D11
D3
D10
D2
D9
D1
D8
D0
OE#
VSS
CE#
A0
NC
NC*
1
2
3
6
7
9
10
11
12
13
17
18
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
4
5
8
A21
A18
14
15
16
19
A17
A7
A6
A5
A4
A3
A2
A1
A0
E#
SS
OE#
D0
D8
D1
D9
D2
D10
D3
D11
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
BYT
VSS
D15/A–1
D7
D14
D6
D13
D5
D12
D4
VCC
E#
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
16
17
1
19
20
21
22
*:Different from FLASH products.
C
V14
15
8
44SOP
2/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
BLOCK DIAGRAM
PIN DESC IONS
me Functions
RIPT
Pin na
D15 / A–1 Data output / Address input
A0 to A21 Address inputs
D0 to D14 Data outputs
CE# Chip enable input
OE# Output enable input
BYTE# Word / Byte select input
VCC Power supply voltage
VSS Ground
NC No connect
In 8-bit output mode, these pins
are placed in a high-Z state and
pin D15 functions as the A-1
address pin.
A
0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
CE# BYTE#
OE#
CE
× 8/× 16 Switch
D0 D2 D4 D6 D8 D10 D12 D14
D1 D3 D5 D7 D9 D11 D13 D15
Memory Cell Matrix
× 16-Bit or 8M × 8-Bit
Row Decoder
Column Dec
Address Buffer
OE
4M
Multiplexer
Output Buffer
oder
A–1
3/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
FUN ON TAB
Mode C OE BYTE#
CC to D7 to D14 D15/A–1
CTI LE
E# # V D0 D8
Read (16-Bit) L DOUT L H
Read (8-Bit) L L L DOUT Hi–Z L/H H
Output disable L H L
Hi–Z ∗
H
Standby H ∗ L
3.3 V
Hi–Z ∗
∗: Don’ or L)
AXIMUM RATINGS
ameter Symbol Condition Unit
t Care (H
ABSOLUTE M
Par Value
Operating temperature under bias Ta 0 to 70 °C
Storage temperature Tstg — –5 125 °C 5 to
Input voltage VI –0.5 to VCC+0.5 V
Output voltage V –0.5 to VCC+0.5 V
O
Power supply voltage VCC relative to VSS –0.5 to 5 V
Power dissipation per package PD Ta = 25°C W 1.0
Out cuit cur — mA put short cir rent IOS 10
RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70°C)
Parameter Symbol Condition Min. Typ. Max. Unit
VCC power supply voltage VCC 3.0 — 3.6 V
Input “H” level VIH 2.2 — VCC+0.5∗ V
Input “L” level VIL VCC = 3.0 to 3.6 V 0.6 V –0.5∗∗ —
Volt relative .
∗ : .5V(Max en puls overs ot is le han 10
∗∗ : Min.) when lse wi dershoo less than 10ns.
PIN CAPACITANCE
(VCC = 3.3 V, Ta = 25°C, f = 1 MHz)
Parameter Symbol Condition Min. Typ. Max. Unit
age is to VSS
Vcc+1 .) wh e width of ho ss t ns.
-1.5V( pu dth of un t is
Input CIN1 — — 12
BYTE# CIN2 VI = 0 V — — 200
Output COUT V
O = 0 V — — 12 pF
4/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
ELECTRICAL CHARACTERISTICS
DC ristics
= 3.0 V to 3.6 V, Ta = 0 to 70°C)
Symbol Conditio Min. Typ. Max. Unit
Characte
(VCC
Parameter n
Input leakage current ILI V
I = 0 to — — 10 μA VCC
Output leakage curren 0 to — — 10 μA t ILO V
O = VCC
ICCSC CE# = V — 10 μA
CC —
VCC power supply curr ICCST CE# = — — 1 mA
ent
(Standby) VIH
VCC power supply curr ICCA IL, O VIH
f=5MH — — 50 mA
ent
(Read) CE# = V E# =
z
VIH — 2.2 — VCC+0.5∗ V Input “H” level
Input “L” level VIL — –0.5∗∗ — 0.6 V
Output “H” level VOH I
OH = –1 mA 2.4 — — V
Output “L” level VOL I
OL = 2 mA — — 0.4 V
Voltage is relative to VSS.
∗ : V Max.) w se w ershoot
when pu width of u rshoot is le 10ns
(VCC = 3.0 V to 3.6 V, Ta = 0 to 70°C)
ter Symbol Condition . Max. Unit
cc+1.5V( hen pul idth of ov is less than 10ns.
∗∗ : -1.5V(Min.) lse nde ss than .
AC Characteristics
Parame Min
Address cycle tim e t — — ns
C 90
Address access time E# = VIL 90 ns tACC CE# = O —
Page cycle time tPC — 30 — ns
Pag — — 30 ns e access time tPAC
CE# access time tCE OE# = VIL — 90 ns
OE# # = VIL — 30 ns access time tOE CE
tCHZ OE# = VIL 0 20 ns
Output disable time tOHZ CE# = VIL 0 20 ns
Output hold time tOH E# = OE# = VIL 0 — ns C
Measurement conditions
Input signal level ---------------------------------0 V/3 V
Input timing reference level--------------------1/2Vcc
Output load ----------------------------------------50 pF
Output timing reference level -----------------1/2Vcc
Output load
Output
44SOP
5/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
TIMING CHART (READ CYCLE)
Random Mode Read Cycle
Address
CE#
OE#
Dout
Access
tC
tCE
tOH
tCHZ
tOHZ
Valid Data
Hi-Z Hi-Z
tOE tOH
tACC
tACC
tC
de Read Cycle
Valid Data
Page Access Mo
tC
A3 to A21
tCE
tOE
tACC
tOH
tCHZ
tOHZ
Hi-Z Hi-Z
Dout
tPAC
tPC tPC
A
-1 to
A
2
(
B
y
te mode
)
A
0 to
A
2
(
Word mode
)
CE#
OE#
tPAC
6/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
PACKAGE DIMENSIONS
Notes for Mounting the Surface Mount Type Package
The surfa ce mount type pac kages are very susceptible to heat in reflow mounting and hu midity absor bed in stora ge.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
(Unit: mm)
7/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
FEDR27V6452L-002-03
MR27V6452L / P2ROM
8/11
Notes for Mounting the Surface Mount Type Package
The surfa ce mount type pac kages are very susceptible to heat in reflow mounting and hu midity absor bed in stora ge.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
(Unit: mm)
8/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
FEDR27V6452L-002-03
MR27V6452L / P2ROM
(Unit: mm)
9/11
Notes for Mounting the Surface Mount Type Package
The surfa ce mount type pac kages are very susceptible to heat in reflow mounting and hu midity absor bed in stora ge.
Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name,
package name, pin number, package code and desired mounting conditions (reflow method, temperature and
times).
9/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
REVISION HISTORY
Page
Document
No. Date Previous
on Current Description
Editi Edition
FEDR27V6452L-02 21, 2005 ition 1 -01 Sep. – – Final ed
FEDR27V6452L-02 t, 18,2005 -02 Oc 1 1, 6 Add MR27V6452L-xxxMA
FEDR27V6452L-02-03 Jun, 07,2007 1 1,2,5,9
Add MR27V6452L-xxxTA
tC, tACC, tCE =100ns->90ns
FEDR27V6452L-002-03 Oct,1,2008 – – Changed company logo and name
to OKI SEMICONDUCTOR
10/11
FEDR27V6452L-002-03
MR27V6452L / P2ROM
11/11
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