D
D
D
D
D
5
G
6
S
7
S
8
S
P0095-01
VGS − Gate to Source Voltage − V
0
2
4
6
8
10
12
14
16
18
20
0 2 4 6 8 10 12
RDS(on) − On-State Resistance − m
G006
ID = 20A
TC = 125°C
TC = 25°C
Qg − Gate Charge − nC
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14
VG − Gate Voltage − V
G003
ID = 20A
VDS = 12.5V
CSD16406Q3
www.ti.com
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD16406Q3
1FEATURES PRODUCT SUMMARY
2 Ultra Low Qg and Qgd VDS Drain to Source Voltage 25 V
Low Thermal Resistance QgGate Charge Total (4.5V) 5.8 nC
Avalanche Rated Qgd Gate Charge Gate to Drain 1.5 nC
Pb Free Terminal Plating VGS = 4.5V 5.9 m
RDS(on) Drain to Source On Resistance VGS = 10V 4.2 m
RoHS Compliant Vth Threshold Voltage 1.8 V
Halogen Free
SON 3.3mm x 3.3mm Plastic Package ORDERING INFORMATION
Device Package Media Qty Ship
APPLICATIONS SON 3.3 × 3.3 13-inch Tape and
CSD16406Q3 2500
Point-of-Load Synchronous Buck Converter Plastic Package reel Reel
for Applications in Networking, Telecom and
Computing Systems ABSOLUTE MAXIMUM RATINGS
Optimized for Control or Synchronous FET TA= 25°C unless otherwise stated VALUE UNIT
Applications VDS Drain to Source Voltage 25 V
VGS Gate to Source Voltage +16 / –12 V
DESCRIPTION Continuous Drain Current, TC= 25°C 60 A
ID
The NexFET™ power MOSFET has been designed Continuous Drain Current(1) 19 A
to minimize losses in power conversion applications. IDM Pulsed Drain Current, TA= 25°C(2) 114 A
PDPower Dissipation(1) 2.7 W
Top View TJ, Operating Junction and Storage –55 to 150 °C
TSTG Temperature Range
Avalanche Energy, single pulse
EAS 101 mJ
ID= 45A, L = 0.1mH, RG= 25
(1) RqJA = 46°C/W on 1in2Cu (2 oz.) on 0.060" thick FR4 PCB.
(2) Pulse width 300ms, duty cycle 2%
RDS(ON) vs VGS Gate Charge
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2009–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CSD16406Q3
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA= 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Static Characteristics
BVDSS Drain to Source Voltage VGS = 0V, ID= 250mA 25 V
IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V 1 mA
IGSS Gate to Source Leakage Current VDS = 0V, VGS = +16/-12V 100 nA
VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID= 250mA 1.4 1.8 2.2 V
VGS = 4.5V, ID= 20A 5.9 7.4 m
RDS(on) Drain to Source On Resistance VGS = 10V, ID= 20A 4.2 5.3 m
gfs Transconductance VDS = 15V, ID= 20A 53 S
Dynamic Characteristics
CISS Input Capacitance 840 1100 pF
COSS Output Capacitance VGS = 0V, VDS = 12.5V, f = 1MHz 680 950 pF
CRSS Reverse Transfer Capacitance 57 80 pF
RgSeries Gate Resistance 1.2 2.4
QgGate Charge Total (4.5V) 5.8 8.1 nC
Qgd Gate Charge Gate to Drain 1.5 nC
VDS = 12.5V, ID= 20A
Qgs Gate Charge Gate to Source 2.5 nC
Qg(th) Gate Charge at Vth 1.5 nC
QOSS Output Charge VDS = 13.6V, VGS = 0V 13.9 nC
td(on) Turn On Delay Time 7.3 ns
trRise Time 12.9 ns
VDS = 12.5V, VGS = 4.5V ID= 20A
RG= 2
td(off) Turn Off Delay Time 8.5 ns
tfFall Time 4.8 ns
Diode Characteristics
VSD Diode Forward Voltage IS= 20A, VGS = 0V 0.85 1.0 V
Qrr Reverse Recovery Charge VDD = 13.6V, IF= 20A, di/dt = 300A/ms 18 nC
trr Reverse Recovery Time VDD = 13.6V, IF= 20A, di/dt = 300A/ms 22 ns
THERMAL CHARACTERISTICS
(TA= 25°C unless otherwise stated) PARAMETER MIN TYP MAX UNIT
RqJC Thermal Resistance Junction to Case(1) 2.7 °C/W
RqJA Thermal Resistance Junction to Ambient(1) (2) 58 °C/W
(1) RqJC is determined with the device mounted on a 1 inch square 2 oz. Cu pad on a 1.5 × 1.5 in 0.06 inch thick FR4 board. RqJC is
specified by design while RqJA is determined by the user’s board design.
(2) Device mounted on FR4 Material with 1 inch2of 2 oz. Cu.
2Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16406Q3
GATE Source
DRAIN
M0161-02
GATE Source
DRAIN
M0161-01
tp PulseDuration–s
ZqJA NormalizedThermalImpedance
G012
0.1
0.05
0.01
0.02
0.0001 0.01 0.1 1 10 100 1k0.001
0.0001
0.01
0.1
10
1
0.001
0.5
0.3
SinglePulse
DutyCycle=t /t
1 2
Rq
q q
JA
J JA JA
=130 C/W(1 inCu)
T =P xZ xR
°2
t1
t2
P
CSD16406Q3
www.ti.com
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
Max RqJA = 162°C/W
Max RqJA = 58°C/W when mounted on
when mounted on 1 minimum pad area of 2
inch2of 2 oz. Cu. oz. Cu.
TYPICAL MOSFET CHARACTERISTICS
(TA= 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): CSD16406Q3
VDS − Drain to Source Voltage − V
0
5
10
15
20
25
30
35
40
45
50
0.0 0.5 1.0 1.5 2.0 2.5 3.0
ID − Drain Current − A
G001
VGS = 2.5V
VGS = 3V
VGS = 4.5V
VGS = 10V
VGS = 3.5V
VGS − Gate to Source Voltage − V
0
10
20
30
40
50
1.5 2.0 2.5 3.0 3.5 4.0
ID − Drain Current − A
G002
VDS = 5V
TC = −55°C
TC = 25°C
TC = 125°C
Qg − Gate Charge − nC
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14
VG − Gate Voltage − V
G003
ID = 20A
VDS = 12.5V
VDS − Drain to Source Voltage − V
0.0
0.5
1.0
1.5
2.0
2.5
0 5 10 15 20 25
C − Capacitance − nF
G004
f = 1MHz
VGS = 0V
CRSS = CGD
COSS = CDS + CGD CISS = CGD + CGS
TC Case Temperature C°
0.50
0.75
1.00
1.25
1.50
1.75
2.00
2.25
−75 −25 25 75 125 175
VGS(th) ThresholdVoltage V
G005
2.50
I =250 A
Dm
VGS − Gate to Source Voltage − V
0
2
4
6
8
10
12
14
16
18
20
0 2 4 6 8 10 12
RDS(on) − On-State Resistance − m
G006
ID = 20A
TC = 125°C
TC = 25°C
CSD16406Q3
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA= 25°C unless otherwise stated)
Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance
Figure 6. Threshold Voltage vs. Temperature Figure 7. On Resistance vs. Gate Voltage
4Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16406Q3
TC − Case Temperature − °C
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
−75 −25 25 75 125 175
Normalized On-State Resistance
G007
ID = 20A
VGS = 10V
0.0 0.2 0.4 0.6 0.8 1.0 1.2
VSD − Source to Drain Voltage − V
ISD − Source to Drain Current − A
G008
100
1
0.01
0.0001
0.001
0.1
10
TC = 25°C
TC = 125°C
G009
1k
10
0.01
1
100
0.1
0.01 0.1 10 1001
SinglePulse
RθJA =130°C/W(minCu)
100 sm
1ms
10ms
100ms
DC
1s
AreaLimited
byRDS(on)
VDS Drain ToSourceVoltage V
ID DrainCurrent A
t(AV) − Time in Avalanche − ms G010
1k
10
1
100
I(AV) − Peak Avalanche Current − A
0.01 0.1 10 1001
TC = 25°C
TC = 125°C
TC − Case Temperature − °C
0
10
20
30
40
50
60
70
−50 −25 0 25 50 75 100 125 150 175
ID − Drain Current − A
G011
CSD16406Q3
www.ti.com
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA= 25°C unless otherwise stated)
Figure 8. Normalized On Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage
Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): CSD16406Q3
M0142-01
D2
D
L1
c
1
2
3
4
5678
LH
b
E2
TopView BottomView
FrontView
SideView
5678
1
2
3
4
A
D
E
q
A1
E
e
CSD16406Q3
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
www.ti.com
MECHANICAL DATA
Q3 Package Dimensions
DIM MILLIMETERS INCHES
MIN NOM MAX MIN NOM MAX
A 0.950 1.000 1.100 0.037 0.039 0.043
A1 0.000 0.000 0.050 0.000 0.000 0.002
b 0.280 0.340 0.400 0.011 0.013 0.016
c 0.150 0.200 0.250 0.006 0.008 0.010
D 3.200 3.300 3.400 0.126 0.130 0.134
D1
D2 1.650 1.750 1.800 0.065 0.069 0.071
E 3.200 3.300 3.400 0.126 0.130 0.134
E1
E2 2.350 2.450 2.550 0.093 0.096 0.100
e 0.650 TYP 0.026
H 0.35 0.450 0.550 0.014 0.018 0.022
L 0.35 0.450 0.550 0.014 0.018 0.022
L1
q
6Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16406Q3
4.00 ±0.10 (See Note 1) 2.00 ±0.05
3.60
3.60
1.30
1.75 ±0.10
M0144-01
8.00 ±0.10
12.00 +0.30
–0.10
5.50 ±0.05
Ø 1.50 +0.10
–0.00
CSD16406Q3
www.ti.com
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
Recommended PCB Pattern
For recommended circuit layout for PCB designs, see application note SLPA005 Reducing Ringing Through
PCB Layout Techniques.
Q3 Tape and Reel Information
Notes:
1. 10 sprocket hole pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm IN 100mm, noncumulative over 250mm
3. Material:black static dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. Thickness: 0.30 ±0.05mm
6. MSL1 260°C (IR and Convection) PbF Reflow Compatible
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Link(s): CSD16406Q3
CSD16406Q3
SLPS202A AUGUST 2009REVISED SEPTEMBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (August 2009) to Revision A Page
Deleted the Package Marking Information section ............................................................................................................... 7
8Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD16406Q3
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
CSD16406Q3 SON DQG 8 2500 330.0 12.8 3.6 3.6 1.2 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2011
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CSD16406Q3 SON DQG 8 2500 335.0 335.0 32.0
PACKAGE MATERIALS INFORMATION
www.ti.com 21-Jan-2011
Pack Materials-Page 2
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