2 Ω, CMOS, ±5 V/+5 V
SPST Switches
ADG601/ADG602
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2001–2007 Analog Devices, Inc. All rights reserved.
FEATURES
Low on resistance, 2.5 Ω maximum
<0.65 Ω on-resistance flatness
Dual ±2.7 V to ±5.5 V or single +2.7 V to +5.5 V supplies
Rail-to-rail input signal range
Tiny, 6-lead SOT-23; 8-lead MSOP; and 820 μm × 2255 μm die
Low power consumption
TTL-/CMOS-compatible inputs
APPLICATIONS
Automatic test equipment
Power routing
Communication systems
Data acquisition systems
Sample-and-hold systems
Avionics
Relay replacement
Battery-powered systems
FUNCTIONAL BLOCK DIAGRAMS
ADG602
DS
IN
ADG601
DS
IN
NOTES
1. SWITCHES SHOWN FOR A LOGIC 0 INPUT.
02619-001
Figure 1.
Table 1. Truth Table
ADG601 IN ADG602 IN Switch Condition
0 1 Off
1 0 On
GENERAL DESCRIPTION
The ADG601/ADG602 are monolithic, CMOS single-pole
single-throw (SPST) switches with on resistance typically less
than 2.5 Ω. The low on-resistance flatness makes the
ADG601/ADG602 ideally suited to many applications,
particularly those requiring low distortion. These switches are
ideal replacements for mechanical relays because they are more
reliable, have lower power requirements, and are available in
much smaller package sizes.
The ADG601 is a normally open (NO) switch, and the ADG602
is a normally closed (NC) switch. Each switch conducts equally
well in both directions when the device is on, with the input
signal range extending to the supply rails.
The switches are available in tiny, 6-lead SOT-23; 8-lead MSOP;
and 820 μm × 2255 μm die.
PRODUCT HIGHLIGHTS
1. Low on resistance (2 Ω typical)
2. Dual ±2.7 V to ±5.5 V or single +2.7 V to +5.5 V supplies
3. Tiny, 6-lead SOT-23; 8-lead MSOP; and 820 μm × 2255 μm die
4. Rail-to-rail input signal range
ADG601/ADG602
Rev. C | Page 2 of 12
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Dual Supply ................................................................................... 3
Single Supply ................................................................................. 4
Absolute Maximum Ratings ............................................................5
ESD Caution...................................................................................5
Pin Configurations and Function Descriptions............................6
Typical Performance Characteristics ..............................................7
Terminology .......................................................................................9
Test Circuits..................................................................................... 10
Outline Dimensions ....................................................................... 11
Ordering Guide .......................................................................... 11
REVISION HISTORY
3/07—Rev. B to Rev. C
Added Die Package.............................................................Universal
Changes to Specifications.................................................................3
Added Figure 4 and Table 6..............................................................6
Changes to Ordering Guide .......................................................... 11
3/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to 6-Lead SOT-23 (RJ-6) Pin Configuration .................6
Added Pin Function Descriptions Table ........................................6
Changes to Figure 19.........................................................................9
Updated Outline Dimensions........................................................11
Changes to Ordering Guide...........................................................11
6/03—Rev. 0 to Rev. A
Changes to Specifications.................................................................2
Changes to Ordering Guide.............................................................4
Updated Outline Dimensions..........................................................8
ADG601/ADG602
Rev. C | Page 3 of 12
SPECIFICATIONS
DUAL SUPPLY
VDD = 5 V ± 10%, VSS = –5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
B Version1
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS to VDD V VDD = +4.5 V, VSS = –4.5 V
On Resistance (RON) 2 Ω typ VS = ±4.5 V, IDS = −10 mA; see Figure 15
2.5 5.5 Ω max
On-Resistance Flatness (RFLAT (ON)) 0.35 0.4 Ω typ VS = ±3.3 V, IDS = −10 mA
0.6 0.65 Ω max
LEAKAGE CURRENTS VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off) ±0.01 nA typ VS = +4.5 V/−4.5 V, VD = −4.5 V/+4.5 V; see Figure 16
±0.25 ±1 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = +4.5 V/−4.5 V, VD = −4.5 V/+4.5 V; see Figure 16
±0.25 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = +4.5 V or −4.5 V; see Figure 17
±0.25 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS2
tON 80 ns typ RL = 300 Ω, CL = 35 pF
120 155 ns max VS = 3.3 V; see Figure 18
tOFF 45 ns typ RL = 300 Ω, CL = 35 pF
75 90 ns max VS = 3.3 V; see Figure 18
Charge Injection 250 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
Bandwidth −3 dB 180 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 21
CS (Off) 50 pF typ f = 1 MHz
CD (Off) 50 pF typ f = 1 MHz
CD, CS (On) 145 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = +5.5 V, VSS = −5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V
1.0 μA max
ISS 0.001 μA typ Digital inputs = 0 V or 5.5 V
1.0 μA max
1 Temperature range for B version is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
ADG601/ADG602
Rev. C | Page 4 of 12
SINGLE SUPPLY
VDD = 5 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
B Version1
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range 0 V to VDD V VDD = 4.5 V
On Resistance (RON) 3.5 Ω typ VS = 0 V to 4.5 V, IDS = −10 mA; see Figure 15
5 8 Ω max
On-Resistance Flatness (RFLAT (ON)) 0.2 0.2 Ω typ VS = 1.5 V to 3.3 V, IDS = –10 mA
0.6 Ω max
LEAKAGE CURRENTS VDD = 5.5 V
Source Off Leakage, IS (Off) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V; see Figure 16
±0.25 ±1 nA max
Drain Off Leakage, ID (Off) ±0.01 nA typ VS = 4.5 V/1 V, VD = 1 V/4.5 V; see Figure 16
±0.25 ±1 nA max
Channel On Leakage, ID, IS (On) ±0.01 nA typ VS = VD = 4.5 V or 1 V; see Figure 17
±0.25 ±1 nA max
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH 0.005 μA typ VIN = VINL or VINH
±0.1 μA max
Digital Input Capacitance, CIN 2 pF typ
DYNAMIC CHARACTERISTICS2
tON 110 ns typ RL = 300 Ω, CL = 35 pF
220 280 ns max VS = 3.3 V; see Figure 18
tOFF 50 ns typ RL = 300 Ω, CL = 35 pF
80 110 ns max VS = 3.3 V; see Figure 18
Charge Injection 20 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 19
Off Isolation −60 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 20
Bandwidth –3 dB 180 MHz typ RL = 50 Ω, CL = 5 pF; see Figure 21
CS (Off) 50 pF typ f = 1 MHz
CD (Off) 50 pF typ f = 1 MHz
CD, CS (On) 145 pF typ f = 1 MHz
POWER REQUIREMENTS VDD = 5.5 V
IDD 0.001 μA typ Digital inputs = 0 V or 5.5 V
1.0 μA max
1 Temperature range for B version is −40°C to +85°C.
2 Guaranteed by design, not subject to production test.
ADG601/ADG602
Rev. C | Page 5 of 12
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to VSS 13 V
VDD to GND −0.3 V to +6.5 V
VSS to GND +0.3 V to –6.5 V
Analog Inputs1VSS − 0.3 V to VDD + 0.3 V
Digital Inputs1−0.3 V to VDD + 0.3 V or
30 mA (whichever
occurs first)
Continuous Current, S or D 100 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 200 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Thermal Resistance
MSOP
θJA 206°C/W
θJC 44°C/W
SOT-23
θJA 229.6°C/W
θJC 91.99°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature 220°C
1 Overvoltages at IN, S, or D are clamped by internal diodes. Current should be
limited to the maximum ratings given.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating may be applied at a time.
ESD CAUTION
ADG601/ADG602
Rev. C | Page 6 of 12
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
DD 1
S
2
V
SS 3
IN
6
D
5
GND
4
ADG601/
ADG602
TOP VIEW
(Not to Scale)
0
2619-002
PIN 1
INDICATOR
D1
NC 2
NC 3
V
DD 4
S8
GND7
IN
6
VSS
5
NC = NO CONNECT
ADG601/
ADG602
TOP VIEW
(Not to Scale)
0
2619-003
PIN 1
INDICATOR
02619-021
1
2
3
4
5
6
7
14
TOP VIEW
(Not to Scale)
13
12
11
10
9
8
Figure 2. 6-Lead SOT-23 (RJ-6) Figure 3. 8-Lead MSOP (RM-8) Figure 4. Die (820 μm × 2255 μm)
Table 5. Pin Function Descriptions
Pin No.
6-Lead SOT-23 8-Lead MSOP Mnemonic Description
1 4 VDD Most Positive Power Supply Potential.
2 8 S Source Terminal. Can be an input or output.
3 5 VSS Most Negative Power Supply Potential.
4 7 GND Ground (0 V) Reference.
5 1 D Drain Terminal. Can be an input or output.
6 6 IN Logic Control Input.
N/A 2, 3 NC No Connect.
Table 6. Die Pad Coordinates1
Die Pad
Coordinates
Die Pad No. X (μm) Y (μm) Mnemonic Description
1 −265 +754 NC No Connect.
2 −265 +525 D Drain Terminal. Can be an input or output.2
3 −265 +241 D Drain Terminal. Can be an input or output.2
4 −265 +141 D Drain Terminal. Can be an input or output.2
5 −265 −191 NC No Connect.
6 −265 −409 NC No Connect.
7 −265 −549 NC No Connect.
8 −265 −787 VDD Most Positive Power Supply Potential.
9 +265 −767 VSS Most Negative Power Supply Potential.
10 +265 −429 IN Logic Control Input.
11 +265 −289 GND Ground (0 V) Reference.
12 +265 +189 S Source Terminal. Can be an input or output.3
13 +265 +521 S Source Terminal. Can be an input or output.3
14 +265 +661 NC Source Terminal. Can be an input or output.
1 Measured from the center of the die.
2 Bond the D pads together to a single point to preserve the on resistance and current handling capability. The common point acts as the drain pin of the switch.
3 Bond the S pads together to a single point to preserve the on resistance and current handling capability. The common point acts as the source pin of the switch.
ADG601/ADG602
Rev. C | Page 7 of 12
TYPICAL PERFORMANCE CHARACTERISTICS
5
4
0
3
2
1
V
D
,V
S
(V)
T
A
=25°C
±3.3V
±3V
±2.5V
±5V
±4.5V
ON RESISTANCE (Ω)
–5 –4 –3 –2 –1 0 1 2 3 4 5
02619-004
Figure 5. On Resistance vs. VD, VS (Dual Supply)
10
8
0
6
4
2
3
9
1
5
7
V
D
,V
S
(V)
0 0.51.01.52.02.53.03.54.04.55.0
ON RESISTANCE (Ω)
V
DD
=2.7V
V
DD
=3.0V
V
DD
=4.5V
V
DD
=3.3V
V
DD
=5.0V
T
A
=25°C
V
SS
=0V
02619-005
Figure 6. On Resistance vs. VD, VS (Single Supply)
5
4
0
3
2
1
V
DD
=+5V
V
SS
=–5V
V
D
,V
S
(V)
–5–4–3–2–1012345
ON RESISTANCE (Ω)
+85°C
+25°C
–40°C
0
2619-006
Figure 7. On Resistance vs. VD, VS for Different Temperatures (Dual Supply)
ON RESISTANCE (Ω)
5
4
0
3
2
1
V
DD
=5V
V
SS
=0V
+85°C
+25°C
–40°C
V
D
,V
S
(V)
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
02619-007
Figure 8. On Resistance vs. VD, VS for Different Temperatures (Single Supply)
LEAKAGE CURRENT (nA)
0.5
0.3
–0.5
0.1
–0.1
–0.3
–0.2
0.4
–0.4
0
0.2
TEMPERATURE (°C)
0 102030405060708085
VDD = +5V
VSS = –5V
VD = ±4.5V
VS =
±
4.5V
IS (OFF)
ID, IS (ON)
ID (OFF)
02619-009
Figure 9. Leakage Currents vs. Temperature (Dual Supply)
LEAKAGE CURRENT (nA)
0.5
0.3
–0.5
0.1
0
–0.1
–0.3
–0.2
0.4
–0.4
0.2
TEMPERATURE (°C)
VDD = 5V
VSS = 0V
VD = 4.5V/1V
VS = 1V/4.5V
IS (OFF)
ID (OFF)
ID, IS (ON)
0 102030405060708085
02619-008
Figure 10. Leakage Currents vs. Temperature (Single Supply)
ADG601/ADG602
Rev. C | Page 8 of 12
CHARGE INJECTION (pC)
500
400
0
300
200
100
150
450
50
250
350
V
S
(V)
T
A
=25°C
V
DD
=+5V
V
SS
=0V
V
DD
=+5V
V
SS
= –5V
–5–4–3–2–1012345
0
2619-010
Figure 11. Charge Injection vs. Source Voltage
TIME (ns)
180
160
0
80
60
40
20
140
100
120
t
ON
t
OFF
TEMPERATURE (°C)
–40 –20 0 20 40 60 80
V
DD
=+5V
V
SS
=0V
V
DD
=+5V
V
SS
=–5V
V
DD
=+5V
V
SS
= –5V
V
DD
=+5V
V
SS
=0V
02619-011
Figure 12. tON/tOFF Times vs. Temperature
FREQUENCY (MHz)
0
–10
–80
–20
–30
–70
–40
–50
–60
OFF ISOLATION (dB)
V
DD
=+5V
V
SS
=–5V
T
A
= 25°C
0.2 1 10 100
02619-012
Figure 13. Off Isolation vs. Frequency
FREQUENCY (MHz)
0
–2
–12
–4
–6
–10
–8
ON RESPONSE (dB)
V
DD
=+5V
V
SS
= –5V
T
A
= 25°C
0.2 1 10 100 400
0
2619-013
Figure 14. On Response vs. Frequency
ADG601/ADG602
Rev. C | Page 9 of 12
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential.
IDD
Positive supply current.
ISS
Negative supply current.
GND
Ground (0 V) reference.
S
Source terminal. Can be an input or an output.
D
Drain terminal. Can be an input or an output.
IN
Logic control input.
VD, VS
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum values of on resistance as measured over the specified
analog signal range.
IS (Off)
Source leakage current with the switch off.
ID (Off)
Drain leakage current with the switch off.
ID, IS (On)
Channel leakage current with the switch on.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
CS (Off)
Off switch source capacitance. Measured with reference to ground.
CD (Off)
Off switch drain capacitance. Measured with reference to ground.
CD, CS (On)
On switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tON
Delay between applying the digital control input and the output
switching on.
tOFF
Delay between applying the digital control input and the output
switching off.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
On Response
Frequency response of the on switch.
Insertion Loss
Loss due to the on resistance of the switch.
ADG601/ADG602
Rev. C | Page 10 of 12
TEST CIRCUITS
I
DS
V1
SD
V
S
R
ON
=V1/I
DS
0
2619-014
Figure 15. On Resistance
SD
V
S
V
D
I
S
(OFF) I
D
(OFF)
AA
0
2619-015
Figure 16. Off Leakage
SD
V
D
I
D
(ON)
A
NC
NC = NO CONNECT
02619-016
Figure 17. On Leakage
0.1µF
V
S
IN
SD
V
DD
GND
R
L
300Ω
C
L
35pF
V
OUT
V
DD
V
IN
V
IN
V
OUT
t
ON
t
OFF
50% 50%
90% 90%
50% 50%
V
SS
V
SS
0.1µF
ADG601
ADG602
02619-017
Figure 18. Switching Times
SD
V
DD
IN
V
S
GND
C
L
1nF
V
OUT
R
S
V
DD
V
SS
V
SS
V
IN
ADG602
V
IN
ADG601
V
OUT
Q
INJ
=C
L
×ΔV
OUT
ΔV
OUT
OFFON
02619-018
Figure 19. Charge Injection
NETWORK
ANALYZER
V
DD
V
SS
0.1µF
0.1µF
V
DD
V
SS
IN
V
IN
S
D
OFF ISOLATION = 20 log
V
OUT
V
S
GND
50Ω50Ω
R
L
50Ω
V
S
V
OUT
02619-019
Figure 20. Off Isolation
NETWORK
ANALYZER
V
DD
V
SS
0.1µF
0.1µF
V
DD
V
SS
IN
V
IN
S
D
INSERTION LOSS = 20 log
V
OUT
WITH SWITCH
V
S
WITHOUT SWITCH
GND
50Ω
R
L
50Ω
V
S
V
OUT
02619-020
Figure 21. Bandwidth
ADG601/ADG602
Rev. C | Page 11 of 12
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-AA
0.80
0.60
0.40
8°
0°
4
8
1
5
PIN 1
0.65 BSC
SEATING
PLANE
0.38
0.22
1.10 MAX
3.20
3.00
2.80
COPLANARITY
0.10
0.23
0.08
3.20
3.00
2.80
5.15
4.90
4.65
0.15
0.00
0.95
0.85
0.75
Figure 22. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
1 3
45
2
6
2.90 BSC
1.60 BSC 2.80 BSC
1.90
BSC
0.95 BSC
0.22
0.08
10°
4°
0°
0.50
0.30
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX
0.60
0.45
0.30
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-AB
Figure 23. 6-Lead Small Outline Transistor Package [SOT-23]
(RJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding1
ADG601BRT-REEL −40°C to +85°C 6-Lead SOT-23 RJ-6 STB
ADG601BRT-REEL7 −40°C to +85°C 6-Lead SOT-23 RJ-6 STB
ADG601BRTZ-REEL2−40°C to +85°C 6-Lead SOT-23 RJ-6 STB#
ADG601BRTZ-REEL72−40°C to +85°C 6-Lead SOT-23 RJ-6 STB#
ADG601BRM −40°C to +85°C 8-Lead MSOP RM-8 STB
ADG601BRM-REEL −40°C to +85°C 8-Lead MSOP RM-8 STB
ADG601BRM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 STB
ADG601BRMZ2−40°C to +85°C 8-Lead MSOP RM-8 S1G
ADG601BRMZ-REEL2−40°C to +85°C 8-Lead MSOP RM-8 S1G
ADG601BRMZ-REEL72−40°C to +85°C 8-Lead MSOP RM-8 S1G
ADG601CSURF Die
ADG602BRT-REEL −40°C to +85°C 6-Lead SOT-23 RJ-6 SUB
ADG602BRT-REEL7 −40°C to +85°C 6-Lead SOT-23 RJ-6 SUB
ADG602BRTZ-REEL2 −40°C to +85°C 6-Lead SOT-23 RJ-6 S18
ADG602BRTZ-REEL72 −40°C to +85°C 6-Lead SOT-23 RJ-6 S18
ADG602BRM −40°C to +85°C 8-Lead MSOP RM-8 SUB
ADG602BRM-REEL −40°C to +85°C 8-Lead MSOP RM-8 SUB
ADG602BRM-REEL7 −40°C to +85°C 8-Lead MSOP RM-8 SUB
ADG602BRMZ2−40°C to +85°C 8-Lead MSOP RM-8 S18
ADG602BRMZ-REEL72−40°C to +85°C 8-Lead MSOP RM-8 S18
1 Branding on SOT-23 and MSOP is limited to three characters due to space constraints.
2 Z = RoHS Compliant Part, # denotes RoHS compliant product, may be top or bottom marked.
ADG601/ADG602
Rev. C | Page 12 of 12
NOTES
©2001–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02619-0-3/07(C)
