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SCES351N − JUNE 2001 − REVISED OCT OBER 2005
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DAvailable in the Texas Instruments
NanoStarand NanoFreePackages
DSupports 5-V VCC Operation
DInputs Accept Voltages to 5.5 V
DMax tpd of 4.6 ns at 3.3 V
DLow Power Consumption, 10-µA Max ICC
D±24-mA Output Drive at 3.3 V
DIoff Supports Partial-Power-Down Mode
Operation
DLatch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
3
2
4
51
NC VCC
Y
A
GND
DBV PACKAGE
(TOP VIEW)
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
DCK PACKAGE
(TOP VIEW)
3
2
4
51
NC VCC
Y
A
GND
3
2
4
51
NC
Y
A
GND
DNU
GND
VCC
Y
A
DRL PACKAGE
(TOP VIEW)
See mechanical drawings for dimensions.
1
4
2
3
5
VCC
DNU − Do not use
YZV PACKAGE
(BOTTOM VIEW)
GND VCC
Y
A
3
1
2
4
description/ordering information
This single Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G17 contains one buffer and performs the Boolean function Y = A. The device functions as an
independent b u ffer, bu t b e c a u s e o f S c h m i t t a c t i o n , i t may have different input threshold levels for positive-going
(VT+) and negative-going (VT−) signals.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Copyright 2005, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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
  
SCES351N − JUNE 2001 − REVISED OCT OBER 2005
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
ORDERING INFORMATION
TAPACKAGEORDERABLE PART NUMBER TOP-SIDE MARKING
NanoStar − WCSP (DSBGA)
0.17-mm Small Bump − YEA SN74LVC1G17YEAR
NanoFree − WCSP (DSBGA)
0.17-mm Small Bump − YZA (Pb-free)
Reel of 3000
SN74LVC1G17YZAR
_ _ _C7_
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
Reel of 3000 SN74LVC1G17YEPR _ _ _C7_
−40
°
C to 85
°
C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free) SN74LVC1G17YZPR
−40
°
C to 85
°
C
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZV (Pb-free) Reel of 3000 SN74LVC1G17YZVR _ _ _ _
C7
SOT (SOT-23) − DBV
Reel of 3000 SN74LVC1G17DBVR
C17_
SOT (SOT-23) − DBV Reel of 250 SN74LVC1G17DBVT C17_
SOT (SC-70) − DCK
Reel of 3000 SN74LVC1G17DCKR
C7_
SOT (SC-70) − DCK
Reel of 250 SN74LVC1G17DCKT
C7_
SOT (SOT-553) − DRL Reel of 4000 SN74LVC1G17DRLR C7_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YEP, YZA/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
YZV: The actual top-side marking is on two lines. Line 1 has four characters to denote year, month, day, and assembly/test site. Line 2 has two
characters which show the family and function code. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
INPUT
AOUTPUT
Y
H H
L L
logic diagram (positive logic)
(DBV, DCK, DRL, YEA, YEP, YZA, and YZP Package)
AY
24
logic diagram (positive logic)
(YZV Package)
AY
13
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) −0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DBV package 206°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 252°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DRL package 142°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA/YZA package 154°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 132°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
YZV package 116°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Supply voltage
Operating 1.65 5.5
V
VCC Supply voltage Data retention only 1.5 V
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V −4
VCC = 2.3 V −8
I
OH
High-level output current
VCC = 3 V
−16 mA
IOH
High-level output current
VCC = 3 V −24
mA
VCC = 4.5 V −32
VCC = 1.65 V 4
VCC = 2.3 V 8
I
OL
Low-level output current
VCC = 3 V
16 mA
IOL
Low-level output current
VCC = 3 V 24
mA
VCC = 4.5 V 32
TAOperating free-air temperature −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES351N − JUNE 2001 − REVISED OCT OBER 2005
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYPMAX UNIT
1.65 V 0.76 1.13
VT+
2.3 V 1.08 1.56
VT+
Positive-going input
threshold voltage
3 V 1.48 1.92 V
Positive-going input
threshold voltage 4.5 V 2.19 2.74
5.5 V 2.65 3.33
1.65 V 0.35 0.59
VT−
2.3 V 0.56 0.88
VT−
Negative-going input
threshold voltage
3 V 0.89 1.2 V
Negative-going input
threshold voltage 4.5 V 1.51 1.97
5.5 V 1.88 2.4
1.65 V 0.36 0.64
VT
2.3 V 0.45 0.78
VT
Hysteresis
(V − V )
3 V 0.51 0.83 V
Hysteresis
(VT+ − VT−)4.5 V 0.58 0.93
T+ T−
5.5 V 0.69 1.04
IOH = −100 µA1.65 V to 4.5 V VCC − 0.1
IOH = −4 mA 1.65 V 1.2
VOH
IOH = −8 mA 2.3 V 1.9
VOH IOH = −16 mA
3 V
2.4 V
IOH = −24 mA 3 V 2.3
IOH = −32 mA 4.5 V 3.8
IOL = 100 µA1.65 V to 4.5 V 0.1
IOL = 4 mA 1.65 V 0.45
VOL
IOL = 8 mA 2.3 V 0.3
VOL IOL = 16 mA
3 V
0.4 V
IOL = 24 mA 3 V 0.55
IOL = 32 mA 4.5 V 0.55
IIA input VI = 5.5 V or GND 0 to 5.5 V ±5µA
Ioff VI or VO = 5.5 V 0±10 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 µA
ICC One input at VCC − 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 mA
CiVI = VCC or GND 3.3 V 4.5 pF
All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range, CL = 15 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd AY2.8 9.9 1.6 5.5 1.5 4.6 0.9 4.4 ns
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switching characteristics over recommended operating free-air temperature range, CL = 30 pF or
50 pF (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V
UNIT
PARAMETER
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
UNIT
tpd AY3.8 11 2 6.5 1.8 5.5 1.2 5 ns
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
TEST CONDITIONS
TYP TYP TYP TYP
UNIT
Cpd Power dissipation capacitance f = 10 MHz 20 21 22 26 pF
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SCES351N − JUNE 2001 − REVISED OCT OBER 2005
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V
VOH − V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 M
1 M
1 M
1 M
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
15 pF
15 pF
15 pF
15 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms
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  
SCES351N − JUNE 2001 − REVISED OCT OBER 2005
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1
V
LOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
Waveform 1
S1 at VLOAD
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/
2
0 V
VOL + V
VOH − V
0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 .
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 k
500
500
500
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
2 ns
2 ns
2.5 ns
2.5 ns
INPUTS
Figure 2. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN74LVC1G17DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DBVRE4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DBVTE4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DCKR ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DCKRE4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DCKRG4 ACTIVE SC70 DCK 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DCKT ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DCKTE4 ACTIVE SC70 DCK 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DRLR ACTIVE SOP DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17DRLRG4 ACTIVE SOP DRL 5 4000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74LVC1G17YEAR ACTIVE WCSP YEA 5 3000 TBD SNPB Level-1-260C-UNLIM
SN74LVC1G17YEPR ACTIVE WCSP YEP 5 3000 TBD SNPB Level-1-260C-UNLIM
SN74LVC1G17YZAR ACTIVE WCSP YZA 5 3000 Pb-Free
(RoHS) SNAGCU Level-1-260C-UNLIM
SN74LVC1G17YZPR ACTIVE WCSP YZP 5 3000 Pb-Free
(RoHS) SNAGCU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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