SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Ioff Feature Supports Partial-Power-Down
Mode Operation
D
Supports 5-V VCC Operation
D
Package Options Include Plastic
Small-Outline Transistor (DBV, DCK)
Packages
description
This single bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G126 is a single bus driver/line driver with a 3-state output. The output is disabled when the
output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the
driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G126 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS OUTPUT
OE AY
H H H
HLL
L X Z
logic symbol†
EN
1
OE 2
AY
4
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
AY
OE 1
24
PRODUCT PREVIEW
Copyright 2000, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
DBV OR DCK PACKAGE
(TOP VIEW)
1
2
3
5
4
OE
A
GND
VCC
Y
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DBV package 347°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCK package 389°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Su
pp
ly voltage
Operating 1.65 5.5
V
V
CC
S
u
ppl
y v
oltage
Data retention only 1.5
V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH
High level in
p
ut voltage
VCC = 2.3 V to 2.7 V 1.7
V
V
IH
High
-
le
v
el
inp
u
t
v
oltage
VCC = 3 V to 3.6 V 2
V
VCC = 4.5 V to 5.5 V 0.7 ×VCC
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL
Low level in
p
ut voltage
VCC = 2.3 V to 2.7 V 0.7
V
V
IL
Lo
w-
le
v
el
inp
u
t
v
oltage
VCC = 3 V to 3.6 V 0.8
V
VCC = 4.5 V to 5.5 V 0.3 ×VCC
VIInput voltage 0 5.5 V
VOOutput voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current
VCC =3V
–16 mA
V
CC =
3
V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current
VCC =3V
16 mA
V
CC =
3
V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
∆t/∆vInput transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ±0.5 V 5
TAOperating free-air temperature –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
IOH = –100
m
A1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2
V
IOH = –8 mA 2.3 V 1.9
V
V
OH IOH = –16 mA
3V
2.4
V
IOH = –24 mA
3
V
2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100
m
A1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
V
IOL = 8 mA 2.3 V 0.3
V
V
OL IOL = 16 mA
3V
0.4
V
IOL = 24 mA
3
V
0.55
IOL = 32 mA 4.5 V 0.55
IIA or OE
inputs VI = 5.5 V or GND 0 to 5.5 V ±5
m
A
Ioff VI or VO = 5.5 V 0±10
m
A
IOZ VO = 0 to 5.5 V 3.6 V 10
m
A
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10
m
A
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500
m
A
CiVI = VCC or GND 3.3 V pF
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 4)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd AYns
ten OE Yns
tdis OE Yns
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
TEST
CONDITIONS
TYP TYP TYP TYP
UNIT
Cpd Power dissipation capacitance f = 10 MHz pF
PRODUCT PREVIEW
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1 kΩ
1 kΩ
Output
Control
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
VCC/2VCC/2
Output
Control 0 V
VCC
Figure 2. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 3 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
0 V
1.5 V 3 V
0 V
0 V
3 V
0 V
tw
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
1.5 V 1.5 V
1.5 V 1.5 V
Figure 3. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW
SN74LVC1G126
SINGLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES224C – APRIL 1999 – REVISED FEBRUAR Y 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 5 V ± 0.5 V
VCC/2
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 11 V
Open
GND
500 Ω
500 Ω
VCC
0 V
VCC
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
Input
Output
W aveform 1
S1 at 11 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
5.5 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
11 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Output
Control
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC
VCC/2
VCC/2
Timing
Input
Data
Input
Figure 4. Load Circuit and Voltage Waveforms
PRODUCT PREVIEW
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Copyright 2000, Texas Instruments Incorporated
