General Description
The MAX8784 generates supply rails for the thin-film
transistor (TFT) liquid-crystal display (LCD) panels in TVs
and monitors. It includes a step-up regulator, a regulated
positive and a negative charge-pump, three high-current
operational amplifiers, and Dual Mode™, logic-con-
trolled, high-voltage switch control block. HVS mode
automatically increases the output voltages of the boost
regulator and the positive charge-pump to stress test
display panels during production. The MAX8784 can
operate from input voltages of 4V to 5.5V and is opti-
mized for LCD TV panel and LCD monitor applications.
The step-up DC-DC regulator provides a regulated sup-
ply voltage for TFT source drivers. The step-up regulator
is a high-frequency (1.2MHz), high-efficiency, current-
mode regulator. The step-up regulator has a built-in
110mΩ(typ) power MOSFET. The high-switching fre-
quency allows the use of ultra-small inductors and
ceramic capacitors. The current-mode architecture pro-
vides fast transient response and easy compensation.
The step-up regulator features output undervoltage pro-
tection, soft-start, internal current limit, and adjustable
output voltage by an external resistive divider.
The three operational amplifiers drive the LCD back-
plane and the gamma-correction-divider string. Each
operational amplifier has a fast slew rate (45V/µs), a
wide bandwidth (20MHz), and a high-output short-cir-
cuit current (200mA). Each op amp has rail-to-rail input
and rail-to-rail output operation.
The positive charge-pump regulator and the negative
charge-pump regulator provide regulated supply volt-
ages for the TFT gate drivers. The positive charge
pump is a two-stage charge pump, which requires no
external diodes. The output voltages of both charge
pumps are resistor adjustable. The logic-controlled
high-voltage switch allows the manipulation of the posi-
tive TFT gate-driver supply.
The MAX8784 is available in a small (5mm x 5mm), low-
profile (0.8mm), 40-pin TQFN package and operates
over the -40°C to +85°C temperature range.
Applications
LCD TVs and LCD Monitors
Features
oStep-Up Regulator Supply for LCD Panel Source
Driver
Fast Transient Response to Pulsed Load
Built-In 18V, 4A, 0.11Ωn-Channel Power
MOSFET with Lossless Current Sensing
Cycle-by-Cycle Current-Limit Comparator
90% Efficiency (5V In to 15V Out)
1.2MHz Switching Frequency
oThree High-Current 19V Operational Amplifiers
180mA Output Short-Circuit Current
45V/µs Slew Rate
20MHz Bandwidth
Rail-to-Rail Input and Output Operation
oRegulated Charge-Pump Tripler with Integrated
Diodes for TFT Gate-On Supply
oRegulated Charge Pump for TFT Gate-Off Supply
oBuilt-In Sequencing
Internal Digital Soft-Start
36V Gate-On Switch
Startup Timing Capacitors for AVDD and GON
oUndervoltage and Thermal Protection
o4V to 5.5V Input Operating Range
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
SHDN
DRVN
FBN
REF
FB
AGND
COMP
VIN
VGOFF
STEP-UP
OUTPUT
STEP-UP
OUTPUT
VCC
PGND
LX
ADEL
FBP
VGON
GDEL
SUP
POUT
C1N C2P
C1P
DRN
CTL TCON
C2N
RSET
OUT3
POS3
OUT2
OUT1
POS1
NEG1
POS2
NEG2
HVSVIN
PGND
STEP-UP
OUTPUT
STEP-UP
OUTPUT
TO
VCOM
TO
VCOM
TO
VCOM
ON/OFF
GON
MAX8784
Simplified Operating Circuit
19-0737; Rev 0; 1/07
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
PART
TEMP RANGE
PIN-
PACKAGE
PKG CODE
MAX8784ETL+
-40°C to +85°C
40 TQFN
5mm x 5mm
T4055-1
Dual Mode is a trademark of Maxim Integrated Products, Inc.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
EVALUATION KIT
AVAILABLE
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC, CTL, HVS, SHDN, ADEL, GDEL to AGND ....-0.3V to +7.5V
REF, COMP, FB, FBN, FBP to AGND.........-0.3V to (VCC + 0.3V)
POS1, NEG1, POS2, NEG2, POS3, OUT1, OUT2,
OUT3 to AGND .......................................-0.3V to (VSUP + 0.3)
PGND, BGND to AGND.........................................-0.3V to +0.3V
LX, RSET to PGND .................................................-0.3V to +22V
SUP to AGND .........................................................-0.3V to +22V
DRVN to AGND.........................................-0.3V to (VSUP + 0.3V)
C1N, C2N to AGND ..................................-0.3V to (VSUP + 0.3V)
C1P to AGND .........................................................-0.3V to +30V
POUT to C2P, C1P to C2P......................................-0.3V to +22V
C2P, POUT to AGND..............................................-0.3V to +40V
GON, DRN to AGND ..............................................-0.3V to +40V
DRN to GON............................................................-30V to +30V
REF Short Circuit to AGND.........................................Continuous
RMS VCC Current................................................................50mA
RMS DRVN Current...........................................................400mA
LX, PGND RMS Current Rating.............................................2.4A
Continuous Power Dissipation (TA= +70°C)
40-Pin TQFN (derate 35.7mW/°C above +70°C) .......2857mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Supply Range 4.0 5.5 V
VCC Undervoltage Lockout Threshold VCC rising, typical hysteresis = 50mV 2.4 2.6 2.8 V
VFB = 1.3V, not switching 1.0
VFB = 1.1V, switching, no load, VSUP disconnected,
VFBP = VCC, VFBN = 0V 46
VCC Quiescent Current
SHDN = GND 0.05
mA
SHDN Input Low Voltage 0.8 V
SHDN Input High Voltage 1.8 V
SHDN Input Current -1 +1 µA
REFERENCE
REF Output Voltage No external load 1.238 1.250 1.262 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current In regulation 10 µA
REF Undervoltage Lockout Threshold Rising edge, typical hysteresis = 200mV 1.0 1.15 V
OSCILLATOR AND TIMING
Frequency 1000 1200 1400 kHz
Oscillator Maximum Duty Cycle 87 90 93 %
Duration to Trigger Fault Condition 47 55 65 ms
AD E L, G D E L C ap aci tor C har g e C ur r ent 4 5 6 µA
ADEL, GDEL Turn-On Threshold 1.25 1.32 V
STEP-UP REGULATOR
FB = COMP, CCOMP = 1nF 1.235 1.246 1.256
FB Regulation Voltage FB = COMP, CCOMP = 1nF, +25°C to +85°C 1.238 1.246 1.256 V
FB Fault-Trip Level Falling edge 0.96 1.00 1.04 V
FB Load Regulation 0 < ILOAD < full -1 %
FB Line Regulation VCC = 4.5V to 5.5V 0.25 %/V
FB Input Bias Current VFB = 1.25V 100 200 nA
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS MIN TYP MAX UNITS
FB Transconductance ∆ICOMP = ±2.5µA, FB = COMP 75 160 280 µS
LX Current Limit VFB = 1.1V, duty cycle = 75% 3.5 4.0 4.6 A
LX On-Resistance ILX = 1.0A 0.10 0.19 Ω
Current-Sense Transresistance 0.10 0.20 0.26 V/A
Soft-Start Period 7-bit current ramp 3 ms
POSITIVE CHARGE-PUMP REGULATOR
VSUP Input Supply Range 619V
VSUP O ver vol tag e C har g e- P um p Inhi b i tV
SUP = rising, typical hysteresis = 200mV 20 21 22 V
FBP Regulation Voltage 1.225 1.25 1.275 V
FBP Line Regulation Error VSUP = 10V ~ 19V, VPOUT = 28V 0.1 %/V
FBP Input Bias Current VFBP = 1.5V -100 +100 nA
POUT Output-Voltage Range IVGON = 0mA 36 V
POUT Fixed Output Voltage HVS = VCC, IPOUT = 0mA 29.1 30 30.9 V
POUT Output Current Limit Not in dropout, VSUP = 9V, VPOUT = 24V 20 50 mA
C1N, C2N High-Side On-Resistance 9.0 Ω
C1N, C2N Low-Side On-Resistance 6.0 Ω
C1P Switch On-Resistance 15.0 Ω
C2P Switch On-Resistance 10.0 Ω
POUT Switch On-Resistance 10.0 Ω
FBP Fault-Trip Level Falling edge 0.96 1.00 1.04 V
Positive Charge-Pump Soft-Start Period 7-bit voltage ramp 3 ms
NEGATIVE CHARGE-PUMP REGULATOR
FBN Regulation Voltage VREF - VFBN 0.985 1.00 1.015 V
FBN Input Bias Current VFBN = 250mV -50 +50 nA
FBN Line Regulation Error VSUP = 11V to 19V, VGOFF = -9V, IVGOFF = -20mA 0.1 %/V
DRVN PCH On-Resistance 10 Ω
DRVN NCH On-Resistance 6Ω
FBN Fault-Trip Level Rising edge 450 mV
N eg ati ve C har g e- P um p S oft- S tar t P er i od 7-bit voltage ramp 3 ms
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
CTL Input-Low Voltage 0.8 V
CTL Input-High Voltage 1.8 V
CTL Input Current CTL = 0V or VCC -1 +1 µA
CTL-to-GON Rising Propagation Delay 200 ns
CTL-to-GON Falling Propagation Delay 200 ns
GON-to-POUT Switch On-Resistance VGDEL = 1.5V, CTL = VCC 10 20 Ω
GO N - to- P OU T S w i tch S atur ati on C ur r ent VPOUT - VGON > 5V 180 mA
GON-to-DRN Switch On-Resistance VGDEL = 1.5V, CTL = 0V 60 Ω
GON-to-DRN Switch Saturation Current VGON - VDRN > 5V 35 mA
GON-to-PGND Switch On-Resistance VGDEL = 1.0V 100 kΩ
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA= 0°C to +85°C. Typical values are at TA= +25°C, unless otherwise noted.)
PARAMETER CONDITIONS MIN TYP MAX UNITS
OPERATIONAL AMPLIFIERS
SUP Supply Range 619V
SUP Overvoltage Fault Threshold (Note 1) 19.1 20 21.0 V
SUP Supply Current Buffer configuration, VPOSx = VSUP / 2, no load 11 15 mA
Input Offset Voltage VNEGx, VPOSx = VSUP / 2, 12 mV
Input Bias Current VNEGx, VPOSx = VSUP / 2 -1 +1 µA
Input Common-Mode Voltage Range 0 VSUP V
Input Common-Mode Rejection Ratio 1V < VNEGx, VPOSx < (VSUP - 1) 80 dB
IOUTx = 1mA VSUP -
50
Output Voltage-Swing High
IOUTx = 25mA VSUP -
300
mV
IOUTx = -1mA 50
Output Voltage-Swing Low IOUTx = -25mA 300 mV
Large-Signal Voltage Gain VOUTx = 1V to VSUP - 1V 80 dB
Slew Rate CLOAD = 20pF 45 V/µs
-3dB Bandwidth CLOAD = 20pF 20 MHz
Short to VSUP / 2, sourcing 140
Short-Circuit Current Short to VSUP / 2, sinking 220 mA
HVS FUNCTION
HVS Input-Low Voltage 0.8 V
HVS Input-High Voltage 1.8 V
HVS Input Pulldown Resistance 5 10 50 kΩ
RSET Output On-Resistance HVS = VCC 520 Ω
RSET Output Leakage HVS = AGND 1 µA
ELECTRICAL CHARACTERISTICS
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Input Supply Range 4.0 5.5 V
VCC Undervoltage Lockout Threshold VCC rising, typical hysteresis = 50mV 2.4 2.8 V
VFB = 1.1V, switching, no load, AVDD isolated
from SUP, VFBP = VCC, VFBN = 0V 6
VCC Quiescent Current
SHDN = GND 0.05
mA
SHDN Input-Low Voltage 0.8 V
SHDN Input-High Voltage 1.8 V
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
REFERENCE
REF Output Voltage No external load 1.232 1.262 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current In regulation 10 µA
REF Undervoltage Lockout Threshold Rising edge, typical hysteresis = 200mV 1.15 V
OSCILLATOR AND TIMING
Frequency 950 1400 kHz
Oscillator Maximum Duty Cycle 87 93 %
Duration-to-Trigger Fault Condition 47 69 ms
ADEL, GDEL Capacitor Charge Current 4 6 µA
ADEL, GDEL Turn-On Threshold 1.18 1.32 V
STEP-UP REGULATOR
FB Regulation Voltage FB = COMP, CCOMP = 1nF 1.230 1.262 V
FB Fault Trip Level Falling edge 0.96 1.04 V
FB Transconductance ∆ICOMP = ±2.5µA, FB = COMP 75 280 µS
LX Current Limit VFB = 1.1V, duty cycle = 75% 3.0 5.0 A
LX On-Resistance ILX = 1.0A 0.19 Ω
Current-Sense Transresistance 0.10 0.26 V/A
POSITIVE CHARGE-PUMP REGULATOR
VSUP Input Supply Range 619V
VSUP Overvoltage Charge-Pump Inhibit VSUP = rising, typical hysteresis = 200mV 20 22 V
FBP Regulation Voltage 1.225 1.275 nA
POUT Output-Voltage Range IPOUT = 0mA VSUP 36 V
POUT Fixed-Output Voltage HVS = VCC, IPOUT = 0mA 29.1 30.9 V
POUT Output-Current Limit Not in dropout, VSUP = 9V VPOUT = 24V 20 mA
C1N, C2N High-Side On-Resistance 9Ω
C1N, C2N Low-Side On-Resistance 6Ω
C1P Switch On-Resistance 15 Ω
CP2 Switch On-Resistance 10 Ω
POUT Switch On-Resistance 10 Ω
FBP Fault Trip Level Falling edge 0.96 1.04 V
NEGATIVE CHARGE-PUMP REGULATOR
FBN Regulation Voltage VREF - VFBN 0.985 1.015 V
DRVN PCH On-Resistance 10 Ω
DRVN NCH On-Resistance 6Ω
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
6 _______________________________________________________________________________________
Note 1: Step-up regulator switching is disabled above the threshold. This fault is not latched.
Note 2: -40°C specs are guaranteed by design, not production tested.
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +5V, Circuit of Figure 1, AVDD = SUP = +14V, TA= -40°C to +85°C, unless otherwise noted.) (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
POSITIVE GATE-DRIVER TIMING AND CONTROL SWITCHES
CTL Input-Low Voltage 0.8 V
CTL Input-High Voltage 1.8 V
GON-to-POUT Switch On-Resistance GDEL = 1.5V, CTL = VCC 20 Ω
GON-to-POUT Switch Saturation VPOUT - VGON > 5V 180 mA
GON-to-DRN Switch On-Resistance GDEL = 1.5V, CTL = 0V 60 Ω
GON-to-DRN Switch Saturation Current VGON - VDRN > 5V 35 mA
OPERATIONAL AMPLIFIERS
SUP Supply Range 619V
SUP Overvoltage Fault Threshold (Note 1) 19.1 21.0 V
SUP Supply Current Buffer configuration, VPOS = VSUP / 2, no load 15 mA
Input Offset Voltage VNEG, VPOS = VSUP / 2 13 mV
Input Common-Mode Voltage Range 0 VSUP V
IOUT = 1mA VSUP -
50
Output-Voltage Swing High
IOUT = 25mA VSUP -
300
mV
IOUT = -1mA 50
Output-Voltage Swing Low IOUT = -25mA 300 mV
HVS FUNCTION
HVS Input-Low Voltage 0.8 V
HVS Input-High Voltage 1.8 V
HVS Input Pulldown Resistance 5 50 kΩ
RSET Output On-Resistance HVS = VCC 20 Ω
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
_______________________________________________________________________________________
7
STEP-UP REGULATOR EFFICIENCY
vs. LOAD CURRENT
MAX8784 toc01
LOAD CURRENT (mA)
EFFICIENCY (%)
600400200
79
83
87
91
95
75
0800
fOSC = 1.2MHz
VIN = 5.0V
STEP-UP REGULATOR LOAD REGULATION
MAX8784 toc02
LOAD CURRENT (mA)
AVDD ERROR (%)
600400200
-0.6
-0.2
0.2
0.6
1.0
-1.0
0 800
VCC QUIESCENT CURRENT
vs. VCC
MAX8784 toc03
VCC (V)
IVCC (mA)
5.64.8 5.24.4
1
2
3
4
5
0
4.0 6.0
SWITCHING
NOT SWITCHING
VCC QUIESCENT CURRENT
vs. TEMPERATURE
MAX8784 toc04
TEMPERATURE (°C)
IVCC (mA)
603510-15
1
2
3
4
5
0
-40 85
SWITCHING
NOT SWITCHING
STEP-UP REGULATOR SOFT-START
(HEAVY LOAD)
MAX8784 toc05
10ms/div
AVDD
LX: 10V/div
ILOAD: 500mA/div
IL: 20A/div
AVDD: 10V/div
IL
ILOAD
LX
STEP-UP REGULATOR LOAD
TRANSIENT RESPONSE
MAX8784 toc06
20µs/div
AVDD
ILOAD: 200mA/div
IL: 1A/div
AVDD: 100mV/div
(AC-COUPLED)
IL
ILOAD
STEP-UP REGULATOR PULSED
LOAD TRANSIENT RESPONSE
MAX8784 toc07
10µs/div
AVDD : 200mV/div
(AC-COUPLED)
IL : 1A/div
IAVDD : 1A/div
IAVDD : 0.3A TO 1.3A,
2µs PULSE
AVDD
IL
IAVDD
0A
0A
Typical Operating Characteristics
(Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA= +25°C, unless otherwise noted.)
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
8 _______________________________________________________________________________________
TIMER-DELAY LATCH RESPONSE
TO OVERLOAD
MAX8784 toc08
10ms/div
AVDD
AVDD: 10V/div
LX: 10V/div
IL: 5A/div
IL
LX
SWITCHING FREQUENCY vs. VCC
MAX8784 toc09
VCC (V)
SWITCHING FREQUENCY (MHz)
5.65.24.84.4
1.1
1.2
1.3
1.4
1.5
1.0
4.0 6.0
REFERENCE LOAD REGULATION
MAX8784 toc10
IREF (µA)
VREF (V)
40302010
1.2502
1.2504
1.2506
1.2508
1.2510
1.2500
050
SUP SUPPLY CURRENT
vs. SUP VOLTAGE
MAX8784 toc11
VSUP (V)
ISUP (mA)
1814 1612
8.2
8.4
8.6
8.8
9.0
8.0
10 20
ALL OUTPUTS ENABLED
POSITIVE CHARGE-PUMP REGULATOR
LINE REGULATION
MAX8784 toc12
VSUP (V)
OUTPUT-VOLTAGE ERROR (%)
1812 159
-1
0
1
2
-2
621
POSITIVE CHARGE-PUMP REGULATOR
LOAD REGULATION
MAX8784 toc13
IPOUT (mA)
OUTPUT VOLTAGE ERROR (%)
5030 4020
10
-1
0
1
2
-2
060
NEGATIVE CHARGE-PUMP REGULATOR
LINE REGULATION
MAX8784 toc114
VSUP (V)
OUTPUT-VOLTAGE ERROR (%)
16 1812 1410
-1
0
1
2
-2
820
NEGATIVE CHARGE-PUMP REGULATOR
LOAD REGULATION
MAX8784 toc15
IVGOFF (mA)
OUTPUT-VOLTAGE ERROR (%)
200100 15050
-1
0
1
2
-2
0250
VSUP = 16.0V
VSUP = 13.5V
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA= +25°C, unless otherwise noted.)
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
_______________________________________________________________________________________
9
HIGH-VOLTAGE SWITCH
CONTROL FUNCTION
MAX8784 toc16
10µs/div
CTL: 5V/div GON: 10V/div
CTL
GON
CGON = 1.5nF
RDRN = 1kΩ TO AVDD
OPERATIONAL AMPLIFIER
FREQUENCY RESPONSE
MAX8784 toc17
FREQUENCY ( MHz)
GAIN (dB)
101
-6
-3
0
3
6
-9
0.1 100
CLOAD = 56pF
CLOAD = 15pF
CLOAD = 33pF
OPERATIONAL AMPLIFIER
RAIL-TO-RAIL OPERATION
MAX8784 toc18
2µs/div
POS1: 5V/div OUT1: 5V/div
OUT1
POS1
OPERATIONAL AMPLIFIER
LOAD-TRANSIENT RESPONSE
MAX8784 toc19
2µs/div
VOUT1: 200mV/div ILOAD: 100mA/div
VOUT1
ILOAD
OPERATIONAL AMPLIFIER
LARGE-SIGNAL RESPONSE
MAX8784 toc20
200ns/div
OUT1: 5V/div POS1: 5V/div
POS1
OUT1
OPERATIONAL AMPLIFIER
SMALL-SIGNAL STEP RESPONSE
MAX8784 toc21
100ns/div
POS1: 50mV/div (AC-COUPLED)
OUT1: 50mV/div (AC-COUPLED)
POS1
OUT1
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VCC = 5V, AVDD = 14V, VPOUT = 28V, VGOFF = -9V, TA= +25°C, unless otherwise noted.)
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
10 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1 C1N Negative Terminal of Flying Capacitor C1
2 C1P Positive Terminal of Flying Capacitor C1
3 BGND Operational Amplifier and Charge-Pump Supply Ground
4 SUP Operational Amplifier and Charge-Pump Supply Input. Connect SUP to AVDD. Bypass SUP to BGND with
0.1µF capacitor.
5 POS1 Operational Amplifier Noninverting Input
6 NEG1 Operational Amplifier Inverting Input
7 OUT1 Operational Amplifier Output
8 OUT2 Operational Amplifier Output
9 NEG2 Operational Amplifier Inverting Input
10 POS2 Operational Amplifier Noninverting Input
11 POS3 Operational Amplifier Noninverting Input
12 OUT3 Operational Amplifier Output
13, 19,
20, 26 N.C. No Connection. Not internally connected.
14 ADEL
Step-Up Regulator Delay Input. Connect a capacitor from ADEL to AGND to set the delay time. A 5µA current
source charges CADEL. ADEL is internally pulled to AGND by a 20Ω resistor in shutdown. For details, see the
Power-Up Sequence section.
15 GDEL
Positive Charge-Pump Startup Delay and High-Voltage Switch Delay Input. Connect a capacitor from GDEL to
AGND to set the delay time. A 5µA current source charges CGDEL. GDEL is internally pulled to AGND by a
20Ω resistor in shutdown. For details, see the Power-Up Sequence section.
16 CTL
High-Voltage Switch Control Input. When CTL is high, the switch between GON and POUT is turned on and
the switch between GON and DRN is turned off. When CTL is low, the switch between GON and DRN is
turned on and the switch between GON and POUT is turned off. For details, see the High-Voltage Switch
Control section.
17 HVS HVS Mode Input. Connect HVS to VCC to enable HVS mode. For details, see the HVS Mode section.
18 DRVN Negative Charge-Pump Regulator Output. Connect DRVN to the negative charge-pump flying capacitor(s).
21 FBN
Negative Charge-Pump Regulator Feedback Input. Connect FBN to the center of a resistive voltage-divider
between the negative output and REF. Place the resistive voltage-divider within 5mm of FBN. For details, see
the Output-Voltage Selection section.
22 REF Reference Output. Connect a 0.22µF capacitor from REF to AGND.
23 AGND Analog Ground
24 VCC VCC Supplies the Internal Reference and Other Internal Circuitry. Connect VCC to the input supply voltage
and bypass VCC to AGND with a minimum 1µF ceramic capacitor.
25 SHDN Active-Low Shutdown. When SHDN is low, the device enters its low-power shutdown mode.
27, 28 PGND Power Ground
29, 30 LX Step-Up Regulator Switching Node. Connect inductor and Schottky diode to LX and minimize trace area for
lowest EMI.
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 11
______________________________________________________________________________________
11
Pin Description (continued)
PIN NAME FUNCTION
31 AGND Analog GND
32 RSET Open-Drain HVS Mode Output. For details, see the HVS Mode section.
33 COMP Error-Amplifier Output. Connect a series RC network from COMP to AGND for compensation.
34 FB
Step-Up Regulator Feedback Input. Connect FB to the center of a resistive voltage-divider between the step-
up regulator output and AGND. Place the resistive voltage-divider within 5mm of FB. For details, see the
Output-Voltage Selection section.
35 GON
Inter nal H i g h- V ol tag e S w i tch C om m on Ter m i nal . GO N com m on ter m i nal b etw een the hi g h- si d e p - channel
M OS FE T and b ack- to- b ack p - channel M O S FE T. G O N i s i nter nal l y p ul l ed to P G N D b y a 100kΩ r esi stor i n
shutd ow n.
36 DRN High-Voltage Switch Drain. Drain of the internal low-side, back-to-back p-channel MOSFET.
37 FBP
Positive Charge-Pump Regulator Feedback Input. Connect FBP to the center of a resistive voltage-divider
between POUT and AGND. Place the resistive voltage-divider within 5mm of FBP. For details, see the Output-
Voltage Selection section.
38 POUT Positive Charge-Pump Output and High-Voltage Switch Source Input
39 C2P Positive Terminal of Flying Capacitor C2
40 C2N Negative Terminal of Flying Capacitor C2
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
12 ______________________________________________________________________________________12 ______________________________________________________________________________________
Typical Operating Circuit
The typical operating circuit (Figure 1) of the MAX8784
is a power-supply system for TFT-LCD panels in moni-
tors and TVs. The circuit generates a +14V source-dri-
ver supply, a +28V positive gate-driver supply, and a
-9V negative gate-driver supply from a 5V ±10% input
supply. Table 1 lists the selected components and
Table 2 lists the contact information of the component
suppliers.
Detailed Description
The MAX8784 is a multiple-output power supply
designed primarily for TFT-LCD panels used in monitors
SHDN
DRVN
FBN
REF
FB
AGND
COMP
VIN = 4.5V TO 5.5V
VGOFF
-9V, 20mA
AVDD
14V, 0.75A
VCC
PGND
LX
AVDD
ADEL
FBP
VGON
28V, 20mA
GDEL
SUP
POUT
C1N C2P
C1P
DRN
CTL
AVDD
TCON
C2N
RSET
OUT3
POS3
OUT2
OUT1
POS1
NEG1
POS2
NEG2
HVS
PGND
VCOM
AVDD
VCOM
VCOM
VIN
GON
C2
0.22µF
C4
1µF
C1
1µF
C3
10µF
C5
0.1µFC6
0.1µF
C14
10µF
C15
10µF
R1
10kΩ
R2
10kΩ
R3
20kΩ
R4
187kΩ
R6
428kΩ
C8
1µF
R5
20kΩ
R7
1kΩ
C9
0.1µF
R9
100kΩ
R8
82kΩ
R11
204kΩ
R10
20kΩ
L1
3µHD1
D2
BGND
BGND
MAX8784
C7
0.1µF
C12
10µF
C13
10µF
C10
0.01µF
C11
330pF
Figure 1. Typical Operating Circuit
Table 1. Component List
C1 1µF ±10%, 6.3V X5R ceramic capacitor (0402)
TDK C1005X5R0J105K
C14, C15
10µF ±20%, 6.3V X5R ceramic capacitors (0603)
TDK C1608X5R0J106M
C12, C13
10µF ±20%, 16V X5R ceramic capacitors (1206)
TDK C3216X5R1C106M
D1 3A, 30V Schottky diode (M-flat)
Toshiba CMS02 (top mark S2)
D2 220mA, 100V dual diode (SOT23)
Fairchild MMBD4148SE (top mark D4)
L1 3.0µH, 3ADC inductor
Sumida CDRH6D28-3R0
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 13
and TVs. It has a step-up switching regulator to gener-
ate the source-driver supply, two charge-pump regula-
tors to generate the positive and negative gate-driver
supplies, and three high-current operational amplifiers.
Each regulator features an adjustable output voltage
and digital soft-start. The step-up regulator has cycle-
by-cycle current limiting and uses a fixed-frequency
current-mode control architecture with fast transient
response and excellent line regulation.
The MAX8784 features a high-voltage switch-control
block, a very stable reference output, well-defined
power-up and power-down sequences, and thermal-
overload protection. Figure 2 shows the MAX8784 func-
tional block diagram.
______________________________________________________________________________________ 13
Table 2. Component Suppliers
BOOST
SEQUENCE
CONTROL
POSITIVE-
CHARGE
PUMP
REF
REF
ADEL
FB
LX
FBP
AGND
BGND
COMP
VIN
VGON
AVDD
OSC
VIN
PGND
VCC
GDEL
SUP
POUT
C1N C2PC1P C2N
HV
SWITCH
BLOCK
GON
DRN
CTL FROM TCON
330pF
100kΩ
HVS
CONTROL
BLOCK
BGND
SUP
NEGATIVE
REGULATOR
DRVN
FBN
OUT3
POS3
OUT2
OUT1
POS1
NEG1
POS2
NEG2
HVS
RSET
SHDN
VGOFF
AVDD
AVDD
MAX8784
Figure 2. Functional Diagram
MAX8784
Step-Up Regulator
The step-up regulator employs a current-mode, fixed-
frequency PWM architecture to maximize loop band-
width and to provide fast-transient response to pulsed
loads typical of TFT-LCD panel source drivers. The
integrated MOSFET and the built-in digital soft-start
function reduce the number of external components
required to control inrush currents. The output voltage
can be set from VIN to 19V with an external resistive
voltage-divider. The regulator controls the output volt-
age and output power by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
where VAVDD is the output voltage of the step-up regulator.
PWM Control Block
Figure 3 is the block diagram of the step-up regulator
controller. On the rising edge of the internal oscillator
clock, the controller sets a flip-flop, turning on the
n-channel MOSFET, which applies the input voltage
across the inductor. The current through the inductor
ramps up linearly. The transconductance error amplifier
compares the FB voltage with the reference voltage.
The error amplifier changes the COMP voltage by
charging or discharging the COMP capacitor. The
COMP voltage is compared with a ramp, which is the
sum of the current-sense signal and a slope compensa-
tion signal. Once the ramp signal exceeds the COMP
voltage, the controller resets the flip-flop and turns off
the MOSFET. Since the inductor current is continuous, a
transverse potential develops across the inductor that
turns on the Schottky diode (D1 in Figure 1). The voltage
across the inductor then becomes the difference
between the output voltage and the input voltage. This
discharge condition forces the current through the
inductor to ramp down, transferring the energy stored in
the magnetic field to the output capacitor and the load.
The MOSFET remains off for the rest of the clock cycle.
Soft-Start and Fault Protection
The step-up regulator achieves soft-start by linearly
ramping up its internal current limit. The soft-start termi-
nates when the output reaches regulation or the full
current limit has been reached. The current limit rises
from zero to the full current limit in approximately 3ms.
The soft-start feature effectively limits the inrush current
during startup (see the Step-Up Regulator Soft-Start
waveforms in the
Typical Operating Characteristics
).
The MAX8784 monitors FB for undervoltage conditions.
If the voltage is continuously below 80% of the nominal
regulation point for approximately 55ms, the MAX8784
sets the fault latch, shutting down all outputs except the
reference and the operational amplifier.
DVV
V
AVDD IN
AVDD
≈−
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
14 ______________________________________________________________________________________
SOFT-
START
OSCILLATOR
TO FAULT
LOGIC
1.25V
FB
LX
CURRENT-LIMIT
COMPARATOR
ILIMIT
CURRENT
SENSE
PGND
1.0V
COMP
CLOCK
ERROR AMP
PWM
COMPARATOR
SLOPE COMP
UNDERVOLTAGE
COMPARATOR
FREQ
LOGIC
AND
DRIVER
SS
Figure 3. Step-Up Regulator PWM Control Block Diagram
Positive Charge-Pump Regulator
The positive charge-pump regulator is typically used to
generate the positive supply rail for the TFT LCD gate
driver ICs. The positive charge pump is a two-stage
charge pump with external pump and reservoir capaci-
tors. The output voltage is set with an external resistive
voltage-divider from its output to GND with the midpoint
connected to FBP. The charge pump includes internal
switches with drivers to control the power transfer.
Figure 4 shows the block diagram of the positive
charge pump.
The controller regulates the positive charge-pump output
voltage so that VFBP = VREF. If VFBP goes below the refer-
ence, P1 and P3 are turned on when the rising edge of
the oscillator arrives, while the drivers pull C1N to GND
and C2N to SUP. The first stage flying capacitor C6
(Figure 4) is charged by the charge-pump supply input
and the second stage flying capacitor C7 is discharged
into the reservoir capacitor C8. After a fixed period, P2 is
turned on and P1 and P3 are turned off while C1N is
pulled to SUP and C2N is pulled to GND. C7 is charged
by C6 in preparation for the next pump cycle.
The MAX8784 implements a digital variable-resistance
algorithm to control the current delivered to the output.
The algorithm sets the on-resistance of the positive
charge-pump drivers according to the load current. The
on-resistance of the drivers is set by counting the num-
ber of charging pulses in the previous 12 oscillator
cycles. As the number of charging pulses in the previ-
ous 12 oscillator cycles increases, the on-resistance of
the switch is reduced. The number of charging pulses in
the previous 12 oscillator cycles is a measure of the load
current. The period of C1N and C2N switching is 1.66µs.
The positive charge-pump regulator’s startup can be
delayed by connecting an external capacitor from
GDEL to GND. An internal constant-current source
begins charging the GDEL capacitor when the negative
charge pump reaches regulation. When the GDEL volt-
age exceeds VREF, the positive charge-pump regulator
is enabled. Each time it is enabled, the positive charge-
pump regulator goes through a soft-start routine by
ramping up its internal reference voltage from 0 to VREF
in 128 steps. The soft-start period is 3ms (typ) and FBP
fault detection is disabled during this period. The soft-
start feature effectively limits the inrush current during
startup.
The MAX8784 monitors the FBP and SUP voltage to
detect fault conditions. If VFBP is continuously below
80% of its nominal regulation point for approximately
55ms, the MAX8784 sets a fault latch, shutting down all
outputs except the reference and operational amplifiers.
If SUP exceeds the SUP overvoltage faut threshold (20V,
typ), LX switching is inhibited until SUP decreases.
Furthermore, if SUP exceeds its overvoltage charge-
pump inhibit level (21V, typ), positive charge-pump
switching is inhibited until SUP decreases to prevent
damage to the charge pump.
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 15
GND
C1N
SUP
C1P
C2P
C8
C6
C7
C2N
FBP
REF
1.1*REF
LCD DISABLE
COMPARATOR
POUT
ERROR AMPLIFIER
CONTROLLER DISABLE
P1
01
Ø2
Ø2
Ø2
Ø1
Ø1
P2
P3
Ø1
Figure 4. Positive Charge-Pump Regulator Control Block
Diagram
MAX8784
Negative Charge-Pump Regulator
The negative charge-pump regulator (see Figure 5)
generates the negative supply rail for the TFT LCD gate
driver ICs. The output voltage is set with an external
resistive voltage-divider from its output to REF with the
midpoint connected to FBN. The number of charge-
pump stages and the setting of the feedback divider
determine the output voltage of the negative charge-
pump regulator. The charge-pump controller includes a
high-side p-channel MOSFET (P4) and a low-side
n-channel MOSFET (N4) to control the power transfer
as shown in Figure 7.
The error comparator compares the feedback signal
(FBN) with a 250mV internal reference. If the feedback
signal is above the reference, the charge-pump regula-
tor turns on N4 and turns off P4 when the rising edge of
the oscillator clock arrives, level shifting C(NEG) in par-
allel with the reservoir capacitor COUT(NEG). If the volt-
age across COUT(NEG) minus a diode drop (VNEG -
VDIODE) is higher than the level-shifted flying capacitor
voltage (-VC(NEG)), charge flow from COUT(NEG) to
C(NEG) until the diode D2-B turns off. The falling edge
of the oscillator clock turns off N4 and turns on P4,
allowing VSUP to charge up flying capacitor C(NEG)
through diode D2-A. If the feedback signal is below the
reference when the rising edge of the oscillator comes,
the regulator ignores this clock edge and keeps P4 on
and N4 off.
The negative charge-pump regulator is enabled when
the step-up regulator reaches regulation. Each time it is
enabled, the negative charge-pump regulator goes
through a soft-start routine by ramping down its internal
reference voltage from 1.25V to 250mV in 128 steps.
The soft-start period is 3ms (typ) and FBN fault detec-
tion is disabled during this period. The soft-start feature
effectively limits the inrush current during startup. The
MAX8784 monitors FBN voltage for undervoltage con-
ditions. If VFBN is continuously above 450mV for
approximately 55ms, the MAX8784 sets a fault latch,
shutting down all outputs except the reference and the
operational amplifiers.
High-Voltage Switch Control
The MAX8784’s high-voltage switch control block
(Figure 6) consists of three high-voltage p-channel
MOSFETs: Q1, between POUT and GON, Q2 and Q3
between GON and DRN. Q2 and Q3 are arranged
back-to-back so that GON can be either above or
below DRN. The switch control block is enabled when
VGDEL goes above VREF.
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
16 ______________________________________________________________________________________
0.25V
OSC
ERROR
COMPARATOR
P4
N4
DRVN
GND1
SUP
FBN REF
VGOFF
D2
C
A
B
COUT
Figure 5. Negative Charge-Pump Regulator Block Diagram
GDEL
POUT
GON
DRN
5µA
VCC
Q3
Q4
SWITCH CONTROL
FAULT
SHDN
FBN SOFT-START DONE
CTL
Q2
Q1
100kΩ
Q5
VREF
Figure 6. High-Voltage Switch Control Block Diagram
When CTL is logic-high, Q1 turns on and Q2 and Q3
turn off, connecting GON to POUT. When CTL is logic-
low, Q1 turns off and Q2 and Q3 turn on, connecting
GON to DRN. GON can be discharged through a resis-
tor connected between DRN and GND.
The switch control block is enabled when GDEL is
charged to VREF. GDEL is charged by a 5µA current
after the negative charge pump reaches regulation.
The switch control block is disabled during fault mode
and during shutdown. When the switch control block is
disabled, GON is pulled to PGND with an internal
100kΩresistor.
Operational Amplifier
The MAX8784 has three operational amplifiers that are
typically used to drive the LCD backplane (VCOM) or
the gamma-correction divider string. Each operational
amplifier features 140mA/220mA (source/sink) output
short-circuit current, 45V/µs slew rate, and 20MHz
bandwidth. While the op amp is a rail-to-rail input and
output design, its accuracy is significantly degraded for
input voltages within 1V of its supply rails (SUP, BGND).
Short-Circuit Current Limit
The operational amplifier limits short-circuit current to
approximately 140mA if the output is shorted to AGND
and to approximately -220mA if the output is shorted to
AVDD. If the short-circuit condition persists, the junc-
tion temperature of the IC rises until it reaches the ther-
mal-shutdown threshold (+160°C typ). Once the
junction temperature reaches the thermal-shutdown
threshold, an internal thermal sensor immediately sets
the thermal-fault latch, shutting off the main step-up
regulator, the charge pumps, the high-voltage switch
control block, and the operational amplifier. Those por-
tions of the device remain inactive until the input volt-
age is cycled.
Driving Pure Capacitive Loads
The operational amplifier is typically used to drive the
LCD backplane (VCOM). The LCD backplane consists
of a distributed series capacitance and resistance, a
load that can be easily driven by the operational ampli-
fier. However, if the operational amplifier is used in an
application with a pure capacitive load, steps must be
taken to ensure stable operation.
As the operational amplifier’s capacitive load increases,
the amplifier’s bandwidth decreases and gain peaking
increases. A 5Ωto 50Ωsmall resistor placed between
VCOM and the capacitive load reduces peaking, but
also reduces the gain. An alternative method of reducing
peaking is to place a series RC network (snubber) in
parallel with the capacitive load. The RC network does
not continuously load the output or reduce the gain.
Reference Voltage
The reference voltage is nominally 1.246V, and can
source at least 50µA (see the
Typical Operating
Characteristics
). VCC is the input of the internal refer-
ence block. Bypass REF with a 0.22µF ceramic capaci-
tor connected between REF and GND.
Power-Up Sequence
The MAX8784 operational amplifier and internal refer-
ence are enabled when VCC exceeds its UVLO thresh-
old. A 5µA current charges ADEL after the internal
reference reaches regulation. The step-up regulator
starts the soft-start sequence after ADEL is charged to
VREF. The FB fault-detection circuit is enabled and the
negative charge-pump regulator starts up after the
step-up regulator reaches regulation. The FBN fault-
detection circuit is enabled and a 5µA current charges
GDEL after the negative charge pump reaches regula-
tion. The positive charge pump starts its soft-start
sequence after GDEL is charged to 1.25V (typ). The
FBP fault-detection circuit is enabled after the positive-
charge pump reaches regulation.
Power-Down Control
The MAX8784 disables the step-up regulator, positive
charge-pump regulator, negative charge-pump regula-
tor, and high-voltage switch control block when SHDN
is logic low. The operational amplifier depends only
upon the supply voltage at SUP.
Fault Protection
During steady-state operation, if any output of the three
regulators (step-up regulator, positive charge-pump
regulator, and negative charge-pump regulator) is not
above its respective fault-detection threshold, the
MAX8784 activates an internal fault timer. If any condi-
tion or a combination of conditions indicates a continu-
ous fault for the fault-timer duration (55ms typ), the
MAX8784 sets the fault latch. The MAX8784 shuts
down all the outputs except the reference and opera-
tional amplifiers after the fault latch is set. Toggle SHDN
or cycle the input voltage to clear the fault latch and
restart the IC.
Thermal-Overload Protection
The thermal-overload protection prevents excessive
power dissipation from overheating the MAX8784.
When the junction temperature exceeds TJ= +160°C
(typ), a thermal sensor immediately sets its fault latch,
which shuts down all the outputs. After the device cools
down, input voltage has to be recycled to restart. The
thermal-overload protection protects the controller in
the event of fault conditions. For continuous operation,
do not exceed the absolute junction temperature rating
of TJ= +150°C.
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 17
MAX8784
HVS Mode
HVS mode is designed as a special operating mode for
end-of-line panel testing. In HVS mode, higher than
normal voltages are forced to the power-supply outputs
to expose faults in the LCD panel. HVS pin is forced
logic-high to enable HVS mode. In HVS mode opera-
tion, FBP is ignored and the positive charge-pump reg-
ulates to a fixed-output voltage of 30V. To raise the
step-up regulator output voltage in HVS operation, the
open-drain RSET pin is pulled to GND. In Figure 1, resis-
tor R8 becomes parallel to R10, which reduces the feed-
back resistance during HVS operation. This special
feature allows the customer to select a resistor that sets
an appropriate HVS voltage according to the panel
requirements. The negative charge pump operates nor-
mally. Figure 7 shows the typical application circuit in
HVS mode.
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
18 ______________________________________________________________________________________
SHDN
DRVN
FBN
REF
FB
AGND
COMP
VIN = 5V
VGOFF
-9V, 20mA
AVDD
17V, 0.65A
VCC
PGND
LX
AVDD
ADEL
FBP FBP IGNORED
VPOUT = 30V
VGON
30V, 20mA
GDEL
SUP
POUT
C1N C2P
C1P
DRN
CTL
AVDD
FROM TCON
C2N
RSET
OUT3
POS3
OUT2
OUT1
POS1
NEG1
POS2
NEG2
HVSVIN
PGND
VCOM
AVDD
VCOM
VCOM
FROM SYSTEM
GON
0.22µF
C4
1µF
1µF
10µF
0.1µF0.1µF
10µF10µF
10kΩ
10kΩ
11kΩ
102kΩ
432kΩ
1µF
20kΩ
0.1µF
100kΩ
82kΩ
RSET = LOW
205kΩ
20kΩ
3µH
MAX8784
0.1µF
10µF10µF
0.01µF
330pF
Figure 7. HVS Mode Operation
Design Procedure
Step-Up Regulator
Inductor Selection
The inductance value, peak-current rating, and series
resistance are factors to consider when selecting the
inductor. These factors influence the converter’s effi-
ciency, maximum output-load capability, transient
response time, and output voltage ripple. Physical size
and cost are also important factors to be considered.
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high-inductance values minimize the cur-
rent ripple, and therefore, reduce the peak current,
which decreases core losses in the inductor and I2R
losses in the entire power path. However, large induc-
tor values also require more energy storage and more
turns of wire, which increase physical size and can
increase I2R losses in the inductor. Low-inductance val-
ues decrease the physical size, but increase the cur-
rent ripple and peak current. Finding the best inductor
involves choosing the best compromise between circuit
efficiency, inductor size, and cost.
The equations used here include a constant LIR, which
is the ratio of the inductor peak-to-peak ripple current
to the average DC inductor at the full-load current. The
best trade-off between inductor size and circuit effi-
ciency for step-up regulators generally has an LIR
between 0.3 to 0.5. However, depending on the AC
characteristics of the inductor core material and ratio of
inductor resistance to the other power-path resis-
tances, the best LIR can shift up or down. If the induc-
tor resistance is relatively high, more ripple can be
accepted to reduce the number of turns required and
increase the wire diameter. If the inductor resistance is
relatively low, increasing inductance to lower the peak
current can decrease losses throughout the power
path. If extremely thin high-resistance inductors are
used, as is common for LCD applications, the best LIR
can increase to between 0.5 and 1.0.
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficien-
cy improvements in typical operating regions.
Calculate the approximate inductor value using the typ-
ical input voltage (VIN), the maximum output current
(IAVDD(MAX)), the expected efficiency (ηTYP) taken from
an appropriate curve in the
Typical Operating Char-
acteristics
, and an estimate of LIR based on the above
discussion:
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input cur-
rent at the minimum input voltage VIN(MIN) using con-
servation of energy and the expected efficiency at that
operating point (ηMIN) taken from an appropriate curve
in the
Typical Operating Characteristics
:
Calculate the ripple current at that operating point and
the peak current required for the inductor:
The inductor’s saturation current rating and the
MAX8784’s LX current limit should exceed ILI_PEAK and
the inductor’s DC current rating should exceed
IIN(DC,MAX). For good efficiency, choose an inductor
with less than 0.1Ωseries resistance.
Considering the typical operating circuit in Figure 1, the
maximum load current (IAVDD(MAX)), with charge-pump
loads, is 820mA with a 14V output and a typical input
voltage of 5V. Choosing an LIR of 0.35 and estimating
efficiency of 85% at this operating point:
Using the circuit’s minimum input voltage (4.5V) and
estimating efficiency of 85% at that operating point:
The ripple current and the peak current are:
IA
AA
LI PEAK_...=+ ≈30 069
2335
IVVV
H V MHz A
LI RIPPLE_
..
..
.=×−
()
×× ≈
45 14 45
30 14 12 069
µ
IAV
VA
IN DCMAX(, ) .
.. .=×
×≈
082 14
45 085 300
LV
V
VV
A MHz H
I=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟≈
5
14
14 5
082 12
085
035 30
2
..
.
..µ
II
I
AVDD PEAK IN DCMAX LI RIPPLE
_(,)
_
=+
2
IVVV
LV f
LI RIPPLE IN MIN AVDD IN MIN
I AVDD SW
_() ()
=×−
()
××
IIV
V
IN DCMAX AVDD MAX AVDD
IN MIN MIN
(, ) ()
()
=×
×η
LV
V
VV
I f LIR
IIN
AVDD
AVDD IN
AVDD MAX SW
TYP
=⎛
⎝
⎜⎞
⎠
⎟−
×
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
2
()
η
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 19
MAX8784
Output-Capacitor Selection
The total output-voltage ripple has two components: the
capacitive ripple caused by the charging and dis-
charging of the output capacitance, and the ohmic ripple
due to the capacitor’s equivalent series resistance (ESR):
and:
where IAVDD_PEAK is the peak inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output-voltage ripple is typically dominated by
VAVDD_RIPPLE(C). The voltage rating and temperature
characteristics of the output capacitor must also be
considered.
Input-Capacitor Selection
The input capacitor reduces the current peaks drawn
from the input supply and reduces noise injection into
the IC. Two 10µF ceramic capacitors are used in the
typical operating circuit (Figure 1) because of the high
source impedance seen in the typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
Typically, the input capacitance can be reduced below
the values used in Figure 1.
Rectifier Diode
The MAX8784’s high switching frequency demands a
high-speed rectifier. Schottky diodes are recommend-
ed for most applications because of their fast recovery
time and low forward voltage. In general, a 2A Schottky
diode complements the internal MOSFET well.
Output-Voltage Selection
The output voltage of the step-up regulator can be
adjusted by connecting a resistive voltage-divider from
the output (AVDD) to AGND with the center tap con-
nected to FB1 (see Figure 1). Select R10 in the 10kΩto
50kΩrange. Calculate R11 with the following equation:
where VFB is the step-up regulator’s feedback set
point. Place R10 and R11 close to the IC.
Loop Compensation
Choose RCOMP (R9 in Figure 1) to set the high-frequen-
cy integrator gain for fast transient response. Choose
CCOMP (C11 in Figure 1) to set the integrator zero to
maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary RCOMP in
20% steps and CCOMP in 50% steps while observing
transient response waveforms.
If additional noise rejection is desired, add a high-fre-
quency pole by placing a 10pF to 47pF capacitor from
COMP to GND.
Charge-Pump Regulators
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement.
The number of negative charge-pump stages is given by:
where nNEG is the number of negative charge-pump
stages, VGOFF is the output of the negative charge-
pump regulator, VSUP is the supply voltage of the
charge-pump regulators, VDis the forward voltage drop
of the charge-pump diode, and VDROPOUT is the
dropout margin for the regulator. Use VDROPOUT = 0.6V.
The above equations are derived based on the assump-
tion that the first stage of the negative charge pump is
connected to ground. Sometimes fractional stages are
more desirable for better efficiency. This can be done
by connecting the first stage to VIN or another available
supply. If the first-stage charge pump is powered from
VIN, then the above equation becomes:
The MAX8784’s positive charge-pump regulator is a
fixed two-stage charge pump with built-in switches.
nVV V
VV
NEG GOFF DROPOUT IN
SUP D
=−+ +
−×2
nVV
VV
NEG GOFF DROPOUT
SUP D
=−+
−×2
CVC
IR
COMP AVDD AVDD
AVDD MAX COMP
≈×
××10 ()
RVV C
LI
COMP IN AVDD AVDD
I AVDD MAX
≈×× ×
×
251
()
RR V
V
AVDD
FB
11 10 1=× −
⎛
⎝
⎜⎞
⎠
⎟
VIR
AVDD RIPPLE ESR AVDD PEAK ESR AVDD_() _ _
≈×
VI
C
VV
Vf
AVDD RIPPLE C AVDD
AVDDT
AVDD IN
AVDD SW
_()
≈−
×
⎛
⎝
⎜⎞
⎠
⎟
VV V
AVDD RIPPLE AVDD RIPPLE C AVDD RIPPLE ESR__()_()
=+
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
20 ______________________________________________________________________________________
Pump Capacitors
Increasing the pump capacitor value (C4, C6, and C7)
lowers the effective source impedance and increases
the output-current capability. Increasing the capaci-
tance indefinitely has a negligible effect on output cur-
rent capability because the internal switch resistance
and the diode impedance place a lower limit on the
source impedance. A 0.1µF ceramic capacitor works
well in most low-current applications. For the negative
charge pump, the flying capacitor’s voltage rating must
exceed the following:
where n is the stage number in which the flying capaci-
tor appears.
For the positive charge pump, the pump capacitor’s
voltage rating must exceed the following:
Charge-Pump Output Capacitor
Increasing the output capacitance or decreasing the
ESR reduces the output ripple voltage and the peak-to-
peak transient voltage. With ceramic capacitors, the
output-voltage ripple is dominated by the capacitance
value. Use the following equation to approximate the
required capacitor value:
where COUT_CP is the output capacitor of the charge
pump, ILOAD_CP is the load current of the charge
pump, and VRIPPLE_CP is the peak-to-peak value of the
output ripple.
Output-Voltage Selection
Adjust the positive charge-pump regulator’s output volt-
age by connecting a resistive voltage-divider from
POUT to GND with the center tap connected to FBP
(Figure 1). Select the lower resistor of divider R5 in the
10kΩto 30kΩrange. Calculate upper resistor R6 with
the following equation:
where VFBP is the positive charge-pump regulator’s
feedback set point.
Adjust the negative charge-pump regulator’s output
voltage by connecting a resistive voltage-divider from
VGOFF to REF with the center tap connected to FBN
(Figure 1). Select R3 in the 20kΩto 68kΩrange.
Calculate R4 with the following equation:
where VREF - VFBN is the negative charge-pump regula-
tor’s feedback set point. Note that REF can only source
up to 50µA. Using a resistor less than 20kΩfor R2 results
in higher bias current than REF can supply.
PCB Layout Grounding
Careful PCB layout is important for proper operation.
Use the following guidelines for good PCB layout:
• Minimize the area of respective high-current loops
by placing step-up regulator’s inductor, diode, and
output capacitors near its input capacitors and its
LX and PGND pins. For the step-up regulator, the
high-current input loop goes from the positive termi-
nal of the input capacitor to the inductor, to the IC’s
LX pins, out of PGND, and to the input capacitor’s
negative terminal. The high-current output loop is
from the positive terminal of the input capacitor to
the inductor, to the output diode (D1), to the posi-
tive terminal of the output capacitors, reconnecting
between the output capacitor and input capacitor
ground terminals. Connect these loop components
with short, wide connections. Avoid using vias in
the high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
• Create a power ground island (PGND) for the step-
up regulator, consisting of the input and output
capacitor grounds and the PGND pin. Connect all
these together with short, wide traces or a small
ground plane. Create an analog ground plane
(AGND) consisting of the AGND pin, all the feed-
back-divider ground connections, the COMP,
ADEL, and GDBL capacitor ground connections,
and the device’s exposed backside pad.
• Place all feedback voltage-divider resistors as
close as possible to their respective feedback pins.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up switch-
ing noise. Care should be taken to avoid running
any feedback trace near LX, DRVN, C1N, C1P,
C2N, or C2P.
RRVV
VV
FBN GOFF
REF FBN
43=× −
−
RR V
V
POUT
FBP
65 1=× −
⎛
⎝
⎜⎞
⎠
⎟
CI
fV
OUT CP LOAD CP
OSC RIPPLE CP
__
_
≥2
VV
VxV
C SUP
C SUP
6
72
>
>
VnV
CX SUP
>×
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 21
MAX8784
• Place VCC pin and REF pin bypass capacitors as
close as possible to the device. The ground con-
nection of the VCC bypass capacitor should be
connected directly to the AGND pin with a wide
trace.
• Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
• Minimize the size of the LX node while keeping it
wide and short. Keep the LX and charge-pump
nodes away from feedback nodes (FB, FBP, and
FBN) and analog ground. Use DC traces as a
shield if necessary.
Refer to the MAX8784 evaluation kit for an example of
proper board layout.
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
22 ______________________________________________________________________________________
MAX8784
TOP VIEW
35
36
34
33
12
11
13
C1P
SUP
POS1
NEG1
OUT1
14
C1N
PGND
SHDN
VCC
PGND
LX
LX
AGND
REF
12
FB
4567
27282930 26 24 23 22
GON
DRN
DRVN
HVS
CTL
GDEL
BGND
N.C.
3
25
37
FBP ADEL
38
39
40
POUT
C2P
C2N
N.C.
OUT3
POS3
COMP
32
15
N.C.
RSET
31
16
17
18
19
20 N.C.
OUT2
NEG2
POS2 FBN
8910
21
AGND
Pin Configuration
Chip Information
TRANSISTOR COUNT: 11,424
PROCESS: BiCMOS
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
______________________________________________________________________________________ 23
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
QFN THIN.EPS
MAX8784
Step-Up Regulator, Internal Charge Pumps, Switch
Control, and Operational Amplifier for TFT LCDs
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2007 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products. Inc.
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the
package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the
package regardless of RoHS status.
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