SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Members of the Texas Instruments
Widebus
Family
D
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V
Operation and Low Static-Power
Dissipation
D
Output Ports Have Equivalent 22-Ω Series
Resistors, So No External Resistors Are
Required
D
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
D
Support Unregulated Battery Operation
Down to 2.7 V
D
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
Ioff and Power-Up 3-State Support Hot
Insertion
D
Distributed VCC and GND Pins Minimize
High-Speed Switching Noise
D
Flow-Through Architecture Optimizes PCB
Layout
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
The ’LVT162240 devices are 16-bit buffers/drivers designed specifically for low-voltage (3.3-V) VCC operation
and to improve both the performance and density of 3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters. They have the capability to provide a TTL interface to a 5-V system
environment.
These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide inverting
outputs and symmetrical active-low output-enable (OE) inputs.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
1
2
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5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
SN54LVT162240 . . . WD PACKAGE
SN74LVT162240 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ω series resistors to
reduce overshoot and undershoot.
When VCC is between 0 and 1.5 V , the devices are in the high-impedance state during power up or power down.
However , to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
The SN54L VT162240 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVT162240 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS OUTPUT
OE AY
L H L
LLH
H X Z
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
47
1A1 46
1A2 44
1A3 43
1A4
1Y1
2
1Y2
3
1Y3
5
1Y4
6
41
2A1 40
2A2 38
2A3 37
2A4
2Y1
8
2Y2
9
2Y3
11
2Y4
12
36
3A1 35
3A2 33
3A3 32
3A4
3Y1
13
3Y2
14
3Y3
16
3Y4
17
30
4A1 29
4A2 27
4A3 26
4A4
4Y1
19
4Y2
20
4Y3
22
4Y4
23
EN1
1
EN4
24
1OE
2OE
3OE
4OE
EN2
48
EN3
25
11
12
13
14
†This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1
47
46
44
43
2
3
5
6
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
48
41
40
38
37
8
9
11
12
3OE
3A1
3A2
3A3
3A4
3Y1
3Y2
3Y3
3Y4
25
36
35
33
32
13
14
16
17
4OE
4A1
4A2
4A3
4A4
4Y1
4Y2
4Y3
4Y4
24
30
29
27
26
19
20
22
23
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance
or power-off state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Current into any output in the low state, IO 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the high state, IO (see Note 2) 30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This current flows only when the output is in the high state and VO > VCC.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
SN54LVT162240 SN74LVT162240
UNIT
MIN MAX MIN MAX
UNIT
VCC Supply voltage 2.7 3.6 2.7 3.6 V
VIH High-level input voltage 2 2 V
VIL Low-level input voltage 0.8 0.8 V
VIInput voltage 5.5 5.5 V
IOH High-level output current –12 –12 mA
IOL Low-level output current 12 12 mA
∆t/∆vInput transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆VCC Power-up ramp rate 200 200 µs/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
SN54LVT162240 SN74LVT162240
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
VIK VCC = 2.7 V, II = –18 mA –1.2 –1.2 V
VOH VCC = 3 V, IOH = –12 mA 2 2 V
VOL VCC = 3 V, IOL = 12 mA 0.8 0.8 V
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
II
Control inputs VCC = 3.6 V, VI = VCC or GND ±1±1
µA
I
I
Data inp ts
VCC =36V
VI = VCC 1 1 µ
A
D
ata
i
nputs
V
CC =
3
.
6
V
VI = 0 –5 –5
Ioff VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
IOZH VCC = 3.6 V, VO = 3 V 5 5 µA
IOZL VCC = 3.6 V, VO = 0.5 V –5 –5 µA
IOZPU VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don’t care ±100* ±100 µA
IOZPD VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don’t care ±100* ±100 µA
VCC
=
3.6 V,
Outputs high 0.19 0.19
ICC
VCC
=
3
.
6
V
,
IO = 0, Outputs low 5 5 mA
VI = VCC or GND Outputs disabled 0.19 0.19
∆ICC‡VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND 0.2 0.2 mA
CiVI = 3 V or 0 4 4 pF
CoVO = 3 V or 0 9 9 pF
∗ On products compliant to MIL-PRF-38535, this parameter is not production tested.
†All typical values are at VCC = 3.3 V, TA = 25°C.
‡This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
SN54LVT162240 SN74LVT162240
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 3.3 V
± 0.3 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V VCC = 2.7 V UNIT
MIN MAX MIN MAX MIN TYP†MAX MIN MAX
tPLH
A
Y
1 4.2 5 1 2.5 4 4.6
ns
tPHL
A
Y
1 4.2 5 1 2.9 4 4.6
ns
tPZH
OE
Y
1 5 5.5 1 2.8 4.8 5.7
ns
tPZL
OE
Y
1 4.9 5.1 1 2.8 4.7 4.9
ns
tPHZ
OE
Y
1.9 4.9 5.4 2 3.5 4.7 5.2
ns
tPLZ
OE
Y
1.9 4.7 4.8 2 3.4 4.5 4.5
ns
tsk(o) 0.5 ns
†All typical values are at VCC = 3.3 V, TA = 25°C.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54LVT162240, SN74LVT162240
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCBS719 – JULY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Data Input
Timing Input 2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
2.7 V
0 V
Input Output
Control
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOL + 0.3 V
VOH – 0.3 V
≈0 V
2.7 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040048/E 12/01
48 PINS SHOWN
56
0.730
(18,54)
0.720
(18,29)
4828
0.370
(9,40)
(9,65)
0.380
Gage Plane
DIM
0.420 (10,67)
0.395 (10,03)
A MIN
A MAX
0.010 (0,25)
PINS **
0.630
(16,00)
(15,75)
0.620
0.010 (0,25)
Seating Plane
0.020 (0,51)
0.040 (1,02)
25
24
0.008 (0,203)
0.0135 (0,343)
48
1
0.008 (0,20) MIN
A
0.110 (2,79) MAX
0.299 (7,59)
0.291 (7,39)
0.004 (0,10)
M
0.005 (0,13)
0.025 (0,635)
0°–ā8°
0.005 (0,13)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUAR Y 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/F 12/97
48 PINS SHOWN
0,25
0,15 NOM
Gage Plane
6,00
6,20 8,30
7,90
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
1,20 MAX
M
0,08
0,10
0,50
0°–8°
56
14,10
13,90
48
DIM
A MAX
A MIN
PINS **
12,40
12,60
64
17,10
16,90
0,15
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
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accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
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