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2.5V to 5.5V, 0.3A 1ch
Synchronous Buck Converter integrated FET
BD9122GUL
●General Description
ROHM’s high efficiency step-down switching regulator
(BD9122GUL) is a power supply designed to produce
a low voltage including 1 volts from 5/3.3 volts power
supply line. Offers high efficiency with our original
pulse skip control technology and synchronous rectifier.
Employs a current mode control system to provide
faster transient response to sudden change in load.
●Features
■ Offers fast transient response with current mode
PWM control system.
■ Offers highly efficiency for all load range with
synchronous rectifier (Nch/Pch FET) and SLLMTM
(Simple Light Load Mode)
■ Incorporates soft-start function.
■ Incorporates thermal protection and ULVO
functions.
■ Incorporates short-current protection circuit with
time delay function.
■ Incorporates shutdown function
●Key Specifications
Input voltage range: 2.5V to 5.5V
Output voltage range: 1.0V to 2.0V
Output current: 0.3A (Max.)
Switching frequency: 1MHz(Typ.)
Pch FET ON resistance: 0.3Ω(Typ.)
Nch FET ON resistance: 0.2Ω(Typ.)
Standby current: 0μA (Typ.)
Operating temperature range: -25℃ to +85℃
●Package
VCSP50L2: 2.50mm x 1.10mm x 0.55mm
●Applications
Power supply for LSI including DSP, Micro computer
and ASIC
●Typical Application Circuit
Fig.1 Typical Application Circuit
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VCC
RITH
CITH
L
ESR
CO
RO
VOUT
○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays.
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Datasheet
●Pin Configuration
●Pin Description
Pin No.
Pin name
Pin function
A1
PGND
Nch FET source pin
A2
GND
Ground
A3
EN
Enable pin（Active High）
A4
ITH
Gm Amp output pin/Connected phase compensation capacitor
B1
SW
Pch/Nch FET drain output pin
B2
PVCC
Pch FET source pin
B3
VCC
Vcc power supply input pin
B4
ADJ
Output voltage detect pin
●Block Diagram
Fig.2 Pin Configuration
SW B1
PVcc B2
Vcc B3
ADJ B4
A1 PGND
A2 GND
A3 EN
A4 ITH
3.3V
Input
PVCC
PGND
SW
GND
Output
Gm Amp
4.7µH
VCC
R
S
Q
OSC
UVLO
TSD
+
4.7μF
VCC
VCC
CLK
SLOPE
EN
Current
Comp
10µF
Soft
Start
Current
Sense/
Protect
+
Driver
Logic
+
VREF
ITH
ADJ
RITH
CITH
R1
R2
SCP
Fig.3 Block Diagram
(Top View)
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●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Limits
Unit
VCC Voltage
VCC
-0.3 to +7 ＊1
V
PVCC Voltage
PVCC
-0.3 to +7 ＊1
V
EN Voltage
VEN
-0.3 to +7
V
SW,ITH Voltage
VSW,VIT
H
-0.3 to +7
V
Power Dissipation
Pd
660＊2
mW
Operating temperature range
Topr
-25 to +85
℃
Storage temperature range
Tstg
-55 to +150
℃
Maximum junction temperature
Tjmax
+150
℃
＊1 Pd should not be exceeded.
＊2 Derating in done 5.28mW/℃ for temperatures above Ta=25℃, Mounted on 50mm×58mm×1.6mm Glass Epoxy PCB.
●Operating Ratings (Ta=25℃)
Parameter
Symbol
Limits
Unit
Min.
Typ.
Max.
VCC Voltage
VCC *3
2.5*4
3.3
5.5
V
PVCC Voltage
PVCC *3
2.5*4
3.3
5.5
V
EN Voltage
EN
0
-
VCC
V
SW average output
Isw *3
-
-
0.3
A
Output voltage Setting Range
VOUT
1.0
-
2.0
V
＊3 Pd should not be exceeded.
＊4 In case set output voltage 1.8V or more, VccMin = 2.7V.
●Electrical Characteristics ◎(Ta=25℃, VCC=PVCC=3.3V, EN=VCC, R1=20kΩ, R2=10kΩ, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Conditions
Min.
Typ.
Max.
Standby current
ISTB
-
0
10
μA
EN=GND
Bias current
ICC
-
250
400
μA
EN Low voltage
VENL
-
GND
0.8
V
Standby mode
EN High voltage
VENH
2.0
VCC
-
V
Active mode
EN input current
IEN
-
1
10
μA
VEN=3.3V
Oscillation frequency
FOSC
0.8
1
1.2
MHz
Pch FET ON resistance
RONP
-
0.3
0.6
Ω
PVCC=3.3V
Nch FET ON resistance
RONN
-
0.2
0.5
Ω
PVCC=3.3V
ADJ Voltage
VADJ
0.780
0.800
0.820
V
Output voltage
VOUT
-
1.200
-
V
ITH SInk current
ITHSI
10
20
-
μA
VADJ=1.0V
ITH Source Current
ITHSO
10
20
-
μA
VADJ=0.6V
UVLO threshold voltage
VUVLO1
2.2
2.3
2.4
V
VCC=3→0V
UVLO release voltage
VUVLO2
2.22
2.35
2.5
V
VCC=0→3V
Soft start time
TSS
0.5
1
2
ms
Timer latch time
TLATCH
1
2
4
ms
SCP/TSD operated
Output Short circuit Threshold Voltage
VSCP
-
VOUT×0.5
-
V
VOUT=2→0V
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●Typical Performance Curves
Fig.4 Vcc - VOUT
Fig.5 VEN - VOUT
Fig.6 IOUT - VOUT
Fig.7 Ta - VOUT
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Fig.8 Efficiency
Fig.9 Ta - Fosc
Fig.10 Ta – RONN, RONP
Fig.11 Ta - VEN
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Fig.12 Ta - Icc
Fig.13 Vcc - Fosc
Fig.14 Soft start waveform
Fig.15 SW waveform Io=10mA
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Fig.16 SW waveform Io=200mA
Fig.17 Transient Response
Io=50→125mA (10μs)
Fig.18 Transient Response
o=125→50mA (10μs)
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Datasheet
●Application Information
Operation
BD9122GUL is a synchronous rectifying step-down switching regulator that achieves faster transient response by
employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode
for heavier load, while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC,
and its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a P-channel MOS FET (while a
N-channel MOS FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp)
receives two signals, a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback
control signal (FB), and issues a RESET signal if both input signals are identical to each other, and turns OFF the
P-channel MOS FET (while a N-channel MOS FET is turned ON) for the rest of the fixed period. The PWM control
repeat this operation.
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching
pulse is designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation
without voltage drop or deterioration in transient response during the mode switching from light load to heavy load or
vise versa
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current
Comp, it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching
is tuned OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces
the switching dissipation and improves the efficiency.
Fig.19 Diagram of current mode PWM control
Fig.20 PWM switching timing chart
Fig.21 SLLMTM switching timing chart
Current
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
IL(AVE)
VOUT(AVE)
SENSE
FB
Current
Comp
SET
RESET
SW
VOUT
PVCC
GND
GND
GND
0A
VOUT(AVE)
SENSE
FB
IL
Not switching
IL
OSC
Level
Shift
Driver
Logic
R
Q
S
IL
SW
ITH
Current
Comp
Gm Amp.
SET
RESET
FB
Load
SENSE
VOUT
VOUT
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Description of Operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited
during startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μF (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width
of 50 mV (Typ.) is provided to prevent output chattering.
Fig.22 Soft start, Shutdown, UVLO timing chart
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
Fig.23 Short-current protection circuit with time delay timing chart
Hysteresis 50mV
Tss
Tss
Tss
Soft start
Standby mode
Operating mode
Standby
mode
Operating mode
Standby
mode
Operating mode
Standby mode
UVLO
EN
UVLO
UVLO
VCC
EN
VOUT
t2=TLATCH
Output OFF
latch
EN
VOUT
Output Short circuit
Threshold Voltage
IL
Standby
mode
Operating mode
Operating mode
EN
Timer latch
EN
Standby
mode
IL Limit
t1<TLATCH
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Datasheet
Information on Advantages
Advantage 1：Offers fast transient response with current mode control system.
Fig.24 Comparison of transient response
Advantage 2： Offers high efficiency for all load range.
・For lighter load:
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as switching
dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and on-resistance
dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance
MOS FETs incorporated as power transistor.
ON resistance of P-channel MOS FET : 0.3Ω(Typ.)
ON resistance of N-channel MOS FET : 0.2Ω(Typ.)
Fig.25 Efficiency
Achieves efficiency improvement for heavier load.
Offers high efficiency for all load range with the improvements mentioned above.
Advantage 3：・Supplied in smaller package due to small-sized power MOS FET incorporated.
Reduces a mounting area required.
Fig.26 Example application
・Output capacitor Co required for current mode control: 10μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor
0.001
0.01
0.1
1
0
50
100
①
②
PWM
SLLMTM
①inprovement by SLLM system
②improvement by synchronous rectifier
Efficiency η[%]
Output current Io[A]
BD9122GUL(transient response IO=50mA⇔125mA)
VOUT
IOUT
VCC=3.3V
Ta=25℃
【VOUT=1.8V】
VOUT
IOUT
VCC=3.3V
Ta=25℃
【VOUT=1.8V】
Io=50→125mA
Io=125→50mA
DC/DC
Convertor
Controller
RITH
L
Co
VOUT
CITH
VCC
Cin
8mm
8mm
RITH
CITH
CIN
CO
L
CVCC
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Switching Regulator Efficiency
Efficiency ŋ may be expressed by the equation shown below:
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
1) ON resistance dissipation of inductor and FET：PD(I2R)
2) Gate charge/discharge dissipation：PD(Gate)
3) Switching dissipation：PD(SW)
4) ESR dissipation of capacitor：PD(ESR)
5) Operating current dissipation of IC：PD(IC)
1)PD(I2R)=IOUT2×(RCOIL+RON) (RCOIL[Ω]：DC resistance of inductor, RON[Ω]：ON resistance of FET, IOUT[A]：Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]：Gate capacitance of FET, f[H]：Switching frequency, V[V]：Gate driving voltage of FET)
4)PD(ESR)=IRMS2×ESR (IRMS[A]：Ripple current of capacitor, ESR[Ω]：Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]：Circuit current.)
Consideration on Permissible Dissipation and Heat Generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
Fig.27 Thermal derating curve
(VCSP50L2)
If VCC=3.3V, VOUT=1.5V, RONP=0.3Ω, RONN=0.2Ω
IOUT=0.3A, for example,
D=VOUT/VCC=1.5/3.3=0.45
RON=0.45×0.3+(1-0.45)×0.2
=0.135+0.11
=0.245[Ω]
P=0.32×0.245≒22.1[mW]
As RONP is greater than RONN in this IC, the dissipation increases as the ON duty becomes greater. With the
consideration on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Vin2×CRSS×IOUT×f
IDRIVE
3)PD(SW)=
(CRSS[F]：Reverse transfer capacitance of FET, IDRIVE[A]：Peak current of gate.)
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D：ON duty (=VOUT/VCC)
RCOIL：DC resistance of coil
RONP：ON resistance of P-channel MOS FET
RONN：ON resistance of N-channel MOS FET
IOUT：Output current
Power dissipation:Pd [W]
Ambient temperature:Ta [℃]
0
25
50
75
100
125
150
0
1.0
0.66W
VCSP50L2(2.50×1.10mm□)
ROHM standard 1 layer board
Board size：50mm×58mm
θj-a=189.4℃/W
0.8
0.6
0.4
0.2
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Selection of Components Externally Connected
1. Selection of inductor (L)
* Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
* Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for
better efficiency.
2. Selection of output capacitor (CO)
As the output rise time must be designed to fall within the soft-start time, the capacitance of output capacitor should be
determined with consideration on the requirements of equation (5):
if VOUT=1.5V, IOUT=0.3A, and TSS=1ms,
Inappropriate capacitance may cause problem in startup. 10μF to 100μF ceramic capacitor is recommended.
3. Selection of input capacitor (Cin)
A low ESR 10μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
ΔIL=
(VCC-VOUT)×VOUT
L×VCC×f
[A]・・・(1)
Appropriate ripple current at output should be 30% more or less of
the maximum output current.
ΔIL=0.3×IOUTmax. [A]・・・(2)
L=
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
Output capacitor should be selected with the consideration on the stability
region and the equivalent series resistance required to smooth ripple voltage.
Output ripple voltage is determined by the equation (4)：
ΔVOUT=ΔIL×ESR [V]・・・(4)
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
* Rating of the capacitor should be determined allowing sufficient margin
against output voltage. Less ESR allows reduction in output ripple voltage.
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (6):
IRMS=IOUT×
VOUT(VCC-VOUT)
VCC
[A]・・・(6)
√
When Vcc is twice the VOUT, IRMS=
IOUT
2
Fig.29 Output capacitor
< Worst case > IRMS(max.)
IRMS=0.3×
1.5(3.3-1.5)
3.3
=0.15[ARMS]
√ 3
.
3
Fig.30 Input capacitor
ΔIL
VCC
IL
L
Co
VOUT
Fig.28 Output ripple current
IL
VCC
L
Co
VOUT
ESR
VCC
L
Co
VOUT
Cin
If VCC=3.3V, VOUT=1.5V, and IOUTmax.=0.3A
Co≦
TSS×(Ilimit-IOUT)
VOUT
・・・(5)
Tss: Soft-start time
Ilimit: Over current detection level, 1A(Typ)
Co≦
1m×(1-0.3)
1.5
≒467 [μF]
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4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area
due to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high
frequency area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the
power amplifier output with C and R as described below to cancel a pole at the power amplifier.
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load
resistance with CR zero correction by the error amplifier.
5. Determination of output voltage
The output voltage VOUT is determined by the equation (7):
VOUT=(R2/R1+1)×VADJ・・・(7) VADJ: Voltage at ADJ terminal (0.8V Typ.)
With R1 and R2 adjusted, the output voltage may be determined as required.
Adjustable output voltage range : 1.0V to 2.0V
Use 1 kΩ to 100 kΩ resistor for R1. If a resistor of the resistance higher than
Fig.34 Determination
of output voltage
Fig.31 Open loop gain characteristics
Fig.32 Error amp phase compensation characteristics
fp=
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
1
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
fp(Min.)=
2π×ROMax.×CO
1
[Hz]←with lighter load
fp(Max.)=
2π×ROMin.×CO
1
[Hz] ←with heavier load
Zero at power amplifier
fz(Amp.)=
2π×RITH×CITH
1
GND,PGND
SW
VCC,PVCC
EN
VOUT
ITH
VCC
VOUT
Cin
RITH
CITH
L
ESR
CO
RO
VOUT
Fig.33 Typical application
fz(Amp.)= fp(Min.)
2π×RITH×CITH
1
=
2π×ROMax.×CO
1
Gain
[dB]
Phase
[deg]
A
0
0
-90
A
0
0
-90
fz(Amp.)
fp(Min.)
fp(Max.)
fz(ESR)
IOUTMin.
IOUTMax.
Gain
[dB]
Phase
[deg]
SW
ADJ
L
Co
R2
R1
Output
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This is
because when the capacitance is doubled, the capacitor ESR
reduces to half.)
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Cautions on PC Board Layout
Fig.35 Layout diagram
① For the sections drawn with heavy line, use thick conductor pattern as short as possible.
② Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the pin
PGND.
③ Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
Recommended Components Lists on Above Application
Symbol
Part
Value
Manufacturer
Series
L
Coil
2.2uH
FDK
MIPF2016D2R2
CIN
Ceramic capacitor
10uF
murata
GRM188B30J106ME47B
CO
Ceramic capacitor
10uF
murata
GRM188B30J106ME47B
CITH
Ceramic capacitor
VOUT=1.0V
2200pF
murata
GRM15 Series
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
1000pF
VOUT=2.0V
RITH
Resistance
VOUT=1.0V
6.8kΩ
ROHM
MCR006 6801
VOUT=1.2V
VOUT=1.5V
VOUT=1.8V
4.7kΩ
MCR006 4701
VOUT=2.0V
* The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit characteristics should be checked on your
application carefully before use. Be sure to allow sufficient margins to accommodate variations between external devices and this IC when employing the
depicted circuit with other circuit constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC pins, and a schottky barrier
diode established between the SW and PGND pins.
SW
PVcc
Vcc
ADJ
PGND
GND
EN
ITH
CO
GND
VOUT
VCC
L
①
③
RITH
CITH
CIN
②
EN
R2
R1
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Datasheet
●I/O equivalent circuit
Fig.36 I/O equivalent circuit
EN
・EN pin
・SW pin
PVCC
SW
PVCC
PVCC
ITH
・ITH pin
VCC
・ADJ pin
ADJ
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© ROHM Co., Ltd. All rights reserved. 16/17 02.MAR.2012 Rev.001
TSZ22111･15･001
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Datasheet
●Operational Notes
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed
the absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Operation in Strong electromagnetic field
Be noted that using the IC in the strong electromagnetic radiation can cause operation failures.
5. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not
be used thereafter for any operation originally intended.
6. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
7. Input to IC terminals
This is a monolithic IC with P+ isolation between P-substrate and each element as illustrated below. This P-layer and
the N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 37.
○P-N junction works as a parasitic diode if the following relationship is satisfied; GND>Terminal A (at resistor side), or
GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Fig.37 Simplified structure of monorisic IC
8. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
Status of this document
The Japanese version of this document is formal specification. A customer may use this translation version only for a reference
to help reading the formal version.
If there are any differences in translation version of this document formal version takes priority.
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Datasheet
VCSP50L2
(TOP VIEW)
●Ordering Information
B
D
9
1
2
2
G
U
L
-
E2
Package
GUL: VCSP50L2
Packaging and forming specification
E2: Embossed tape and reel
(VCSP50L2)
●Physical Dimension, Tape and Reel Information
●Marking Diagram
(Unit:mm)
VCSP50L2
<Dimension>
Direction of feed
Tape
Quantity
Direction
of feed
Embossed carrier tape
3000pcs
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand.)
<Tape and Reel information>
Reel
1Pin
1234
1234
1234
1234
1234
1234
※When you order , please order in times the amount of package quantity.
LOT No.
1PIN MARK
9 1 2 2
Datasheet
Datasheet
Notice - Rev.001
Notice
●Precaution for circuit design
1) The products are designed and produced for application in ordinary electronic equipment (AV equipment, OA
equipment, telecommunication equipment, home appliances, amusement equipment, etc.). If the products are to be
used in devices requiring extremely high reliability (medical equipment, transport equipment, aircraft/spacecraft,
nuclear power controllers, fuel controllers, car equipment including car accessories, safety devices, etc.) and whose
malfunction or operational error may endanger human life and sufficient fail-safe measures, please consult with the
ROHM sales staff in advance. If product malfunctions may result in serious damage, including that to human life,
sufficient fail-safe measures must be taken, including the following:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits in the case of single-circuit failure
2) The products are designed for use in a standard environment and not in any special environments. Application of the
products in a special environment can deteriorate product performance. Accordingly, verification and confirmation of
product performance, prior to use, is recommended if used under the following conditions:
[a] Use in various types of liquid, including water, oils, chemicals, and organic solvents
[b] Use outdoors where the products are exposed to direct sunlight, or in dusty places
[c] Use in places where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2,
and NO2
[d] Use in places where the products are exposed to static electricity or electromagnetic waves
[e] Use in proximity to heat-producing components, plastic cords, or other flammable items
[f] Use involving sealing or coating the products with resin or other coating materials
[g] Use involving unclean solder or use of water or water-soluble cleaning agents for cleaning after soldering
[h] Use of the products in places subject to dew condensation
3) The products are not radiation resistant.
4) Verification and confirmation of performance characteristics of products, after on-board mounting, is advised.
5) In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse) is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
6) De-rate Power Dissipation (Pd) depending on Ambient temperature (Ta).
When used in sealed area, confirm the actual ambient temperature.
7) Confirm that operation temperature is within the specified range described in product specification.
8) Failure induced under deviant condition from what defined in the product specification cannot be guaranteed.
●Precaution for Mounting / Circuit board design
1) When a highly active halogenous (chlorine, bromine, etc.) flux is used, the remainder of flux may negatively affect
product performance and reliability.
2) In principle, the reflow soldering method must be used; if flow soldering method is preferred, please consult with the
Company in advance.
Regarding Precaution for Mounting / Circuit board design, please specially refer to ROHM Mounting specification
●Precautions Regarding Application Examples and External Circuits
1) If change is made to the constant of an external circuit, allow a sufficient margin due to variations of the characteristics
of the products and external components, including transient characteristics, as well as static characteristics.
2) The application examples, their constants, and other types of information contained herein are applicable only when
the products are used in accordance with standard methods. Therefore, if mass production is intended, sufficient
consideration to external conditions must be made.
Datasheet
Datasheet
Notice - Rev.001
●Precaution for Electrostatic
This product is Electrostatic sensitive product, which may be damaged due to Electrostatic discharge. Please take proper
caution during manufacturing and storing so that voltage exceeding Product maximum rating won't be applied to products.
Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron, isolation from
charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
●Precaution for Storage / Transportation
1) Product performance and soldered connections may deteriorate if the products are stored in the following places:
[a] Where the products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] Where the temperature or humidity exceeds those recommended by the Company
[c] Storage in direct sunshine or condensation
[d] Storage in high Electrostatic
2) Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using products of which storage time is
exceeding recommended storage time period .
3) Store / transport cartons in the correct direction, which is indicated on a carton as a symbol. Otherwise bent leads may
occur due to excessive stress applied when dropping of a carton.
4) Use products within the specified time after opening a dry bag.
●Precaution for product label
QR code printed on ROHM product label is only for internal use, and please do not use at customer site. It might contain a
internal part number that is inconsistent with an product part number.
●Precaution for disposition
When disposing products please dispose them properly with a industry waste company.
●Precaution for Foreign exchange and Foreign trade act
Since concerned goods might be fallen under controlled goods prescribed by Foreign exchange and Foreign trade act,
please consult with ROHM in case of export.
●Prohibitions Regarding Industrial Property
1) Information and data on products, including application examples, contained in these specifications are simply for
reference; the Company does not guarantee any industrial property rights, intellectual property rights, or any other
rights of a third party regarding this information or data. Accordingly, the Company does not bear any responsibility for:
[a] infringement of the intellectual property rights of a third party
[b] any problems incurred by the use of the products listed herein.
2) The Company prohibits the purchaser of its products to exercise or use the intellectual property rights, industrial
property rights, or any other rights that either belong to or are controlled by the Company, other than the right to use,
sell, or dispose of the products.