Voltage-to-Frequency
and Frequency-to-Voltage
CONVERTER
FEATURES
●HIGH LINEARITY: 12 to 14 bits
±0.005% max at 10kHz FS
±0.03% max at 100kHz FS
±0.1% typ at 1MHz FS
●V/F OR F/V CONVERSION
●6-DECADE DYNAMIC RANGE
●GAIN DRIFT: 20ppm/°C max
●OUTPUT TTL/CMOS COMPATIBLE
APPLICATIONS
●INEXPENSIVE A/D AND D/A CONVERTER
●DIGITAL PANEL METERS
●TWO-WIRE DIGITAL TRANSMISSION WITH
NOISE IMMUNITY
●FM MOD/DEMOD OF TRANSDUCER
SIGNALS
●PRECISION LONG TERM INTEGRATOR
●HIGH RESOLUTION OPTICAL LINK FOR
ISOLATION
●AC LINE FREQUENCY MONITOR
●MOTOR SPEED MONITOR AND CONTROL
Comparators
–7.5V Ref
Flip-
flop
Common
f
OUT
f
IN
One-shot
V
OUT
+V
CC
–In
+In
–V
CC
C
1
DESCRIPTION
The VFC320 monolithic voltage-to-frequency and frequency-to-
voltage converter provides a simple low cost method of convert-
ing analog signals into digital pulses. The digital output is an
open collector and the digital pulse train repetition rate is propor-
tional to the amplitude of the analog input voltage. Output pulses
are compatible with TTL, and CMOS logic families.
High linearity (0.005%, max at 10kHz FS) is achieved with
relatively few external components. Two external resistors and
two external capacitors are required to operate. Full scale fre-
quency and input voltage are determined by a resistor in series
with –In and two capacitors (one-shot timing and input amplifier
integration). The other resistor is a non-critical open collector
pull-up (fOUT to +VCC). The VFC320 is available in two perfor-
mance grades. The VFC320 is specified for the –25°C to +85°C,
range.
VFC320
SBVS017A – AUGUST 2001
www.ti.com
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1982, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VFC320
VFC320
2SBVS017A
✻
Specification the same as for VFC320BP.
ELECTRICAL CHARACTERISTICS
At TA = +25°C and ±15VDC power supply, unless otherwise noted.
NOTES: (1) A 25% duty cycle at full scale (0.25mA input current) is recommended where possible to achieve best linearity. (2) Determined by R
IN
and full scale current range
constraints. (3) Adjustable to zero. See Offset and Gain Adjustment section. (4) Linearity error at any operating frequency is defined as the deviation from a straight line drawn between
the full scale frequency and 0.1% of full scale frequency. See Discussion of Specifications section. (5) When offset and gain errors are nulled, at an operating temperature, the linearity
error determines the final accuracy. (6) For e
1
= 0 typical linearity errors are: 0.01% at 10kHz, 0.2% at 100kHz, 0.1% at 1MHz. (7) Exclusive of external components’ drift.
(8) FSR = Full Scale Range (corresponds to full scale and full scale input voltage.) (9) Positive drift is defined to be increasing frequency with increasing temperature.
(10) One pulse of new frequency plus 50ns typical.
VFC320BP VFC320CP
PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
V/F CONVERTER fOUT = VIN/7.5 R1C1, Figure 4
INPUT TO OP AMP
Voltage Range(1) Fig. 4 with e2 = 0 >0 Note 2 V
Fig. 4 with e1 = 0 <0 –10 V
Current Range(1) IIN = VIN/RIN +0.25 +750 ✻✻µA
Bias Current
Inverting Input 48 ✻✻ nA
Noninverting Input 10 30 ✻✻ nA
Offset Voltage(3) ±0.15 ✻mV
Offset Voltage Drift ±5✻µV/°C
Differential Impedance 300 || 5 650 || 5 ✻✻ kΩ || pF
Common-Mode
Impedance 300 || 3 500 || 3 ✻✻ kΩ || pF
ACCURACY
Linearity Error (1) (4) (5) Fig. 4 with e2 = 0(6)
0.01Hz ≤ fOUT ≤ 10kHz ±0.004 ±0.005 ±0.0015 ±0.002 % FSR
0.1Hz ≤ fOUT ≤ 100kHz ±0.008 ±0.030 ✻✻% FSR
1Hz ≤ fOUT ≤ 1MHz ±0.1 ✻% FSR
Offset Error Input
Offset Voltage(3) ±15 ✻ppm FSR
Offset Drift(7) ±0.5 ✻ppm FSR/°C
Gain Error(3) ±5±10 ✻✻% FSR
Gain Drift(7) f = 10kHz 50 20 ppm FSR/°C
Full Scale Drift f = 10kHz 50 20 ppm FSR/°C
(Offset Drift and Gain Drift) (7)(8)(9)
Power Supply Sensitivity ±VCC = 14VDC to 18VDC ±0.015 ✻% FSR%
DYNAMIC RESPONSE
Full Scale Frequency CLOAD ≤ 50pF 1 ✻MHz
Dynamic Range 6 ✻Decades
Settling Time (V/F) to Specified Linearity
For a Full Scale Input Step Note 10 ✻
Overload Recovery <50% Overload Note 10 ✻
OPEN COLLECTOR OUTPUT
Voltage, Logic “0”ISINK = 8mA, max 0.4 ✻V
Leakage Current, Logic “1”VO = 15V 0.01 1.0 ✻✻ µA
Voltage, Logic “1”External Pull-up Resistor
Required (See Figure 4) VPU ✻V
Duty Cycle at FS For Best Linearity 25 ✻%
Fall Time IOUT = 5mA, CLOAD = 500pF 100 ✻ns
F/V CONVERTER VOUT = 7.5 R1C1 fIN, Figure 9
INPUT TO COMPARATOR
Impedance 50 || 10 150 || 10 ✻✻ kΩ || pF
Logic “1”+1.0 +VCC ✻✻V
Logic “0”–VCC –0.05 ✻✻V
Pulse-width Range 0.25 ✻µs
OUTPUT FROM OP AMP
Voltage IO = 6mA 0 to +10 ✻V
Current VO = 7VDC +10 ✻mA
Impedance Closed-Loop 0.1 ✻Ω
Capacitive Load Without Oscillation 100 ✻pF
POWER SUPPLY
Rated Voltage ±15 ✻V
Voltage Range ±13 ±20 ✻✻V
Quiescent Current ±6.5 ±7.5 ✻✻ mA
TEMPERATURE RANGE
Specification
B and C Grades –25 +85 ✻✻°C
S Grade –55 +125 °C
Operating
B and C Grades –40 +85 ✻✻°C
S Grade –55 +125 °C
Storage –65 +150 ✻✻°C
VFC320 3
SBVS017A
PACKAGE SPECIFIED
DRAWING PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT
PRODUCT PACKAGE NUMBER DESIGNATOR RANGE MARKING NUMBER(1) MEDIA
VFC320BP DIP-14 010 N –40°C to +85°C
VFC320CP DIP-14 010 N –40°C to +85°C
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces
of “VFC320BP/2K5” will get a single 2500-piece Tape and Reel.
Top View DIP
+VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
–VCC
fOUT
–In
NC
One-Shot
Capacitor
VOUT
Common
+In
NC
NC
Comparator
Input
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltage................................................................................... ±20V
Output Sink Current at fOUT ............................................................... 50mA
Output Current at VOUT ................................................................... +20mA
Input Voltage, –Input.......................................................................... ±VCC
Input Voltage, +Input.......................................................................... ±VCC
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
VFC320
4SBVS017A
DISCUSSION OF
SPECIFICATIONS
LINEARITY
Linearity is the maximum deviation of the actual transfer
function from a straight line drawn between the end points
(100% full scale input or frequency and 0.1% of full scale
called zero.) Linearity is the most demanding measure of
voltage-to-frequency converter performance, and is a func-
tion of the full scale frequency. Refer to Figure 1 to deter-
mine typical linearity error for your application. Once the
full scale frequency is chosen, the linearity is a function of
operating frequency as it varies between zero and full scale.
Examples for 10kHz full scale are shown in Figure 2. Best
linearity is achieved at lower gains (∆fOUT/∆VIN) with opera-
tion as close to the chosen full scale frequency as possible
The high linearity of the VFC320 makes the device an
excellent choice for use as the front end of Analog-to-Digital
(A/D) converters with 12- to 14-bit resolution, and for
highly accurate transfer of analog data over long lines in
noisy environments (2-wire digital transmission.)
Figure
Figure
Figure 1. Linearity Error vs Full Scale Frequency.
Figure 2. Linearity Error vs Operating Frequency.
0 2k 4k 6k 8k 10k
Operatin
g
Frequenc
y
(Hz)
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
Typical Linearity jErrorf (% of FSR)
1k 3k 5k 7k 9k
B Grade
C Grade
f
FULL SCALE
= 10kHz
Typical, T
A
= +25°C
FREQUENCY STABILITY VS TEMPERATURE
The full scale frequency drift of the VFC320 versus tem-
perature is expressed as parts per million of full scale range
per °C. As shown in Figure 3, the drift increases above
10kHz. To determine the total accuracy drift over tempera-
ture, the drift coefficients of external components (espe-
cially R1 and C1) must be added to the drift of the VFC320.
RESPONSE
Response of the VFC320 to changes in input signal level is
specified for a full scale step, and is 50ns plus 1 pulse of the
new frequency. For a 10V input signal step with the VFC320
operating at 100kHz full scale, the settling time to within
±0.01% of full scale is 10µs.
THEORY OF OPERATION
The VFC320 monolithic voltage-to-frequency converter pro-
vides a digital pulse train output whose repetition rate is
directly proportional to the analog input voltage. The circuit
shown in Figure 4 is composed of an input amplifier, two
comparators and a flip-flop (forming a on-shot), two switched
current sinks, and an open collector output transistor stage.
Essentially the input amplifier acts as an integrator that
produces a two-part ramp. The first part is a function of the
input voltage, and the second part is dependent on the input
voltage and current sink. When a positive input voltage is
applied at VIN, a current will flow through the input resistor,
causing the voltage at VOUT to ramp down toward zero,
according to dV/dt = VIN/R1C1. During this time the con-
stant current sink is disabled by the switch. Note, this period
is only dependent on VIN and the integrating components.
When the ramp reaches a voltage close to zero, comparator
A sets the flip-flop. This closes the current sink switches as
well as changing fOUT from logic 0 to logic 1. The ramp now
begins to ramp up, and 1mA charges through C1 until VC1 =
–7.5V. Note this ramp period is dependent on the 1mA
current sink, connected to the negative input of the op amp,
as well as the input voltage. At this –7.5V threshold point
C1, comparator B resets the flip-flop, and the ramp voltage
Figure 3. Full Scale Drift vs Full Scale Frequency.
1k 1M
Full Scale Fre
q
uenc
y
(
Hz
)
1000
10
Typical Full Scale Temp Drift
(ppm of FSR/°C)
10k 100k
100
C Grade
B and S Grades
1k 1M
Full Scale Fre
q
uenc
y
(
Hz
)
0.10
0.001
Typical Linearity Error (% of FSR)
10k 100k
0.01
D
FS
= 0.25
T
A
= +25°C
VFC320 5
SBVS017A
(8)
In the time t1 + t2 the integrator capacitor C2 charges and
discharges but the net voltage change is zero.
Thus ∆Q = 0 = IIN t1 + (IIN – IA) t2
So that IIN (t1 + t2) = IA t2
But since t1 + t2 = and IIN =
fOUT =
In the time t1, IB charges the one-shot capacitor C1 until its
voltage reaches –7.5V and trips comparator B.
Thus t2 =
Using in yield f V
RC I
I
OUT IN B
A
() () .
76 75 11
=•
Since IA = IB the result is
fOUT =
Since the integrating capacitor, C2, affects both the rising
and falling segments of the ramp voltage, its tolerance and
temperature coefficient do not affect the output frequency. It
should, however, have a leakage current that is small com-
pared to IIN, since this parameter will add directly to the gain
error of the VFC. C1, which controls the one-shot period,
should be very precise since its tolerance and temperature
coefficient add directly to the errors in the transfer function.
begins to ramp down again before the input amplifier has a
chance to saturate. In effect the comparators and flip-flop
form a one-shot whose period is determined by the internal
reference and a 1mA current sink plus the external capacitor,
C1. After the one-shot resets, fOUT changes back to logic 0
and the cycle begins again.
The transfer function for the VFC320 is derived for the
circuit shown in Figure 4. Detailed waveforms are shown in
Figure 5.
fOUT = 1
t1 + t2
0V
–7.5V
∆VOUT
t1t2
VFC Output
fOUT
One-shot
VC1
Integrator Output
VOUT
FIGURE 5. Integrator and VFC Output Timing.
(1)
FIGURE 4. Functional Block Diagram of the VFC320.
fOUT
VIN
1R1
IA R2 R2
VIN
CIN 7.5
IB
7.5 R1 C1
VIN
(3)
(2)
(4), (5)
(6)
(7)
(9)
Comparators Flip-
flop
Common
f
OUT
f
IN
One-shot
V
OUT
1
5411
I
A
I
IN
e
1
e
2
Switch
C
1
One-shot
Capacitor
–V
CC
12
+V
CC
7
Pull-up
Resitor R
2
1013
Input
Amp
Constant
Current Sinks
(1mA)
–7.5V
Ref B
Integrating
Capacitor
R
1
Input Resistor
Q
1
C
2
I
B
A
For Postive Input Voltages use e
1
, short e
2
.
For Negative Input Voltages use e
2
, short e
1
.
For Differental Input Voltages use e
1 and
e
2
.
V
IN:
f
OUT
=V
IN
7.5 R
1
C
1
+V
PULL-UP
(V
PU
)
(5V to 15V Typically)
14
VFC320
6SBVS017A
IIN max
The operation of the VFC320 as a highly linear frequency-
to-voltage converter, follows the same theory of operation as
the voltage-to-frequency converter. e1 and e2 are shorted and
FIN is disconnected from VOUT. FIN is then driven with a
signal which is sufficient to trigger comparator A. The one-
shot period will then be determined by C1 as before, but the
cycle repetition frequency will be dictated by the digital
input at FIN.
DUTY CYCLE
The duty cycle (D) of the VFC is the ratio of the one-shot
period (t2) or pulse width, PW, to the total VFC period (t1 +
t2). For the VFC320, t2 is fixed and t1 + t2 varies as the input
voltage. Thus the duty cycle, D, is a function of the input
voltage. Of particular interest is the duty cycle at full scale
frequency, DFS, which occurs at full scale input. DFS is a user
determined parameter which affects linearity.
Dt
tt PW f
FS FS
=+=•
2
12
Best linearity is achieved when DFS is 25%. By reducing
equations (7) and (9) it can be shown that
DFS = =
Thus DFS = 0.25 corresponds to IIN max = 0.25mA.
INSTALLATION AND
OPERATING INSTRUCTIONS
VOLTAGE-TO-FREQUENCY CONVERSION
The VCF320 can be connected to operate as a V/F converter
that will accept either positive or negative input voltages, or
an input current. Refer to Figures 6 and 7.
FIGURE 7. Connection Diagram for V/F Conversion,
Negative Input Voltages.
EXTERNAL COMPONENT SELECTION
In general, the design sequence consists of: (1) choosing
fMAX, (2) choosing the duty cycle at full scale (DFS = 0.25
typically), (3) determining the input resistor, R1 (Figure 4),
(4) calculating the one-shot capacitor, C1, (5) selecting the
integrator capacitor C2, and (6) selecting the output pull-up
resistor, R2.
Input Resistors R1 and R3
The input resistance (R1 and R3 in Figures 6 and 7) is
calculated to set the desired input current at full scale input
voltage. This is normally 0.25mA to provide a 25% duty
cycle at full scale input and output. Values other than DFS =
0.25 may be used but linearity will be affected.
The nominal value is R1 is
R1 =
If gain trimming is to be done, the nominal value is reduced
by the tolerance of C1 and the desired trim range. R1 should
have a very-low temperature coefficient since its drift adds
directly to the errors in the transfer function.
One-Shot Capacitor, C1
This capacitor determines the duration of the one-shot pulse.
From equation (9) the nominal value is
C1 NOM =
For the usual 25% duty at fMAX = VIN/R1 = 0.25mA there is
approximately 15pF of residual capacitance so that the
design value is
C1(pF) = – 15
(11)
(12)
(10)
VIN max / R1
1mA 1mA
0.25mA
VINmax
VIN
7.5 R1 fOUT
33 • 106
fFS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
–VCC(1)
NC NC
NC
+VCC(1)
VIN
C2Integrator Capacitor
Gain Adjustment
IIN
R3
R1
R5
R4
+15V
–15V
One-shot
Capacitor
C1
R2
+VPU
fOUT
NOTE:
(
1
)
B
y
pass with 0.01
µ
FPin numbers in squares
refer to DIP packa
g
e.
Offset Adj.
FIGURE 6. Connection Diagram for V/F Conversion,
Positive Input Voltages.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
–V
CC(1)
NC NC
NC
+V
CC(1)
C
2
Integrator Capacitor
Gain AdjustmentI
IN
R
1
R
3
R
5
R
4
+15V
–15V
One-shot
capacitor
C
1
R
2
+V
PU
f
OUT
NOTE:
(
1
)
B
y
pass with 0.01
µ
FPin numbers in squares
refer to DIP package.
Offset Adj.
V
IN
VFC320 7
SBVS017A
where fFS is the full scale output frequency in Hz. The
temperature drift of C1 is critical since it will add directly to
the errors of the transfer function. An NPO ceramic type is
recommended. Every effort should be made to minimize
stray capacitance associated with C1. It should be mounted
as close to the VFC320 as possible. Figure 8 shows pulse
width and full scale frequency for various values of C1 at
DFS = 25%.
FIGURE 8. Output Pulse Width (DFS = 0.25) and Full Scale
Frequency vs External One-shot Capacitance.
OFFSET AND GAIN ADJUSTMENT PROCEDURES
To null errors to zero, follow this procedure:
1. Apply an input voltage that should produce an output
frequency of 0.001 • full scale.
2. Adjust R5 for proper output.
3. Apply the full scale input voltage.
4. Adjust R3 for proper output.
5. Repeat stems 1 through 4.
If nulling is unnecessary for the application, delete R4 and
R5, and replace R3 with a short circuit.
POWER SUPPLY CONSIDERATIONS
The power supply rejection ratio of the VFC320 is 0.015%
of FSR/% max. To maintain ±0.015% conversion, power
supplies which are stable to within ±1% are recommended.
These supplies should be bypassed as close as possible to the
converter with 0.01µF capacitors.
Internal circuitry causes some current to flow in the common
connection (pin 11 on DIP package). Current flowing into
the fOUT pin (logic sink current) will also contribute to this
current. It is advisable to separate this common lead ground
from the analog ground associated with the integrator input
to avoid errors produced by these currents flowing through
any ground return impedance.
DESIGN EXAMPLE
Given a full scale input of +10V, select the values of R1, R2,
R3, C1, and C2 for a 25% duty cycle at 100kHz maximum
operation into one TTL load. See Figure 6.
Selecting C1 (DFS = 0.25)
C1 = [(33 • 106)/fMAX] – 15 [(66 • 106)/fMAX] – 15
if DFS = 0.5
= [(33 • 106)/100kHz] – 15
= 315pF
Choose a 300pF NPO ceramic capacitor with 1% to 10%
tolerance.
Selecting R1 and R3 (DRS = 0.25)
R1 + R3 = VIN max/0.25mA VIN max/0.5mA
if DFS = 0.5
= 10V/0.25mA
= 40kΩ
Choose 32.4kΩ metal film resistor with 1% tolerance and
R3 = 10kΩ cermet potentiometer.
Selecting C2
C2 = 102/FMAX
= 102/100kHz
= 0.001µF
Choose a 0.001µF capacitor with ±5% tolerance.
Integrating Capacitor, C2
Since C2 does not occur in the V/F transfer function equation
(9), its tolerance and temperature stability are not important;
however, leakage current in C2 causes a gain error. A
ceramic type is sufficient for most applications. The value of
C2 determines the amplitude of VOUT. Input amplifier satu-
ration, noise levels for the comparators and slew rate limit-
ing of the integrator determine a range of acceptable values,
100/fFS; if fFS ≤ 100kHz
C2 (µF) = 0.001; if 100kHz < fFS ≤ 500kHz
0.0005; if fFS > 500kHz
Output Pull Up Resistor R2
The open collector output can sink up to 8mA and still be
TTL-compatible. Select R2 according to this equation:
R2 min (Ω) VPULLUP/(8mA – ILOAD)
A 10% carbon film resistor is suitable for use as R2.
Trimming Components R3, R4, R5
R5 nulls the offset voltage of the input amplifier. It should
have a series resistance between 10kΩ and 100kΩ and a
temperature coefficient less than 100ppm/°C. R4 can be a
10% carbon film resistor with a value of 10MΩ.
R3 nulls the gain errors of the converter and compensates for
initial tolerances of R1 and C1. Its total resistance should be
at least 20% of R1, if R1 is selected 10% low. Its temperature
coefficient should be no greater than five times that of R1 to
maintain a low drift of the R3 - R1 series combination.
(13)
10
1
Capacitance C
1
(pF)
10,000
1000
100
10
1
Pulse Width (µs)
10
6
10
5
10
4
10
3
10
2
Full Scale Frequency (Hz)
10
2
10
3
10
4
10
5
Full Scale Frequency
Pulse Width
VFC320
8SBVS017A
Selecting R2
R2 = VPULLUP/(8mA – ILOAD)
=5V/(8mA – 1.6mA), one TTL-load = 1.6mA
=781Ω
Choose a 750Ω 1/4-watt carbon compensation resistor with
±5% tolerance.
FREQUENCY-TO-VOLTAGE CONVERSION
To operate the VFC320 as a frequency-to-voltage converter,
connect the unit as shown in Figure 9. To interface with
TTL-logic, the input should be coupled through a capacitor,
and the input to pin 10 biased near +2.5V. The converter will
detect the falling edges of the input pulse train as the voltage
at pin 10 crosses zero. Choose C3 to make t = 0.1t (see
Figure 9). For input signals with amplitudes less than 5V,
pin 10 should be biased closer to zero to insure that the input
signal at pin 10 crosses the zero threshold.
Errors are nulled using 0.001 • full scale frequency to null
offset, and full scale frequency to null the gain error. The
procedure is given on this page. Use equations from V/F
calculations to find R1, R3, R4, C1 and C2.
TYPICAL APPLICATIONS
Excellent linearity, wide dynamic range, and compatible
TTL, DTL, and CMOS digital output make the VFC320
ideal for a variety of VFC applications. High accuracy
allows the VFC320 to be used where absolute or exact
readings must be made. It is also suitable for systems
requiring high resolution up to 14 bits
Figures 10-14 show typical applications of the VFC320.
FIGURE 9. Connection Diagram for F/V Conversion.
FIGURE 10. Inexpensive A/D with Two-Wire Digital Transmission Over Twisted Pair.
FIGURE 11. Inexpensive Digital Panel Meter.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Input
Amp
Switch
One-
shot
NC
NC
–V
CC(1)
NC NC
NC
+V
CC(1)
C
2
Integrator Capacitor
R
1
R
3
R
5
R
4
+15V
–15V
One-shot
Capacitor C
1
f
OUT
NOTE:
(
1
)
B
y
pass with 0.01
µ
FPin numbers in squares
refer to DIP packa
g
e.
R
6
12kΩ
2.5V
R
7
2.2kΩ
0.001µF
C
3
f
IN
V
OUT
+1V
0V
(t)
T
F
FS
= 100kHz
Sensor
INA101
+
–
VFC320
V
IN
f
OUT
Clock
Counter
Computer
Parallel
Data
High Noise
Immunity
Instrumentation
Amp
VFC320
VIN fOUT
Clock
BDC
Counter
Driver/Display
e1
e2
Differential
Input
VFC320 9
SBVS017A
FIGURE 12. Remote Transducer Readout via Fiber Optic Link (Analog and Digital Output).
FIGURE 13. Bipolar input is accomplished by offsetting the
input to the VFC with a reference voltage.
Accurately matched resistors in the REF101
provide a stable half-scale output frequency at
zero volts input.
FIGURE 14. Absolute value circuit with the VFC320. Op
amp, D1 and Q1 (its base-emitter junction
functioning as a diode) provide full-wave
rectification of bipolar input voltages. VFC
output frequency is proportional to | e1 |. The
sign bit output provides indication of the input
polarity.
3510B VFC320
0.01µF
C1
3270pF
C2
R3
40.2kΩ
R2
100kΩ
R1
11kΩ
4.7kΩ4.7kΩ
+VCC
VIN
8.66kΩ
R4
D1
IN4154
2N2222
Sign Bit
Out
e1
Bipolar
Input Q1
fOUT
–
+
Integrator
Current
20kΩ20kΩ
REF101 VFC320
10
13
7
5
7+15V
8
1
+10V to –10V
Input
4
10V
30kΩ
12
0.01µF
+15V
3
3300pF
11
14
–15V
0 to
10kHz
Output
1
Gain Adjust
6
5
2kΩ
VFC320
V/F
V
IN
f
OUT
Clock
BCD
Counter
Driver
INA101
Transducer
Precision DC
levels down to
10mV full scale
FOT FOR
Display
VFC320
F/V V
OUT
f
IN
Analog
Output
Digital
Output
0.005% Linearity
Instrumentation
Amp
VFC320
10 SBVS017A
PACKAGE DRAWING
MPDI002B – JANUARY 1995 – REVISED FEBRUARY 2000
N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE
0.325 (8,26)
0.300 (7,62)
0.010 (0,25) NOM
Gauge Plane
0.015 (0,38)
0.430 (10,92) MAX
20
0.975
(24,77)
0.940
(23,88)
18
0.920
0.850
14
0.775
0.745
(19,69)
(18,92)
16
0.775
(19,69)
(18,92)
0.745
A MIN
DIM
A MAX
PINS **
(23,37)
(21,59)
Seating Plane
14/18 PIN ONLY
4040049/D 02/00
9
8
0.070 (1,78) MAX
A
0.035 (0,89) MAX 0.020 (0,51) MIN
16
1
0.015 (0,38)
0.021 (0,53)
0.200 (5,08) MAX
0.125 (3,18) MIN
0.240 (6,10)
0.260 (6,60)
M
0.010 (0,25)
0.100 (2,54)
16 PINS SHOWN
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (20-pin package is shorter than MS-001).
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