Freescale Semiconductor, Inc.
Datasheet: Technical Data
© 2015 Freescale Semiconductor, Inc. All rights reserved.
Rev.17 of the 56F803 Datasheet has two parts:
• The addendum to revision 16 of the datasheet, immediately following this cover page.
• Revision 16 of the datasheet, following the addendum. The changes described in the addendum have
not been implemented in the specified pages.
56F803 Datasheet with Addendum
Document Number: DSP56F803
Rev. 17, 10/2015
Freescale Semiconductor, Inc.
Datasheet Addendum
© 2015 Freescale Semiconductor, Inc. All rights reserved.
This addendum identifies changes to Rev.16 of the 56F803 datasheet. The changes described in this
addendum have not been implemented in the specified pages.
1 Update the incomplete Thermal Design
Considerations section
Thermal Considerations section in 56F803 datasheet Rev.16 is incomplete. The complete Thermal
Design Consideration section should be as follows:
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
TJ = TA + (PD x R
JA)Eqn. 1
where:
TA = ambient temperature °C
RJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance
and a case-to-ambient thermal resistance:
R
JA = R
JC + R
CA Eqn. 2
Location: Section 5.1, Page 51
Document Number: DSP56F803AD
Rev. 0, 10/2015
Addendum to Rev. 16 of the 56F803
datasheet
Addendum to Rev.16 of 56F803 Technical Data, Rev. 0, 10/2015
Freescale Semiconductor, Inc. 3
Update the incomplete Thermal Design Considerations section
where
RJA = package junction-to-ambient thermal resistance °C/W
RJC = package junction-to-case thermal resistance °C/W
RCA = package case-to-ambient thermal resistance °C/W
RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance,RCA . For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
Definitions
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case)
closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.
• Measure the thermal resistance f rom the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.
• Use the value obtained by the equation (TJ – TT)/PD where TT is the temperature of the package
case determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at
theinterface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
Addendum to Rev.16 of 56F803 Technical Data, Rev. 0, 10/2015
4Freescale Semiconductor, Inc.
Add missing Electrical Design Considerations section
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
2 Add missing Electrical Design Considerations section
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Use the following list of considerations to assure correct DSP operation:
• Provide a low-impedance path from the board power supply to each VDD pin on the DSP, and from
the board ground to each VSS (GND) pin.
• The minimum bypass requirement is to place six 0.01–0.1 mF capacitors positioned as close as
possible to the package supply pins. The recommended bypass configuration is to place one bypass
capacitor on each of the seven VDD/VSS pairs, including VDDA/VSSA. The VCAP capacitors
must be 150 milliohm or less ESR capacitors.
• Ensure that capacitor leads and associated printe d circuit traces that connect to the chip VDD and
VSS (GND) pins are less than 0.5 inch per capacitor lead.
• Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VDD and VSS .
• Bypass the VDD and VSS layers of the PCB with approximately 100 mF, preferably with a
highgrade capacitor such as a tantalum capacitor.
• Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal
3 Add missing Ordering part section
Table 1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales
office or authorized distributor to determine availability and to order parts.
Location: Section 5.2, Page 52
Location: Section 6, Page 53
Table 1. 56F803 Ordering Information
Part Supply
Voltage Package Type Pin Count Ambient
Frequency
(MHz) Order Number
56F803 3.0–3.6 V Low Profile Plastic Quad Flat
Pack (LQFP) 100 80 DSP56F803BU80
Addendum to Rev.16 of 56F803 Technical Data, Rev. 0, 10/2015
Freescale Semiconductor, Inc. 5
Add missing Ordering part section
56F803 3.0–3.6 V Low Profile Plastic Quad Flat
Pack (LQFP) 100 80 DSP56F803BU80E1
1This package is RoHS compliant
Table 1. 56F803 Ordering Information
Part Supply
Voltage Package Type Pin Count Ambient
Frequency
(MHz) Order Number
56F800
16-bit Digital Signal Controllers
freescale.com
56F803
Data Sheet
Preliminary Technical Data
DSP56F803
Rev. 16
09/2007
56F803 Technical Data, Rev. 16
Freescale Semiconductor 3
56F803 Block Diagram
JTAG/
OnCE
Port
Digital Reg Analog Reg
Low Voltage
Supervisor
Program Contro ller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP RESET
RESETIRQA IRQB
Applica-
tion-Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
4096 x 16 Flash
2048 x 16 SRA M
COP/
Watchdog
SPI
or
GPIO
SCI
or
GPIO
Quad Timer D
A/D1
A/D2 ADC
4
2
2
4
4
3
6PWM Outputs
Fault Inputs
PWMA
16 16
VCAPC VDD VSS VDDA VSSA
626 6*
••
•
•
•••
•
EXTBOOT
Current Sense Inputs
3
Quadrature
Decoder 0 /
Quad Timer A
CAN 2.0A/B
2
CLKO
External
Address Bus
Switch
Bus
Control
External
Data Bus
Switch
External
Bus
Interface
Unit
RD Enable
WR Enable
DS Select
PS Select
10
16
6A[00:05]
D[00:15]
A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7
4
Quad Timer C
VREF
Quad Timer B
*includes TCS pin which is reserved for factory use and is tied to VSS
56F803 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP and
controller functions: MAC, bit manipulation unit, 14
addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
•512 × 16-bit word s (1KB) Program RAM
•4K × 16-bit words (8KB) Dat a Flash
•2K × 16-bit words (4KB) Dat a RAM
•2K × 16-bit words (4KB ) Boot Flash
• Up to 64K × 16-bit words each of external Program
and Data memory
• 6-channel PWM module
• Two 4-channel 12-bit ADCs
• Quadrature Decoder
• CAN 2.0 B module
• Serial Communication Interface (SCI)
• Serial Peripheral Interface (SPI)
• Up to two General Purpose Quad Timers
• JTAG/OnCETM port for debugging
• 16 shared GPIO lines
• 100–pin LQFP package
56F803 Technical Data, Rev. 16
4 Freescale Semiconductor
Part 1 Overview
1.1 56F803 Features
1.1.1 Processing Core
• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
•Two 36
-bit accumulators, including extension bits
•16
-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing mo des
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller style addressing modes and instructions for compact code
• Efficient C compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE debug programming interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
—31.5K × 16-bit words of Program Flash
—512K × 16-bit words of Program RAM
—4K × 16-bit words of Data Flash
—2K × 16-bit words of Data RAM
—2K × 16-bit words of Boot Flash
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16 bits of Data memory
— As much as 64K × 16 bits of Program memory
1.1.3 Peripheral Circuits for 56F803
• Pulse W idth Modulator module (PWM) with six PWM outputs, three Current Sense inputs, and three Fault
inputs, fault-tolerant design with dead time insertion, supports both center- and edge- aligned modes,
supports Freescale’s patented dead time distortion correction
•Two 12
-bit Analog-to-Digital Converters (ADCs), which support two simultaneo us conversions; ADC and
PWM modules can be synchronized
• Quadrature Decoder with four inputs (shares pins with Quad Timer)
56F803 Description
56F803 Technical Data, Rev. 16
Freescale Semiconductor 5
• Four General Purpose Quad Timers: T imer A (sharing pins with Quad Dec0), Timers B &C without external
pins and Timer D with two pins
• CAN 2.0 B module with 2-pin ports for transmit and receive
• Serial Communication Interface (SCI) with two pins (or two additional GPIO lines)
• Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)
• Computer Operating Properly (COP) Watchdog timer
• Two dedicated external interrupt pins
• Sixteen multiplexed General Purpose I/O (GPIO) pins
• External reset input pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
1.1.4 Energy Information
• Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
• Uses a single 3.3V power supply
• On-chip regulators for digital and analog circuitry to lower cost and reduce noise
• Wait and Stop modes available
1.2 56F803 Description
The 56F803 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F803 is well-suited for many applications. The 56F803 includes many peripherals
that are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, and industrial control for power, lighting, and automation.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact device and control code.
The instruction set is also highly efficient for C compilers to enable rapid development of optimized
control applications.
The 56F803 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F803 also provides two external
dedicated interrupt lines, and up to 16 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F803 controller includes 31.5K words (16-bit) of Program Flash and 4K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM and 2K words of Data RAM. It
also supports program execution from external memory.
A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
56F803 Technical Data, Rev. 16
6 Freescale Semiconductor
software routines that can be used to program the main Program and Data Flash memory areas. Both
Program and Data Flash memories can be independently bulk–erased or erased in page sizes of 256 words.
The Boot Flash memory can also be either bulk- or page-erased.
A key application-specific feature of the 56F803 is the inclusion of a Pulse Width Modulator (PWM)
module. This module incorporates three complementary, individually programmable PWM signal outputs
(the module is also capable of supporting three independent PWM functions, for a total of six PWM
outputs) to enhance motor control functionality. Complementary operation permits programmable dead
time insertion, distortion correction via current sensing by software, and separate top and bottom output
polarity control. The up-counter value is programmable to support a continuously variable PWM
frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is
supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both
BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance
Motors), and stepper motors. The PWM incorporates fault protection and cycle-by-cycle current limiting
with sufficient output drive capability to directly drive standard opto-isolators. A “smoke-inhibit”,
write-once protection feature for key parameters and patented PWM waveform distortion correction
circuit are also provided. The PWM is double-buffered and includes interrupt controls to permit integral
reload rates to be programmable from 1 to 16. The PWM module provides a reference output to
synchronize the ADC.
The 56F803 incorporates a separate Quadrature Decoder capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast and slow moving shafts. The integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.
This controller also provides a full set of standard programmable peripherals that include a Serial
Communications Interface (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of
these interfaces can be used as General Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant) and an internal interrupt controller
are also included on the 56F803.
1.3 State of the Art Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
Product Documentation
56F803 Technical Data, Rev. 16
Freescale Semiconductor 7
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F803. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at: www.freescale.com
Table 1-1 56F803 Chip Documentation
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
Topic Description Order Number
56800E
Family Manual Detailed description of the 56800 family architecture, and
16-bit core processor and the instruction set 56800EFM
DSP56F801/803/805/807
User’s Manual Detailed description of memory, peripherals, and interfaces
of the 56F801, 56F803, 56F803, and 56F807 DSP56F801-7UM
56F803
Technical Data Sheet Electrical and timing specifications, pin descriptions, and
package descriptions (this document) DSP56F803
56F803
Errata Details any chip issues that might be present DSP56F803E
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
56F803 Technical Data, Rev. 16
8 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F803 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. In Table 2-2 through Table 2-17, each table row describes the signal or
signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group Number of
Pins Detailed
Description
Power (VDD or VDDA)7Table 2-2
Ground (VSS or VSSA)7Table 2-3
Supply Capacitors 2 Table 2-4
PLL and Clock 3 Table 2-5
Address Bus116 Table 2-6
Data Bus 16 Table 2-7
Bus Control 4 Table 2-8
Interrupt and Program Control 4 Table 2-9
Pulse Width Modulator (PWM) Port 12 Table 2-10
Serial Peripheral Interface (SPI) Port1
1. Alternately, GPIO pins
4Table 2-11
Quadrature Decoder Port2
2. Alternately, Quad Timer pins
4Table 2-12
Serial Communications Interface (SCI) Port12Table 2-13
CAN Port 2 Table 2-14
Analog to Digital Converter (ADC) Port 9 Table 2-15
Quad Timer Module Port 2 Table 2-16
JTAG/On-Chip Emulation (OnCE) 6 Table 2-17
Introduction
56F803 Technical Data, Rev. 16
Freescale Semiconductor 9
Figure 2-1 56F803 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parenthesis.
56F803
Power Port
Ground Port
Power Port
Ground Port
PLL
and
Clock
External
Address Bus or
GPIO
External
Data Bus
External
Bus Control
SCI0 Port
or GPIO
VDD
VSS
VDDA
VSSA
VCAPC
EXTAL
XTAL
CLKO
A0-A5
A6-7 (GPIOE2-E3)
A8-15 (GPIOA0-A7)
D0–D15
PS
DS
RD
WR
PHASEA0 (TA0)
PHASEB0 (TA1)
INDEX0 (TA2)
HOME0 (TA3)
TCK
TMS
TDI
TDO
TRST
DE
Quadrature
Decoder or
Quad Timer A
JTAG/OnCE™
Port
PWMA0-5
ISA0-2
FAULTA0-2
SCLK (GPIOE4)
MOSI (GPIOE5)
MISO (GPIOE6)
SS (GPIOE7)
TXD0 (GPIOE0)
RXD0 (GPIOE1)
ANA0-7
VREF
MSCAN_RX
MSCAN_TX
TD1-2
IRQA
IRQB
RESET
EXTBOOT
Quad
Timer D
ADCA
Port
Other
Supply
Ports
6
6*
1
1
2
1
1
1
6
2
8
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Interrupt/
Program
Control
6
3
3
1
1
1
1
1
1
8
1
1
1
2
1
1
1
1
PWMA
Port
SPI Port
or GPIO
CAN
*includes TCS pin which is reserved for fact ory use and is tied to VSS
56F803 Technical Data, Rev. 16
10 Freescale Semiconductor
2.2 Power and Ground Signals
Table 2-2 Power Inputs
No. of Pins Signal Name Signal Description
6VDD Power—These pins provide power to the internal structures of the chip, and sh ould all
be attached to VDD.
1VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the chip and
should be connected to a low noise 3.3V supply.
Table 2-3 Grounds
No. of Pins Signal Name Signal Description
5VSS GND—These pins provide grounding for the internal structures of the chip, and should all
be attached to VSS.
1VSSA Analog Ground—This pin supplies an analog ground.
1TCS TCS—This Schmitt pin is reserved for factory use and must be tied to VSS for normal use.
In block diagrams, this pin is considered an additional VSS.
Table 2-4 Supply Capacitors
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
2VCAPC Supply Supply VCAPC—Connect each pin to a 2.2 μF or greater bypass capacitor in
order to bypass the core logic voltage regulator (required for proper chip
operation). For more information, please refer to Section 5.2.
Clock and Phase Locked Loop Signals
56F803 Technical Data, Rev. 16
Freescale Semiconductor 11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1EXTAL Input Input External Cr ystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
1XTAL Input/
Output Chip-driven Crystal Oscillator Output—T his output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
This pin can also be connected to an external clock source . For more
information, please refer to Section 3.5.3.
1CLKO Output Chip-driven Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select Register
(CLKOSR), the user can select between outputting a version of the
signal applied to XTAL and a version of the device’s master clock at the
output of the PLL. The clock frequency on this pin can also be disabled
by programming the CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
6A0–A5 Output Tri-stated Address Bus—A0–A5 specify the address for external Program or Data
memory accesses.
2A6–A7
GPIOE2–
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus—A6–A7 specify the address for external Program or Data
memory accesses.
Port E GPIO—These two pins are General Purpose I/O (GPIO) pins that
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8A8–A15
GPIOA0–
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight pins are General Purpose I/O (GPIO) pins
that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
56F803 Technical Data, Rev. 16
12 Freescale Semiconductor
2.5 Interrupt and Program Control Signals
Table 2-7 Data Bus Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
16 D0–D15 Input/O
utput Tri-stated Data Bus— D0–D15 specify the data for external Program or Data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pull-ups may be active.
Table 2-8 Bus Control Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1PS Output Tri-stated Program Memory Select—PS is asserted low for external Program memory
access.
1DS Output Tri-stated Data Memory Select—DS is asserted low for external Data memory access.
1WR Output Tri-stated Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data
on the bus. When WR is deasserted high, the external data is latched inside
the external device. When WR is asserted, it qualifies the A0–A15, PS, and
DS pins. WR can be connected directly to the WE pin of a Static RAM.
1RD Output Tri-stated Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the controller. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
Table 2-9 Interrupt and Program Control Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1IRQA Input
(Schmitt) Input External Interrupt Request A—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge- triggered.
1IRQB Input
(Schmitt) Input External Interrupt Request B—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
Pulse Width Modulator (PWM) Signals
56F803 Technical Data, Rev. 16
Freescale Semiconductor 13
2.6 Pulse Width Modulator (PWM) Signals
1RESET Input
(Schmitt) Input Reset—This input is a direct hardware reset on the processor.
When RESET is asserted low, the controller is initialized and placed
in the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip ope rating mode
is latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure a complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1EXTBOOT Input
(Schmitt) Input External Boot—This input is tied to VDD to force device to boot from
off-chip memory. Otherwise, it is tied to VSS.
Table 2-10 Pulse Width Modulator (PWMA) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
6PWMA0–5Output Tri-stated PWMA0–5— These are six PWMA output pins.
3ISA0–2Input
(Schmitt) Input ISA0–2— These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
3FAULTA0–2Input
(Schmitt) Input FAULTA0–2— These three fault input pins are used for disabling
selected PWMA outputs in cases where fault condi ti o ns originate
off-chip.
Table 2-9 Interrupt and Program Control Signals (Continued)
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
56F803 Technical Data, Rev. 16
14 Freescale Semiconductor
2.7 Serial Peripheral Interface (SPI) Signals
Table 2-11 Serial Peripheral Interface (SPI) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1MISO
GPIOE6
Input/Out
put
Input/Out
put
Input
Input
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a
master device and an output from a slave devi c e. The MISO line of a
slave device is placed in the high impedance state if the slave device
is not selected.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is MISO.
1MOSI
GPIOE5
Input/Out
put
Input/Out
put
Input
Input
SPI Master Out/Slave In (MOSI)—This serial data pin is an output
from a master device and an input to a slave device. The master
device places data on the MOSI line a half-cycle before the clock
edge that the slave device uses to latch the data.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is MOSI.
1SCLK
GPIOE4
Input/Out
put
Input/Out
put
Input
Input
SPI Serial Clock—In master mode, this pin serves as an output,
clocking slaved listeners. In slave mode, this pin serves as the data
clock input.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SCLK.
1SS
GPIOE7
Input
Input/Out
put
Input
Input
SPI Slave Select—In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the slave.
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SS.
Quadrature Decoder Signals
56F803 Technical Data, Rev. 16
Freescale Semiconductor 15
2.8 Quadrature Decoder Signals
2.9 Serial Communications Interface (SCI) Signals
Table 2-12 Quadrature Decoder (Quad Dec0) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1PHASEA0
TA0
Input
Input/Output
Input
Input
Phase A—Quadrature Decoder #0 PHASEA input
TA0—Timer A Channel 0
1PHASEB0
TA1
Input
Input/Output
Input
Input
Phase B—Quadrature Decoder #0 PHASEB input
TA1—Timer A Channel 1
1INDEX0
TA2
Input
Input/Output
Input
Input
Index—Quadrature Decoder #0 INDEX input
TA2—Timer A Channel 2
1HOME0
TA3
Input
Input/Output
Input
Input
Home—Quadrature Decoder #0 HOME input
TA3—Timer A Channel 3
Table 2-13 Serial Communications Interface (SCI0) Signals
No. of
Pins Signal
Name Signal Type State During
Reset Signal Description
1TXD0
GPIOE0
Output
Input/Output
Input
Input
Transmit Data (TXD0)—SCI0 transmit data output
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SCI output.
1RXD0
GPIOE1
Input
Input/Output
Input
Input
Receive Data (RXD0)— SCI0 receive data input
Port E GPIO—This General Purpose I/O (GPIO) pin can be
individually programmed as an input or output pin.
After reset, the default state is SCI input.
56F803 Technical Data, Rev. 16
16 Freescale Semiconductor
2.10 CAN Signals
2.11 Analog-to-Digital Converter (ADC) Signals
2.12 Quad Timer Module Signals
Table 2-14 CAN Module Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1MSCAN_ RX Input
(Schmitt) Input MSCAN Receive Data—This is the MSCAN input. This pin has an
internal pull - up resi st or.
1MSCAN_ TX Output Output MSCAN Transmit Data—MSCAN output. CAN output is
open-drain output and a pul l-up resistor is needed.
Table 2-15 Analog to Digital Converter Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
4ANA0–3Input Input ANA0–3—Analog inputs to ADC channel 1
4ANA4–7Input Input ANA4–7—Analog inputs to ADC channel 2
1VREF Input Input VREF—Analog reference voltage for ADC. Must be set to VDDA-0.3V
for optimal performance.
Table 2-16 Quad Timer Module Signals
No. of Pins Signal Name Signal Type State During Reset Signal Description
2TD1–2Input/Output Input TD1–2— Timer D Channel 1–2
JTAG/OnCE
56F803 Technical Data, Rev. 16
Freescale Semiconductor 17
2.13 JTAG/OnCE
Part 3 Specifications
3.1 General Characteristics
The 56F803 is fabricated in high-density CMOS with 5-V tolerant TTL-compatible digital inputs. The
term “5-V tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology,
to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Table 2-17 JTAG/On-Chip Emulation (OnCE) Signals
No. of
Pins Signal
Name Signal
Type State During
Reset Signal Description
1TCK Input
(Schmitt) Input, pulled low
internally Test Clock Inpu t—This input pin provides a gated clock to synchronize the
test logic and shift serial data to the JTAG/OnCE port. The pin is connected
internally to a pull-down resistor.
1TMS Input
(Schmitt) Input, pulled
high internally Test Mode Select Input—This input pin is used to sequence th e JTAG
TAP controller’s state machine. It is sampled on the rising edge of TCK and
has an on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
1TDI Input
(Schmitt) Input, pulled
high internally Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
1TDO Output Tri-stated Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
1TRST Input
(Schmitt) Input, pulled
high internally Test Reset—As an input, a low signal on this pin provides a reset signal to
the JTAG TAP controller. To ensure complete hardware reset, TRST
should be asserted at power-up and whenever RESET is asserted. The
only exception occurs in a debugging environment when a hardware device
reset is required and it is necessary not to reset the OnCE/JTAG module. In
this case, assert RESET, but do not assert TRST.
Note: For normal operation, connect TRST directly to VSS. If the design is to b e
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
1DE Output Output Debug Event—DE provides a low pulse on recognized debug events.
56F803 Technical Data, Rev. 16
18 Freescale Semiconductor
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F803 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against damage due
to high static voltage or electrical fields. However, normal precautions
are advised to avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability of operation is
enhanced if unused inputs are tied to an appropriate voltage level.
Table 3-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage VDD VSS – 0.3 VSS + 4.0 V
All other input voltages, excluding Analog inputs VIN VSS – 0.3 VSS + 5.5V V
Voltage difference VDD to VDDA ΔVDD - 0.3 0.3 V
Voltage difference VSS to VSSA ΔVSS - 0.3 0.3 V
Analog inputs ANA0-7 and VREF VIN VSSA– 0.3 VDDA+ 0.3 V
Analog inputs EXTAL and XTAL VIN VSSA– 0.3 VSSA+ 3.0 V
Current drain per pin excluding VDD, VSS, PWM outputs, TCS,
VPP, VDDA, VSSA
I—10mA
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
Supply voltage, digital VDD 3.0 3.3 3.6 V
Supply Voltage, analog VDDA 3.0 3.3 3.6 V
Voltage difference VDD to VDDA ΔVDD -0.1 - 0.1 V
General Characteristics
56F803 Technical Data, Rev. 16
Freescale Semiconductor 19
Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2 p thermal test boar d.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p where “s” is the number of signal layers and “p” is the
number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with
the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC ), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate ther mal performance when the package is being used with a heat sink.
Voltage difference VSS to VSSA ΔVSS -0.1 - 0.1 V
ADC reference voltage VREF 2.7 – VDDA V
Ambient operating temperature TA–40 – 85 °C
Table 3-3 Thermal Characteristics6
Characteristic Comments Symbol Value Unit Notes
100-pin LQFP
Junction to ambient
Natural convection RθJA 41.7 °C/W 2
Junction to ambient (@1m/sec) RθJMA 37.2 °C/W 2
Junction to ambient
Natural convection Four layer board (2s2p) RθJMA
(2s2p) 34.2 °C/W 1,2
Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 32 °C/W 1,2
Junction to case RθJC 10.2 °C/W 3
Junction to center of case ΨJT 0.8 °C/W 4, 5
I/O pin power dissipation P I/O User Determined W
Power dissipation P D P D = (IDD x VDD + P I/O)W
Junction to center of case PDMAX (TJ - TA) /RθJA W7
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
56F803 Technical Data, Rev. 16
20 Freescale Semiconductor
4. Thermal Characterization Parameter, Psi-JT (ΨJT ), is the “resistance” from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady state customer environments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
6. See Section 5.1 from more details on thermal design considerations.
7. TJ = Junction Tem perature
TA = Ambient Temperature
3.2 DC Electrical Characteristic
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
Input high voltage (XTAL/EXTAL) VIHC 2.25 — 2.75 V
Input low voltage (XTAL/EXTAL) VILC 0—0.5V
Input high voltage (Schmitt trigger inputs)1VIHS 2.2 — 5.5 V
Input low voltage (Schmitt trigge r inputs)1VILS -0.3 — 0.8 V
Input high voltage (all other digita l inputs) VIH 2.0 — 5.5 V
Input low voltage (all other digital inputs) VIL -0.3 — 0.8 V
Input current high (pull up/pulldown resistors
disabled, VIN=VDD)IIH -1 — 1 μA
Input current low (pullup/pulldown resistors
disabled, VIN=VSS)IIL -1 — 1 μA
Input current high (with pullup resistor, VIN=VDD)I
IHPU -1 — 1 μA
Input current low (with pullup resistor, V IN=VSS)I
ILPU -210 — -50 μA
Input current high (with pulldown resistor, VIN=VDD)I
IHPD 20 — 180 μA
Input current low (with pulldown resistor, VIN=VSS)I
ILPD -1 — 1 μA
Nominal pullup or pulldown resistor value RPU, RPD 30 KΩ
Output tri-state current low IOZL -10 — 10 μA
Output tri-state current high IOZH -10 — 10 μA
DC Electrical Characteristic
56F803 Technical Data, Rev. 16
Freescale Semiconductor 21
Input current high (analog inputs, VIN=VDDA)2IIHA -15 — 15 μA
Input current lo w (a na l o g in p uts, VIN=VSSA)2IILA -15 — 15 μA
Output High Voltage (at IOH) VOH VDD – 0.7 — — V
Output Low Voltage (at IOL) VOL ——0.4 V
Output source current IOH 4——mA
Output sink current IOL 4——mA
PWM pin output source current3IOHP 10 — — mA
PWM pin output sink current4IOLP 16 — — mA
Input capacitance CIN —8—pF
Output capacitance COUT —12— pF
VDD supply current IDDT5
Run 6— 126 152 mA
Wait7— 105 129 mA
Stop — 60 84 mA
Low Voltage Interrupt, external power supply8VEIO 2.4 2.7 3.0 V
Low Voltage Interrupt, internal power supply9VEIC 2.0 2.2 2.4 V
Power on Reset10 VPOR —1.72.0 V
1.
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, ISA0-2, FAULTA0-3, TCS, TCK, TRST, TMS, TDI, and
MSCAN_RX
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% du ty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured
as inputs; measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (f osc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC
loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects
wait IDD; measured with PLL enabled.
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
56F803 Technical Data, Rev. 16
22 Freescale Semiconductor
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown.
8. This low-voltage interr upt monitors the VDDA external power supply. VDDA is generally connected to the same potential
as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed
under transient conditions wh en VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is
generated).
9. This low voltage interrupt monitors the internally regulated core power sup ply. If the output from the internal voltage is
regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not
be generated unless the external power supply drops below the minimum specified value (3.0V).
10. Power–on reset occurs when ever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is
ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate
is. The internally regulated vo ltage is typically 100mV less than VDD during ra mp-up, until 2.5V is reached, at which time it
self-regulates.
0
30
90
120
180
60
20 40 60 80
Freq. (MHz)
IDD (mA)
150
IDD Digital IDD Analog IDD Total
Flash Memory Characteristics
56F803 Technical Data, Rev. 16
Freescale Semiconductor 23
Figure 3-2 Input Signal Measurement References
Figure 3-3 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
Figure 3-3 Signal States
3.4 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
Mode XE1
1. X address enable, all rows are disabled when XE = 0
YE2
2. Y address enable, YMUX is disabled when YE = 0
SE3
3. Sense amplifier enable
OE4
4. Output enable, tri-state Flash data out bus when OE = 0
PROG5ERASE6MAS17NVSTR8
Standby L L L L L L L L
Read HHHH L L L L
Word ProgramHHLLH LLH
Page Erase H L L L L H L H
Mass Erase H L L L L H H H
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low High 90%
50%
10%
Rise Time
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
56F803 Technical Data, Rev. 16
24 Freescale Semiconductor
5. Defines program cycle
6. Defines erase cycle
7. Defines mass erase cycle, erase whole block
8. Defines non-volatile store cycle
Table 3-6 IFREN Truth Table
Mode IFREN = 1 IFREN = 0
Read Read information block Read main memory block
Word program Program information block Program main memory block
Page erase Erase information block Erase main memory block
Mass erase Erase both block Erase main memory block
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit Figure
Progra m time Tprog* 20 – – us Figure 3-4
Erase time Terase* 20 – – ms Figure 3-5
Mass erase time Tme* 100 – – ms Figure 3-6
Endurance1 ECYC 10,000 20,000 – cycles
Data Retention1DRET 10 30 – years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set up time Tnv* –5–usFigure 3-4,
Figure 3-5,
Figure 3-6
NVSTR hold time Tnvh* –5–usFigure 3-4,
Figure 3-5
NVSTR hold time (mass erase) Tnvh1* – 100 – us Figure 3-6
NVSTR to program set up time Tpgs* –10–usFigure 3-4
Recovery time Trcv* –1–usFigure 3-4,
Figure 3-5,
Figure 3-6
Flash Memory Characteristics
56F803 Technical Data, Rev. 16
Freescale Semiconductor 25
Figure 3-4 Flash Program Cycle
Cumulative program
HV period2Thv –3–ms Figure 3-4
Program hold time3Tpgh ––– Figure 3-4
Address/data set up time3Tads ––– Figure 3-4
Address/data hol d ti me3Tadh ––– Figure 3-4
1. One cycle is equal to an erase program and read.
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed
twice before next erase.
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
Table 3-7 Flash Timing Parameters (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit Figure
XADR
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tpgs
Tadh
Tprog
Tads
Tpgh
Tnvh Trcv
Thv
IFREN
XE
56F803 Technical Data, Rev. 16
26 Freescale Semiconductor
Figure 3-5 Flash Erase Cycle
Figure 3-6 Flash Mass Erase Cycle
XADR
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh Trcv
Terase
IFREN
XE
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1 Trcv
Tme
MAS1
IFREN
XE
External Clock Operation
56F803 Technical Data, Rev. 16
Freescale Semiconductor 27
3.5 External Clock Operation
The 56F803 system clock can be derived from an external crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected between
the EXTAL and XTAL pins.
3.5.1 Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-9. In Figure 3-7 a recommended crystal
oscillator circuit is shown. Follow the crystal supplier’s recommendations when selecting a crystal,
because crystal parameters determine the component values required to provide maximum stability and
reliable start-up. The crystal and associated components should be mounted as close as possible to the
EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal
56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in
Figure 3-8 no external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
Figure 3-7 Connecting to a Crystal Oscillator
CL = CL1 * CL2
CL1 + CL2 + Cs = + 3 = 6 + 3 = 9pF
12 * 12
12 + 12
Recommended External Crystal
Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
fc
56F803 Technical Data, Rev. 16
28 Freescale Semiconductor
3.5.2 Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is
shown. Refer to supplier’s recommendations when selecting a ceramic resonator and associated
components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-7 no external load capacitors should be used.
Figure 3-8 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
3.5.3 External Clock Source
The recommended method of connecting an external clock is given in Figure 3-9. The external clock
source is connected to XTAL and the EXTAL pin is grounded.
Figure 3-9 Connecting an External Clock Signal
Recommended Ceramic Resonator
Parameters:
Rz = 1 to 3 MΩ
fc = 8MHz (optimized for 8MHz)
EXTAL XTAL
Rz
fc
56F803
XTAL EXTAL
External VSS
Clock
External Clock Operation
56F803 Technical Data, Rev. 16
Freescale Semiconductor 29
Figure 3-10 External Clock Timing
Table 3-8 External Clock Operation Timing Requirements3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)1
1. See Figure 3-9 for details on using the recommended connection of an external clock driver.
fosc 0—80MHz
Clock Pulse Width2, 3
2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. However, the high pulse width
does not have to be any particular percent of the low pulse width.
3. Parameters listed are guaranteed by design.
tPW 6.25 — — ns
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10% tPW tPW
56F803 Technical Data, Rev. 16
30 Freescale Semiconductor
3.5.4 Phase Locked Loop Timing
3.6 External Bus Asynchronous Timing
Table 3-9 PLL Timing
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 8MHz input crystal.
2. ZCLK may not exceed 80MHz. For additional information o n ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
fosc 4810MHz
PLL output frequency 2fout/2 40 — 110 MHz
PLL stabilization time 3 0o to +85oCtplls —110ms
PLL stabilization time3 -40o to 0oCtplls — 100 200 ms
Table 3-10 External Bus Asynchronous Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Max Unit
Address Valid to WR Asserted tAWR 6.5 — ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR 7.5
(T*WS) + 7.5 —
—ns
ns
WR Asserted to D0–D15 Out Valid tWRD —4.2ns
Data Out Hold Time from WR Deasserted tDOH 4.8 — ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS 2.2
(T*WS) + 6.4 —
—ns
ns
RD Deasserted to Address Not Valid tRDA 0—ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD 18.7
(T*WS) + 18.7
—ns
ns
External Bus Asynchronous Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 31
Input Data Hold to RD Deasserted tDRD 0—ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD 19
(T*WS) + 19 —
—ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD —
—1
(T*WS) + 1 ns
ns
Address Valid to RD Asserted tARDA -4.4 — ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD —
—2.4
(T*WS) + 2.4 ns
ns
WR Deasserted to RD Asserted tWRRD 6.8 — ns
RD Deasserted to RD Asserted tRDRD 0—ns
WR Deasserted to WR Asserted tWRWR 14.1 — ns
RD Deasserted to WR Asserted tRDWR 12.8 — ns
Table 3-10 External Bus Asynchronous Timing1, 2 (Continued)
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Max Unit
56F803 Technical Data, Rev. 16
32 Freescale Semiconductor
Figure 3-11 External Bus Asynchronous Timing
3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing 1, 5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance tRAZ —21nsFigure 3-12
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
tRA 275,000T
128T —
—ns
ns
Figure 3-12
RESET De-assertion to First External Address Output tRDA 33T 34T ns Figure 3-12
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the addres s lines do not change state.
Data In
Data Out
tAWR
tARDA
tARDD tRDA
tRD tRDRD
tRDWR
tWRWR tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 33
Edge-sensitive Interrupt Re quest Width tIRW 1.5T — ns Figure 3-13
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM 15T — ns Figure 3-14
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG 16T — ns Figure 3-14
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3tIRI 13T — ns Figure 3-15
IRQA Width Assertion to Recover from Stop State4tIW 2T — ns Figure 3-16
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
—275,000T
12T ns
ns
Figure 3-16
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
—275,000T
12T ns
ns
Figure 3-17
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
—275,000T
12T ns
ns
Figure 3-17
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recove r from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)1, 5
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Max Unit See Figure
56F803 Technical Data, Rev. 16
34 Freescale Semiconductor
Figure 3-12 Asynchronous Reset Timing
Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive)
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
RESET
First Fetch
tRA
tRAZ tRDA
IRQA,
IRQB tIRW
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 35
Figure 3-14 External Level-Sensitive Interrupt Timing
Figure 3-15 Interrupt from Wait State Timing
Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing
A0–A15,
PS, DS,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
tIDM
tIG
Instruction Fetch
IRQA,
IRQB
First Interrupt Vector
A0–A15,
PS, DS,
RD, WR
tIRI
Not IRQA Interrupt Vector
IRQA
A0–A15,
PS, DS,
RD, WR First Instruction Fetch
tIW
tIF
56F803 Technical Data, Rev. 16
36 Freescale Semiconductor
Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service
3.8 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
tC50
25 —
—ns
ns
Figures 3-18, ,
3-20, 3-21
Enable lead time
Master
Slave
tELD —
25 —
—ns
ns
Figure 3-21
Enable lag time
Master
Slave
tELG —
100 —
—ns
ns
Figure 3-21
Clock (SCLK) high time
Master
Slave
tCH 17.6
12.5 —
—
ns
ns Figures 3-18, ,
3-20, 3-21
Clock (SCLK) low time
Master
Slave
tCL 24.1
25 —
—ns
ns
Figures 3-18, ,
3-20, 3-21
Data set-up time required for inputs
Master
Slave
tDS 20
0—
—ns
ns
Figures 3-18, ,
3-20, 3-21
Data hold time required for inputs
Master
Slave
tDH 0
2—
—ns
ns
Figures 3-18, ,
3-20, 3-21
Access time (time to data active from high-impedance
state)
Slave
tA4.8 15 ns Figure 3-21
Disable time (hold time to high-impedance state)
Slave tD3.7 15.2 ns Figure 3-21
Instruction Fetch
IRQA
A0–A15
PS, DS,
RD, WR First IRQA Interrupt
tIRQ
tII
Serial Peripheral Interface (SPI) Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 37
Figure 3-18 SPI Master Timing (CPHA = 0)
Data Valid for outputs
Master
Slave (after enable edge)
tDV —
—4.5
20.4 ns
ns
Figures 3-18, ,
3-20, 3-21
Data invalid
Master
Slave
tDI 0
0—
—ns
ns
Figures 3-18, ,
3-20, 3-21
Rise time
Master
Slave
tR—
—11.5
10.0 ns
ns
Figures 3-18, ,
3-20, 3-21
Fall time
Master
Slave
tF—
—9.7
9.0 ns
ns
Figures 3-18, ,
3-20, 3-21
1. Parameters listed are guaranteed by design.
Table 3-12 SPI Timing1
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic Symbol Min Max Unit See Figure
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input) SS is held High on master
tR
tF
tF
tDI
tDS
tDI(ref)
tDV
tCH
tDH
tCtRtF
tR
tCL
tCH
tCL
56F803 Technical Data, Rev. 16
38 Freescale Semiconductor
Figure 3-19 SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14– 1 Master LSB out
SS
(Input) SS is held High on master
tC
tCL
tF
tDI
tDV(ref) tDV
tR
tDH
tDS
tR
tCH
tCH
tCL
tF
tR
tF
Serial Peripheral Interface (SPI) Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 39
Figure 3-20 SPI Slave Timing (CPHA = 0)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tELG
tF
tR
tC
tCL
tCH
tCL
tELD
tAtCH tRtFtD
tDI
tDI
tDS
tDH
tDV
56F803 Technical Data, Rev. 16
40 Freescale Semiconductor
Figure 3-21 SPI Slave Timing (CPHA = 1)
3.9 Quad Timer Timing
Table 3-13 Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic Symbol Min Max Unit
Timer input period PIN 4T+6 — ns
Timer input high/low peri od PINHL 2T+3 — ns
Timer output period POUT 2T — ns
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tC
tCL
tDV
tA
tELD
tR
tF
tELG
tCH
tCL
tCH
tF
tDS tDV tDI
tDH
tD
tR
Quadrature Decoder Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 41
Figure 3-22 Timer Timing
3.10 Quadrature Decoder Timing
Timer output high/low period POUTHL 1T — ns
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Table 3-14 Quadrature Decoder Timing1,2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12. ns. VSS = 0 V, VDD = 3.0 – 3.6V,
TA = –40° to +85°C, CL ≤ 50pF.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Quadrature input period PIN 8T+12 — ns
Quadrature input high/low period PHL 4T+6 — ns
Quadrature phase period PPH 2T+3 — ns
Table 3-13 Timer Timing1, 2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Timer Inputs
Timer Outputs
PIN PINHL PINHL
POUT POUTHL POUTHL
56F803 Technical Data, Rev. 16
42 Freescale Semiconductor
Figure 3-23 Quadrature Decoder Timing
3.11 Serial Communication Interface (SCI) Timing
Figure 3-24 RXD Pulse Width
Table 3-15 SCI Timing4
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
Characteristic Symbol Min Max Unit
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
BR — (fMAX*2.5)/(80) Mbps
RXD2 Pulse Width
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXDPW 0.965/BR 1.04/BR ns
TXD3 Pulse Width
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
TXDPW 0.965/BR 1.04/BR ns
Phase B
(Input)
Phase A
(Input)
PIN
PIN PHL PHL
PHL
PHL
PPH
PPH PPH PPH
RXD
SCI receive
data pin
(Input) RXDPW
Analog-to-Digital Converter (ADC) Characteristics
56F803 Technical Data, Rev. 16
Freescale Semiconductor 43
Figure 3-25 TXD Pulse Width
3.12 Analog-to-Digital Converter (ADC) Characteristics
Table 3-16 ADC Characteristics
Characteristic Symbol Min Typ Max Unit
ADC input voltages VADCIN 01—VREF2V
Resolution RES 12 — 12 Bits
Integral Non-Linearity3INL — +/- 2.5 +/- 4 LSB4
Differential Non-Linearity DNL — +/- 0.9 +/- 1 LSB4
Monotonicity GUARANTEED
ADC internal clock5fADIC 0.5 — 5 MHz
Conversion range RAD VSSA —V
DDA V
Power-up time tADPU —16 —
tAIC cycles6
Conversion time tADC —6 —
tAIC cycles6
Sample time tADS —1 —
tAIC cycles6
Input capacitance CADI —5 — pF6
Gain Error (transfer gain)5EGAIN 0.95 1.00 1.10 —
Offset Voltage5VOFFSET -80 -15 +20 mV
Total Harmonic Distortion5THD 60 64 — dB
Signal-to-Noise plus Distortion5SINAD 55 60 — dB
Effective Number of Bits5ENOB 9 10 — bit
Spurious Free Dynamic Range5SFDR 65 70 — dB
Bandwidth BW — 100 — KHz
TXD
SCI receive
data pin
(Input) TXDPW
56F803 Technical Data, Rev. 16
44 Freescale Semiconductor
1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)
3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)
4. Sampling capacitor at the sample and hold circuit. (1pf)
Figure 3-26 Equivalent Analog Input Circuit
3.13 Controller Area Network (CAN) Timing
ADC Quiescent Current (both ADCs) IADC —50 — mA
VREF Quiescent Current (both ADCs) IVREF —1216.5 mA
1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital
output code of 0.
2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VD-
DA-0.3V.
3. Measured in 10-90% range.
4. LSB = Least Significant Bit.
5. Guaranteed by characterization.
6. tAIC = 1/fADIC
Table 3-17 CAN Timing2
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40× to +85×C, CL £ 50pF, MSCAN Clock = 30MHz
Characteristic Symbol Min Max Unit
Baud Rate BRCAN —1Mbps
Bus Wakeup detection 1T WAKEUP 5—μs
Table 3-16 ADC Characteristics
Characteristic Symbol Min Typ Max Unit
12
3
4
ADC analog input
Controller Area Network (CAN) Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 45
Figure 3-27 Bus Wakeup Detection
1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event
(on MSCAN_RX pin) whose duration is less than 5 micro seconds is filtered away. However, a valid CAN bus wakeup detec-
tion takes place for a wakeup pulse equal to or greater than 5 microseconds. The value of 5 microseconds originates from the
fact that the CAN wakeup message consists of 5 dominant bits at the highest possib le baud rate of 1Mbps.
2. Parameters listed are guaranteed by design.
MSCAN_RX
CAN receive
data pin
(Input) T WAKEUP
56F803 Technical Data, Rev. 16
46 Freescale Semiconductor
3.14 JTAG Timing
Figure 3-28 Test Clock Input Timing Diagram
Table 3-18 JTAG Timing1, 3
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6 V, TA = –40° to +85°C, CL ≤ 50pF, fOP = 80MHz
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation2
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
fOP DC 10 MHz
TCK cycle time tCY 100 — ns
TCK clock pulse width tPW 50 — ns
TMS, TDI data set-up time tDS 0.4 — ns
TMS, TDI data hold ti me tDH 1.2 — ns
TCK low to TDO data valid tDV — 26.6 ns
TCK low to TDO tri-state tTS — 23.5 ns
TRST assertion time tTRST 50 — ns
DE assertion time tDE 4T — ns
TCK
(Input) VM
VIL
VM = VIL + (VIH – VIL)/2
VM
VIH
tPW
tCY
tPW
JTAG Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor 47
Figure 3-29 Test Access Port Timing Diagram
Figure 3-30 TRST Timing Diagram
Figure 3-31 OnCE—Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
TMS
tDV
tTS
tDV
tDS tDH
TRST
(Input) tTRST
DE tDE
56F803 Technical Data, Rev. 16
48 Freescale Semiconductor
Part 4 Packaging
4.1 Package and Pin-Out Information 56F803
This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F803.
Figure 4-1 Top View, 56F803 100-pin LQFP Package
PIN 1
PIN 26 PIN 51
PIN 76
D10
D11
D12
D13
D14
D15
A0
VDD
VSS
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
VDD
PS
DS
A14
A15
VSS
WR
RD
IRQA
IRQB
TCS
TCK
TMS
TDI
TDO
TRST
VCAPC
ISA0
ISA1
ISA2
FAULTA0
MSCAN_TX
FAULTA1
MSCAN_RX
FAULTA2
VREF
AN0
AN1
PWMA5
PWMA4
PWMA3
PWMA2
PWMA1
PWMA0
HOME0
INDEX0
VSS
VDD
PHASEB0
PHASEA0
VSS
VDD
VDD
VDDA
VSSA
EXTAL
XTAL
AN7
AN6
AN5
AN4
AN3
AN2
D9
D8
D7
D6
D5
D4
D3
VSS
VDD
D2
D1
D0
VCAPC
SCLK
MOSI
MISO
SS
TD2
TD1
CLKO
DE
RESET
EXTBOOT
RXD0
TXD0
ORIENTATION
MARK
Package and Pin-Out Information 56F803
56F803 Technical Data, Rev. 16
Freescale Semiconductor 49
Table 4-1 56F803 Pin Identification By Pin Number
Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal Name
1 D10 26 A14 51 AN2 76 TXD0
2 D11 27 A15 52 AN3 77 RXD0
3 D12 28 VSS 53 AN4 78 EXTBOOT
4 D13 29 WR 54 AN5 79 RESET
5 D14 30 RD 55 AN6 80 DE
6 D15 31 IRQA 56 AN7 81 CLKO
7A032IRQB
57 XTAL 82 TD1
8V
DD 33 TCS 58 EXTAL 83 TD2
9V
SS 34 TCK 59 VSSA 84 SS
10 A1 35 TMS 60 VDDA 85 MISO
11 A2 36 TDI 61 VDD 86 MOSI
12 A3 37 TDO 62 VDD 87 SCLK
13 A4 38 TRST 63 VSS 88 VCAPC
14 A5 39 VCAPC 64 PHASEA0 89 D0
15 A6 40 ISA0 65 PHASEB0 90 D1
16 A7 41 ISA1 66 VDD 91 D2
17 A8 42 ISA2 67 VSS 92 VDD
18 A9 43 FAULTA0 68 INDEX0 93 VSS
19 A10 44 MSCAN_TX 69 HOME0 94 D3
20 A11 45 FAULTA1 70 PWMA0 95 D4
21 A12 46 MSCAN_RX 71 PWMA1 96 D5
22 A13 47 FAULTA2 72 PWMA2 97 D6
23 VDD 48 VREF 73 PWMA3 98 D7
24 PS 49 AN0 74 PWMA4 99 D8
25 DS 50 AN1 75 PWMA5 100 D9
56F803 Technical Data, Rev. 16
50 Freescale Semiconductor
Figure 4-2 100-pin LQPF Mechanical Information
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DA TUM PLANE -AB- IS LOCATED A T BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4. DA TUMS -T -, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCA TED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
9. EXACT SHAPE OF EACH CORNER MA Y VAR Y
FROM DEPICTION.
AE
AE
AD
SEATING
(24X PER SIDE)
R
GAUGE PLANE
DETAIL AD SECTION AE-AE
S
V
B
A
96X
X
E
C
K
HW
D
F
J
N
9
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A13.950 14.050 0.549 0.553
B13.950 14.050 0.549 0.553
C1.400 1.600 0.055 0.063
D0.170 0.270 0.007 0.011
E1.350 1.450 0.053 0.057
F0.170 0.230 0.007 0.009
G0.500 BSC 0.020 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
Q1 5 1 5
R0.150 0.250 0.006 0.010
S15.950 16.050 0.628 0.632
V15.950 16.050 0.628 0.632
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
°°
°°°°
-T-
S
T-U
S
0.15 (0.006) Z S
AC
S
T-U
S
0.15 (0.006) Z S
AC
S
T-U
S
0.15 (0.006) Z S
AC
-U-
S
T-U
S
0.15 (0.006) Z S
AB
-Z-
-AC-
GPLANE
-AB-
S
T-U
M
0.20 (0.008) Z S
AC
0.100 (0.004) AC
Q°
M°
0.25 (0.010)
Thermal Design Considerations
56F803 Technical Data, Rev. 16
Freescale Semiconductor 51
Please see www.freescale.com for the most current case outline.
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal res istance and
a case-to-ambient thermal resistance:
Equation 2:
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment . For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
TJTAPDRθJA
×()+=
RθJA RθJC RθCA
+=
Document Number: DSP56F803
Rev. 17
10/2015
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