SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
!"
Typical Size
6,6 mm X 9,8 mm
FEATURES
DQualified for Automotive Applications
D30-mΩ, 12-A Peak MOSFET Switches for High
Efficiency at 6-A Continuous Output Source
and Sink
D0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V Fixed
Output Voltage Devices With 1% Initial
Accuracy
DInternally Compensated for Easy Use and
Minimal Component Count
DFast Transient Response
DWide PWM Frequency − Fixed 350 kHz,
550 kHz or Adjustable 280 kHz to 700 kHz
DLoad Protected by Peak Current Limit and
Thermal Shutdown
DIntegrated Solution Reduces Board Area and
Total Cost
APPLICATIONS
DLow-Voltage, High-Density Systems With
Power Distributed at 5 V or 3.3 V
DPoint of Load Regulation for High
Performance DSPs, FPGAs, ASICs and
Microprocessors
DBroadband, Networking and Optical
Communications Infrastructure
DPortable Computing/Notebook PCs
DESCRIPTION
The SWIFT family of dc/dc regulators, the TPS54611,
TPS54612, TPS54613, TPS54614, TPS54615, and
TPS54616 low-input voltage high-output current
synchronous-buck PWM converters integrate all required
active components. Included on the substrate are true,
high-performance, voltage error amplifiers that provide
high performance under transient conditions; an
under-voltage-lockout circuit to prevent start-up until the
input voltage reaches 3 V; an internally and externally set
slow-start circuit to limit in-rush currents; and a power good
output useful for processor/logic reset, fault signaling, and
supply sequencing.
The TPS54611−6 devices are available in a thermally
enhanced 28-pin TSSOP (PWP) PowerPAD package,
which eliminates bulky heatsinks. Texas Instruments
provides evaluation modules and the SWIFT designer
software tool to aid in quickly achieving high-performance
power supply designs to meet aggressive equipment
development cycles.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
#$%&'()*#&$ # +,''-$* ) &% .,/0#+)*#&$ 1)*-2 '&1,+*
+&$%&'( *& .-+#%#+)*#&$ .-' *3- *-'( &% -4) $*',(-$* *)$1)'1 5)'')$*62
'&1,+*#&$ .'&+-#$7 1&- $&* $-+-)'#06 #$+0,1- *-*#$7 &% )00 .)')(-*-'2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
www.ti.com
Copyright 2008 Texas Instruments Incorporated
PowerPAD and SWIFT are trademarks of Texas Instruments.
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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2
VIN PH
BOOT
PGND
VSENSE
Output
AGND
VBIAS
Input
TPS54614
SIMPLIFIED SCHEMATIC
50
55
60
65
70
75
80
85
90
95
100
0123456
Load Current − A
Efficiency − %
EFFICIENCY AT 350 kHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AGND
VSENSE
NC
PWRGD
BOOT
PH
PH
PH
PH
PH
PH
PH
PH
PH
RT
FSEL
SS/ENA
VBIAS
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PWP PACKAGE
(TOP VIEW)
THERMAL
PAD
AVAILABLE OPTIONS{
OUTPUT
PACKAGED DEVICES}
OUTPUT
PACKAGED DEVICES}
TJ
OUTPUT
VOLTAGE PLASTIC HTSSOP
(PWP)§TJ
OUTPUT
VOLTAGE PLASTIC HTSSOP
(PWP)§
0.9 V TPS54611QPWPRQ1 1.8 V TPS54614QPWPRQ1
−40°C to 125°C1.2 V TPS54612QPWPRQ1¶−40°C to 125°C2.5 V TPS54615QPWPRQ1
−40 C to 125 C
1.5 V TPS54613QPWPRQ1
−40 C to 125 C
3.3 V TPS54616QPWPRQ1
†For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site
at http://www.ti.com.
‡Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
§The PWP package is taped and reeled as denoted by the R suffix on the device type (i.e., TPS54616QPWPRQ1).
See application section of data sheet for PowerPAD drawing and layout information.
¶Product Preview
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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3
Terminal Functions
TERMINAL
DESCRIPTION
NAME NO.
DESCRIPTION
AGND 1 Analog ground. Return for slow-start capacitor, VBIAS capacitor , RT resistor FSEL. Make PowerP AD connection to AGND.
BOOT 5 Bootstrap input. A 0.022-µF to 0.1-µF low-ESR capacitor connected from BOOT to PH generates a floating drive for t h e
high-set FET driver.
NC 3 No connection
PGND 15−19 Power ground. High current return for the low-side driver and power MOSFET. Connect PGND with large copper areas to
the input and output supply returns and negative terminals of the input and output capacitors.
PH 6−14 Phase input/output. Junction of the internal high-side and low-side power MOSFETs, and output inductor.
PWRGD 4 Power good open drain output. High-Z when VSENSE ≥ 90% V ref, otherwise PWRGD is low . Note that output is low when
SS/ENA is low or internal shutdown signal active.
RT 28 Frequency setting resistor input. Connect a resistor from RT to AGND to set the switching frequency.
SS/ENA 26 Slow-start/enable input/output. Dual function pin which provides logic input to enable/disable device operation and
capacitor input to externally set the start-up time.
FSEL 27 Frequency select input. Provides logic input to select between two internally set switching frequencies.
VBIAS 25 Internal bias regulator output. Supplies regulated voltage to internal circuitry. Bypass VBIAS pin to AGND pin with a high
quality, low-ESR 0.1-µF to 1-µF ceramic capacitor.
VIN 20−24 Input supply for the power MOSFET switches and internal bias regulator. Bypass VIN pins to PGND pins close to device
package with a high quality, low-ESR 1-µF to 10-µF ceramic capacitor.
VSENSE 2 Error amplifier inverting input. Connect directly to output voltage sense point.
ABSOLUTE MAXIMUM RATINGS
over o p e r ating free-air temperature range unless otherwise noted(1)
VIN, SS/ENA, FSEL −0.3 V to 7 V
VI
Input voltage range
RT −0.3 V to 6 V
V
I
Input voltage range
VSENSE −0.3 V to 4 V
BOOT −0.3 V to 17 V
VO
Output voltage range
VBIAS, PWRGD −0.3 V to 7 V
V
O
Output voltage range
PH −0.6 V to 10 V
IO
Source current
PH Internally Limited
I
O
Source current
VBIAS 6 mA
IS
Sink current
PH 12 A
I
S
Sink current
SS/ENA, PWRGD 10 mA
Voltage differential AGND to PGND ±0.3 V
Continuous power dissipation See Power Dissipation Rating Table
TJOperating virtual junction temperature range −40°C to 150°C
Tstg Storage temperature −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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4
DISSIPATION RATINGS(1)(2)
PACKAGE THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT TA =25°C
POWER RATING TA = 70°C
POWER RATING TA = 85°C
POWER RATING
28 pin PWP with solder 18.2°C/W 5.49 W(3) 3.02 W 2.2 W
28 pn PWP without solder 40.5°C/W 2.48 W 1.36 W 0.99 W
(1) For more information on the PWP package, see the Texas Instruments technical brief, literature number SLMA002.
(2) Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
(3) Maximum power dissipation may be limited by overcurrent protection.
ADDITIONAL 6A SWIFT DEVICES
DEVICE OUTPUT VOLT AGE
TPS54610 0.9 V to 3.3 V
TPS54672 DDR memory adjustable
TPS54680 Sequencing adjustable
TPS54673 Prebias adjustable
RELATED DC/DC PRODUCTS
DTPS40000—Low-input, voltage-mode synchronous buck controller
DTPS759xx—7.5-A low dropout regulator
DPT6440 series—6 A plugin modules
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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5
ELECTRICAL CHARACTERISTICS
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY VOLTAGE, VIN
VIN Input voltage range 3 6 V
fs = 350 kHz, FSEL ≤ 0.8 V, RT open, phase pin open 9.8 15
I
(Q)
Quiescent current fs = 550 kHz, FSEL ≥ 2.5 V, RT open, phase pin open 14 23 mA
I(Q)
Quiescent current
Shutdown, SS/ENA = 0 V 1 1.4
mA
UNDER VOLTAGE LOCK OUT
Start threshold voltage, UVLO 2.95 3 V
Stop threshold voltage, UVLO 2.7 2.8 V
Hysteresis voltage, UVLO 0.16 V
Rising and falling edge deglitch,
UVLO(1) 2.5 µs
BIAS VOLT AGE
Output voltage, VBIAS I(VBIAS) = 0 2.7 2.8 2.95 V
Output current, VBIAS(2) 100 µA
OUTPUT VOLT AGE
TPS54611
TJ = 25°C, VIN = 5 V 0.9 V
TPS54611
3 V ≤ VIN ≤6 V, 0 ≤IL ≤6 A, −40° ≤TJ ≤125°C −2% 2%
TPS54612
TJ = 25°C, VIN = 5 V 1.2 V
TPS54612
3 V ≤ VIN ≤6 V, 0 ≤IL ≤6 A, −40° ≤TJ ≤125°C −2% 2%
TPS54613
TJ = 25°C, VIN = 5 V 1.5 V
VO
Output voltage
TPS54613
3 V ≤ VIN ≤6 V, 0 ≤IL ≤6 A, −40° ≤TJ ≤125°C −2% 2%
V
O
Output voltage
TPS54614
TJ = 25°C, VIN = 5 V 1.8 V
TPS54614
3 V ≤ VIN ≤6 V, 0 ≤IL ≤6 A, −40° ≤TJ ≤125°C −3% 3%
TPS54615
TJ = 25°C, VIN = 5 V 2.5 V
TPS54615
3.2 V ≤ VIN ≤6 V, 0 ≤IL ≤6 A, −40° ≤TJ ≤125°C −3% 3%
TPS54616
TJ = 25°C, VIN = 5 V 3.3 V
TPS54616
4 V ≤ VIN ≤6 V, 0 ≤IL ≤6 A, −40° ≤TJ ≤125°C −3% 3%
REGULATION
Line regulation(1) (3) IL = 3 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C 0.088 %/V
Load regulation(1) (3) IL = 0 A to 6 A, 350 ≤ fs ≤ 550 kHz, TJ = 85°C 0.0917 %/A
(1) Specified by design
(2) Static resistive loads only
(3) Tested using circuit in Figure 10.
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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6
ELECTRICAL CHARACTERISTICS (CONTINUED)
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OSCILLATOR
Internally set—free running frequency
FSEL ≤ 0.8 V, RT open 265 350 440
kHz
Internally set—free running frequency
FSEL ≥ 2.5 V, RT open 415 550 680
kHz
Externally set—free running
RT = 180 kΩ (1% resistor to AGND)(1) 252 280 308
Externally set—free running
frequency range
RT = 160 kΩ (1% resistor to AGND) 290 312 350 kHz
frequency range
RT = 68 kΩ (1% resistor to AGND)(1) 663 700 762
kHz
High level threshold, FSEL 2.5 V
Low level threshold, FSEL 0.8 V
Pulse duration, FSEL(1) 50 ns
Frequency range, FSEL(1) (4) 330 700 kHz
Ramp valley(1) 0.75 V
Ramp amplitude (peak-to-peak)(1) 1 V
Minimum controllable on time(1) 200 ns
Maximum duty cycle(1) 90%
(1) Specified by design
(2) Static resistive loads only
(3) Tested using circuit in Figure 10.
(4) To ensure proper operation when RC filter is used between external clock and FSEL pin, the recommended values are R ≤ 1kΩ and
C ≤ 68 pF.
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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7
ELECTRICAL CHARACTERISTICS (CONTINUED)
TJ = –40°C to 125°C, VI = 3 V to 6 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ERROR AMPLIFIER
Error amplifier open loop voltage gain(1) 26 dB
Error amplifier unity gain bandwidth(1) 3 5 MHz
Error amplifier common mode input voltage range Powered by internal LDO(1) 0 VBIAS V
PWM COMPARA TOR
PWM comparator propagation delay time, PWM
comparator input to PH pin (excluding deadtime) 10-mV overdrive(1) 70 85 ns
SLOW-START/ENABLE
Enable threshold voltage, SS/ENA 0.82 1.20 1.40 V
Enable hysteresis voltage, SS/ENA(1) 0.03 V
Falling edge deglitch, SS/ENA(1) 2.5 µs
(1)
TPS54611 2.6 3.3 4.1
(1)
TPS54612 3.5 4.5 5.4
Internal slow-start time (1)
TPS54613 4.4 5.6 6.7
ms
Internal slow-start time (1)
TPS54614 2.6 3.3 4.1
ms
TPS54615 3.6 4.7 5.6
TPS54616 4.7 6.1 7.6
Charge current, SS/ENA SS/ENA = 0 V 2.5 5 8 µA
Discharge current, SS/ENA SS/ENA = 0.2 V, VI = 2.7 V 1.2 2.3 4.0 mA
POWER GOOD
Power good threshold voltage VSENSE falling 90 %VO
Power good hysteresis voltage See (1) 3 %VO
Power good falling edge deglitch See (1) 35 µs
Output saturation voltage, PWRGD I(sink) = 2.5 mA 0.18 0.3 V
Leakage current, PWRGD VI = 5.5 V 1µA
CURRENT LIMIT
Current limit
VI = 3 V 7.2 10
A
Current limit
VI = 6 V 10 12
A
Current limit leading edge blanking time (1) 100 ns
Current limit total response time(1) 200 ns
THERMAL SHUTDOWN
Thermal shutdown trip point(1) 135 150 165
_C
Thermal shutdown hysteresis(1) 10 _
C
OUTPUT POWER MOSFETS
rDS(on)
Power MOSFET switches
IO = 3 A, VI = 6 V(2) 26 47
mΩ
r
DS(on
)
Power MOSFET switches
IO = 3 A, VI = 3 V(2) 36 65
m
Ω
(1) Specified by design
(2) Matched MOSFETs, low side rDS(on) production tested, high side rDS(on) specified by design.
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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8
INTERNAL BLOCK DIAGRAM
VI
Falling
Edge
Deglitch
Enable
Comparator
1.8 V
VIN
2.94 V
Hysteresis: 0.03
V2.5 µs
Falling
and
Rising
Edge
Deglitch
2.5 µs
VIN UVLO
Comparator
Hysteresis: 0.16
V
Internal/External
Slow-Start
(Internal Slow-Start Time
=
3.3 ms to 6.6 ms)
VI
Feed-Forward
Compensation
−
+
Error
Amplifier
Thermal
Shutdown
145°C
SHUTDOWN
SS_DIS
PWM
Comparator
OSC
Leading
Edge
Blanking
100 ns
RQ
S
Adaptive Dead-Time
and
Control Logic
SHUTDOWN
Sensefet
30 mΩ
VIN
REG
VBIAS
VIN
BOOT
VIN
PH LOUT
CO
PGND
PWRGD
Falling
Edge
Deglitch
35 µs
VSENSE
SHUTDOWN
0.90 Vref
Hysteresis: 0.03 Vref
Power good
Comparator
AGND VBIAS
ILIM
Comparator VIN
VO
FSEL
RTVSENSE
SS/ENA
TPS5461x
30 mΩ
5 µA
Reference/
DAC
2 kΩ
40 kΩ
25 ns Adaptive
Deadtime
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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9
TYPICAL CHARACTERISTICS
Figure 1
0
20
40
60
80
100
120
−40 0 25 85 125
IO = 3 A
VI = 3.3 V
TJ − Junction Temperature − °C
Drain-Source On-State Resistance −
DRAIN-SOURCE ON-STATE
RESISTANCE
vs
JUNCTION TEMPERATURE
Ω
Figure 2
0
20
40
60
80
100
−40 0 25 85 125
IO = 3 A
VI = 5 V
TJ − Junction Temperature − °C
Drain-Source On-State Resistance −
DRAIN-SOURCE ON-STATE
RESISTANCE
vs
JUNCT I O N T E M P E R ATURE
Ω
Figure 3
450
−40 0 25
f − Internally Set Oscillator Frequency −kHz
550
INTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCT I O N T E M P E R ATURE
750
85 125
650
350
250
TJ − Junction Temperature − °C
FSEL ≥ 2.5 V
FSEL ≤ 0.8 V
Figure 4
400
−40 0 25
f − Externally Set Oscillator Frequency − kHz
500
EXTERNALLY SET OSCILLATOR
FREQUENCY
vs
JUNCTION TEMPERATURE
800
85 125
700
300
200
TJ − Junction Temperature − °C
600
RT = 68 k
RT = 100 k
RT = 180 k
Figure 5
0.889
−40 0 25
− Voltage Reference − V
VOLT AGE REFERENCE
vs
JUNCT I O N T E M P E R ATURE
0.895
85 125
0.893
0.887
0.885
TJ − Junction Temperature − °C
0.891
Vref
Figure 6
0.8850
0.8870
0.8890
0.8910
0.8930
0.8950
3456
f = 350 kHz
TA = 85°C
VI − Input Voltage − V
− Output Voltage Regulation − V
OUTPUT VOLTAGE REGULATION
vs
INPUT VOLT AGE
VO
Figure 7
f − Frequency − Hz
60
40
0
0 10 100 1 k 10 k 100 k 1 M
Gain − dB
80
100
ERROR AMPLIFIER
OPEN LOOP RESPONSE
140
10 M
120
20
−20
Phase − Degrees
0
−20
−40
−60
−80
−100
−120
−140
−160
−180
−200
RL= 10 kΩ,
CL = 160 pF,
TA = 25°C
Phase
Gain
Figure 8
TJ − Junction Temperature − °C
3.35
3.20
2.90
−40 0 25 85
Internal Slow-Start Time − ms
3.50
3.65
INTERNAL SLOW-START TIME
vs
JUNCT I O N T E M P E R ATURE
12
5
3.80
3.05
2.75
Figure 9
IL − Load Current − A
2
1.5
0.5
0123456
Device Power Losses − W
2.5
3
DEVICE POWER LOSSES
vs
LOAD CURRENT
5
78
3.5
1
0
4
4.5 TJ = 125°C
FS = 700 kHz
VI = 3.3 V
VI = 5.0 V
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
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10
APPLICATION INFORMATION
Figure 10 shows the schematic diagram for a typical
TPS54614 application. The TPS54614 (U1) can provide
greater than 6 A of output current at a nominal output
voltage o f 1.8 V. For proper operation, the exposed thermal
PowerPAD underneath the integrated circuit package
needs to be soldered to the printed-circuit board.
13
12
7
8
6
BOOT 5
9
10
11
14
15
16
17
18
PH
PH
PH
PH
PH
PH
PH
PH
PH
19
PGND
PGND
PGND
PGND
PGND
PwrPad
AGND
NC
RT
SS/ENA
VIN
20
22
24
VBIAS
27
26
4
2
1
0.047 µF
7.2 µH
680 µF
VO
1.8 V
10 kΩ
Enable 0.1 µF
VI
3 V − 6 V 21
23
28
25
3
10 µF
220 µFVIN
VIN
VIN
VIN
VSENSE
PWRGD
FSEL
PwrGood
CSS
Figure 10. Application Circuit
COMPONENT SELECTION
The values for the components used in this design
example were selected using the SWIFT designer
software t o o l . S W I F T d e s i g n e r p r o vides a complete design
environment for developing dc-dc converters using the
TPS54614, or other devices in the SWIFT product family.
Additional design information is available at www.ti.com.
INPUT FILTER
The input to the circuit is a nominal 3.3 VDC or 5 VDC. The
input filter is a 220-µF POSCAP capacitor, with a
maximum allowable ripple current of 3 A. A 10-µF ceramic
capacitor for the TPS54614 is required, and must be
located as close as possible to the device.
FEEDBACK CIRCUIT
The output voltage of the converter is fed directly into the
VSENSE pin of the TPS54614. The TPS54614 is
internally compensated to provide stability of the output
under varying line and load conditions.
OPERATING FREQUENCY
In the application circuit, 350 kHz operation is selected by
leaving FSEL open. Different operating frequencies can
be selected by connecting a resistor between R T pin and
AGND. Choose the value of R using Equation 1 for the
desired operating frequency:
R+500 kHz
SwitchingFrequency 100 kW
Alternately, a preset operating frequency of 550 kHz can
be selected by leaving RT open and connecting the FSEL
pin to VI.
OUTPUT FILTER
The output filter is composed of a 5.2-µH inductor and a
470-µF capacitor. The inductor is low dc resistance
(16-mΩ) type, Sumida CDRH104R−5R2. The capacitor
used is a 4-V POSCAP with a maximum ESR of 40 mΩ.
The output filter components work with the internal
compensation network to provide a stable closed loop
response for the converter.
(1)
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11
GROUNDING AND POWERPAD LAYOUT
The TPS54611−16 have two internal grounds (analog and
power). Inside the TPS54611−16, the analog ground ties
to all of the noise sensitive signals, while the power ground
ties to the noisier power signals. The PowerPAD is tied
internally t o the analog ground. Noise injected between the
two grounds can degrade the performance of the
TPS54611−16, particularly at higher output currents.
However, ground noise on an analog ground plane can
also cause problems with some of the control and bias
signals. For these reasons, separate analog and power
ground planes are recommended. These two planes
should tie together directly at the IC to reduce noise
between the two grounds. The only components that
should tie directly to the power ground plane are the input
capacitor, the output capacitor, the input voltage
decoupling capacitor, and the PGND pins of the
TPS54611−16. The layout of the TPS54614 evaluation
module is representative of a recommended layout for a
4-layer board. Documentation for the TPS54614
evaluation module can be found on the Texas Instruments
web site (www .ti.com) under the TPS54614 product folder.
See the TPS54614−185 User’s Guide, Texas Instruments
(SLVU053) and the application note, Texas Instruments
(SLVA105).
LAYOUT CONSIDERATIONS FOR THERMAL
PERFORMANCE
For operation at full rated load current, the analog ground
plane must provide adequate heat dissipating area. A 3
inch by 3 inch plane of 1 ounce copper is recommended,
though not mandatory, depending on ambient temperature
and airflow. Most applications have larger areas of internal
ground plane available, and the PowerPAD should be
connected to the largest area available. Additional areas
on the top or bottom layers also help dissipate heat, and
any area available should be used when 3 A or greater
operation is d esired. Connection from the exposes area of
the PowerPAD to the analog ground plane layer should be
made using 0.013 inch diameter vias to avoid solder
wicking through the vias. Six vias should be in the
PowerPAD area with four additional vias located under the
device package. The size of the vias under the package,
but not in the exposed thermal pad area, can be increased
to 0.018. Additional vias beyond the 10 recommended that
enhance thermal performance should be included in areas
not under the device package.
Connect Pin 1 to Analog Ground Plane
in This Area for Optimum Performance
Minimum Recommended Top
Side Analog Ground Area
0.3478
0.0150
0.06
0.0256
0.1700
0.1340
0.0630
0.0400
Ø0.01804 PL
0.2090
Ø0.0130
8 PL
Minimum Recommended Exposed
Copper Area for Powerpad. 5mm
Stencils May Require 10 Percent
Larger Area
0.0650
0.0500
0.0500
0.0650
0.0339
0.0339
0.0500
Minimum Recommended Thermal Vias: 8 x 0.013 Diameter Inside
Powerpad Area 4 x 0.018 Diameter Under Device as Shown.
Additional 0.018 Diameter Vias May Be Used if Top Side Analog Ground
Area Is Extended.
0.3820
Figure 11. Recommended Land Pattern for 28-Pin PWP PowerPAD
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12
PERFORMANCE GRAPHS
Figure 12
VI = 5 V
VI = 3.3V
IL − Load Current − A
70
0123456
Efficiency − %
80
EFFICIENCY
vs
LOAD CURRENT
100
78910
90
60
50
Figure 13
VI = 5 V
VI = 3.3V
1
0.99
0.98
0123456
− Output Voltage − V
1.01
OUTPUT V O LTAGE
vs
LOAD CURRENT
1.03
78910
1.02
0.97
VO
IL − Load Current − A
Figure 14
Phase
Gain
f − Frequency − Hz
20
10
−10
10 100 1 k 10 k 100 k
Gain − dB
30
40
LOOP RESPONSE
60
50
0
−20
Phase − Degrees
180
135
90
45
0
Figure 15
40
t − Time − µs
TRANSIENT RESPONSE
300
020
350
0
250
50
150
60 80 100 120 140 160 180 200
100
200
400
− Output Voltage − mV
VO
0
2
4
6
8
10
12
14
16
− Output Current − A
IO
Figure 16
4
t − Time − µs
START-UP WAVEFORMS
6
02
7
0
5
1
3
6 8 10 12 14 16 18 20
2
4
8
− Input Voltage − VVI
Figure 17
40
t − Time − µs
OUTPUT RIPPLE VOLTAGE
60
020
70
0
50
10
30
60 80 100 120 140 160 180 200
20
40
80
− Output Voltage − mVVO
Figure 18
75
65
35
0123456
− Ambient T emperature −
85
95
AMBIENT TEMPERATURE
vs
LOAD CURRENT
125
78
105
45
25
C
°
TA
IL − Load Current − A
TJ = 125°C
FS = 700 kHz
VI = 3.3 V
VI = 5 V
55
115
Safe Operating Area
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
13
DETAILED DESCRIPTION
Under Voltage Lock Out (UVLO)
The TPS5461x incorporates an under voltage lockout
circuit to keep the device disabled when the input voltage
(VIN) is insufficient. During power up, internal circuits are
held inactive until VIN exceeds the nominal UVLO
threshold voltage of 2.95 V. Once the UVLO start threshold
is reached, device start-up begins. The device operates
until VIN falls below the nominal UVLO stop threshold of
2.8 V. Hysteresis in the UVLO comparator and a 2.5-µs
rising and falling edge deglitch circuit reduces the
likelihood o f shutting the device down due to noise on VIN.
Slow-Start/Enable (SS/ENA)
The slow-start/enable pin provides two functions. First, t he
pin acts as an enable (shutdown) control by keeping the
device turned off until the voltage exceeds the start
threshold voltage of approximately 1.2 V. When SS/ENA
exceeds the enable threshold, device start up begins. The
reference voltage fed to the error amplifier is linearly
ramped up from 0 V to 0.891 V in 3.35 ms. Similarly, the
converter output voltage reaches regulation in
approximately 3.35 ms. Voltage hysteresis and a 2.5-µs
falling edge deglitch circuit reduce the likelihood of
triggering the enable due to noise. See the following table
for start up times for each device
DEVICE OUTPUT V O LTAGE SLOW-START
TPS54611 0.9 V 3.3 ms
TPS54612 1.2 V 4.5 ms
TPS54613 1.5 V 5.6 ms
TPS54614 1.8 V 3.3 ms
TPS54615 2.5 V 4.7 ms
TPS54616 3.3 V 6.1 ms
The second function of the SS/ENA pin provides an
external means for extending the slow-start time with a
ceramic capacitor connected between SS/ENA and
AGND. Adding a capacitor to the SS/ENA pin has two
effects on start-up. First, a delay occurs between release
of the SS/ENA pin and start-up of the output. The delay is
proportional to the slow-start capacitor value and lasts until
the SS/ENA pin reaches the enable threshold. The
start-up delay is approximately:
td+C(SS) 1.2 V
5mA
Second, as the output becomes active, a brief ramp up a t
the internal slow-start rate may be observed before the
externally set slow-start rate takes control and the output
rises at a rate proportional to the slow-start capacitor. The
slow-start time set by the capacitor is approximately:
t(SS) +C(SS) 0.7 V
5mA
The actual slow-start time is likely to be less than the above
approximation due to the brief ramp up at the internal rate.
VBIAS Regulator
The VBIAS regulator provides internal analog and digital
blocks with a stable supply voltage over variations in
junction temperature and input voltage. A high quality,
low-ESR, ceramic bypass capacitor is required on the
VBIAS pin. X7R or X5R grade dielectrics are
recommended because their values are more stable over
temperature. The bypass capacitor should be placed close
to the VBIAS pin and returned to AGND.
External loading on VBIAS is allowed, with the caution that
internal circuits require a minimum VBIAS of 2.7 V, and
external loads on VBIAS with ac or digital switching noise
may degrade performance. The VBIAS pin may be useful
as a reference voltage for external circuits.
Voltage Reference
The voltage reference system produces a precise,
temperature-stable voltage from a bandgap circuit. A
scaling amplifier and DAC are then used to produce the
reference voltages for each of the fixed output devices.
Oscillator and PWM Ramp
The oscillator frequency can be set to internally fixed
values o f 350 kHz or 550 kHz using the FSEL pin as a static
digital input. If a dif ferent frequency of operation is required
for the application, the oscillator frequency can be
externally adjusted from 280 kHz to 700 kHz by connecting
a resistor from the R T pin to AGND and floating the FSEL
pin. The switching frequency is approximated by the
following equation, where R is the resistance from RT to
AGND:
Switching Frequency +100 kW
R 500 [kHz]
External synchronization of the PWM ramp is possible
over the frequency range of 330 kHz to 700 kHz by driving
a synchronization signal into FSEL and connecting a
resistor from R T to AGND. Choose an RT resistor that sets
the free-running frequency to 80% of the synchronization
signal. Table 1 summarizes the frequency selection
configurations.
(2)
(3)
(4)
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
14
Table 1. Summary of the Frequency
Selection Configurations
SWITCHING
FREQUENCY FSEL P I N RT PIN
350 kHz, internally
set Float or AGND Float
550 kHz, internally
set ≥ 2.5 V Float
Externally set 280
kHz to 700 kHz Float R = 68 kΩ to 180 kΩ
Externally
synchronized
frequency(1)
Synchronization
signal R = RT value for 80% of
external synchronization
frequency
(1) To ensure proper operation when RC filter is used between external
clock and FSEL pin, the recommended values are R ≤ 1kΩ and
C ≤ 68 pF.
Error Amplifier
The high performance, wide bandwidth, voltage error
amplifier is gain-limited to provide internal compensation
of the control loop. The user is given limited flexibility in
choosing output L and C filter components. Inductance
values of 4.7 µH to 10 µH are typical and available from
several vendors. The resulting designs exhibit good noise
and ripple characteristics, but with exceptional transient
response. Transient recovery times are typically in the
range of 10 µs to 20 µs.
PWM Control
Signals from the error amplifier output, oscillator, and
current limit circuit are processed by the PWM control
logic. Referring to the internal block diagram, the control
logic includes the PWM comparator, OR gate, PWM latch,
and portions of the adaptive dead-time and control logic
block. During steady-state operation below the current
limit threshold, the PWM comparator output and oscillator
pulse train alternately set and reset the PWM latch. Once
the PWM latch is set, the low-side FET remains on for a
minimum duration set by the oscillator pulse width. During
this period, the PWM ramp discharges rapidly to its valley
voltage. When the ramp begins to charge back up, the
low-side FET turns off and high-side FET turns on. As the
PWM ramp voltage exceeds the error amplifier output
voltage, the PWM comparator resets the latch, thus
turning off the high-side FET and turning on the low-side
FET. The low-side FET remains on until the next oscillator
pulse discharges the PWM ramp.
During transient conditions, the error amplifier output
could b e below the PWM ramp valley voltage or above the
PWM peak voltage. If the error amplifier is high, the PWM
latch i s never reset, and the high-side FET remains on until
the oscillator pulse signals the control logic to turn the
high-side FET off and the low-side FET on. The device
operates a t its maximum duty cycle until the output voltage
rises to the regulation set-point, setting VSENSE to
approximately the same voltage as Vref. If the error
amplifier output is low, the PWM latch is continually reset
and the high-side FET does not turn on. The low-side FET
remains on until the VSENSE voltage decreases to a
range that allows the PWM comparator to change states.
The TPS54611−TPS54616 devices are capable of sinking
current continuously until the output reaches the
regulation set-point.
If the current limit comparator trips for longer than 100 ns,
the PWM latch resets before the PWM ramp exceeds the
error amplifier output. The high-side FET turns off and the
low-side FET turns on to decrease the energy in the output
inductor and consequently decrease the output current.
This process is repeated each cycle in which the current
limit comparator is tripped.
Dead-Time Control and MOSFET Drivers
Adaptive dead-time control prevents shoot-through
current from flowing in both N-channel power MOSFETs
during the switching transitions by actively controlling the
turnon times of the MOSFET drivers. The high-side driver
does not turn on until the voltage at the gate of the low-side
FET is below 2 V. The high-side and low-side drivers are
designed with 300-mA source and sink capability to
quickly drive the power MOSFETs gates. The low-side
driver is supplied from VIN, while the high-side drive is
supplied from the BOOT pin. A bootstrap circuit uses an
external BOOT capacitor and internal 2.5-Ω bootstrap
switch connected between the VIN and BOOT pins. The
integrated bootstrap switch improves drive efficiency and
reduces external component count.
Overcurrent Protection
Cycle-by-cycle current limiting is achieved by sensing the
current flow through the high-side MOSFET and a
differential amplifier with preset overcurrent threshold. The
high-side MOSFET is turned off within 200 ns of reaching
the current limit threshold. A 100-ns leading edge blanking
circuit prevents false tripping of current limit. Current limit
detection occurs only when current flows from VIN to PH
when sourcing current to the output filter. Load protection
during current sink operation is provided by thermal
shutdown.
Thermal Shutdown
The device uses the thermal shutdown to turn off the power
MOSFETs and disable the controller if the junction
temperature exceeds 150°C. The device is released from
shutdown when the junction temperature decreases to
10°C below the thermal shutdown trip point, and starts up
under control of the slow-start circuit. Thermal shutdown
provides protection when an overload condition is
sustained for several milliseconds. With a persistent fault
condition, the device cycles continuously: starting up by
SGLS266G − OCTOBER 2004 − REVISED JUNE 2008
www.ti.com
15
control of the slow-start circuit, heating up due to the fault,
and then shutting down upon reaching the thermal
shutdown trip point.
Power Good (PWRGD)
The power good circuit monitors for under voltage
conditions on VSENSE. If the voltage on VSENSE falls
10% below the reference voltage, the open-drain PWRGD
output is pulled low. PWRGD is also pulled low if VIN is
less than the UVLO threshold, or SS/ENA is low, or
thermal shutdown is asserted. When VIN = UVLO
threshold, SS/ENA = enable threshold, and VSENSE >
90% of Vref, the open drain output of the PWRGD pin is
high. A hysteresis voltage equal to 3% of Vref and a 35-µs
falling edge deglitch circuit prevent tripping of the power
good comparator due to high-frequency noise.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS54612QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54613QPWPRQ1 ACTIVE HTSSOP PWP 28 TBD Call TI Call TI
TPS54614QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54615QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS54616QPWPRQ1 ACTIVE HTSSOP PWP 28 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
OTHER QUALIFIED VERSIONS OF TPS54612-Q1, TPS54613-Q1, TPS54614-Q1, TPS54615-Q1, TPS54616-Q1 :
•Catalog: TPS54612, TPS54613, TPS54614, TPS54615, TPS54616
•Enhanced Product: TPS54612-EP, TPS54613-EP, TPS54614-EP, TPS54615-EP, TPS54616-EP
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
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