LMX2531
LMX2531 High Performance Frequency Synthesizer System with Integrated VCO
Literature Number: SNAS252P
LMX2531
September 17, 2010
High Performance Frequency Synthesizer System with
Integrated VCO
General Description
The LMX2531 is a low power, high performance frequency
synthesizer system which includes a fully integrated delta-
sigma PLL and VCO with fully integrated tank circuit. The third
and fourth poles are also integrated and also adjustable. Also
included are integrated ultra-low noise and high precision
LDOs for the PLL and VCO which give higher supply noise
immunity and also more consistent performance. When com-
bined with a high quality reference oscillator, the LMX2531
generates very stable, low noise local oscillator signals for up
and down conversion in wireless communication devices.
The LMX2531 is a monolithic integrated circuit, fabricated in
an advanced BiCMOS process. There are several different
versions of this product in order to accommodate different
frequency bands.
Device programming is facilitated using a three-wire
MICROWIRE Interface that can operate down to 1.8 volts.
Supply voltage range is 2.8 to 3.2 Volts. The LMX2531 is
available in a 36 pin 6x6x0.8 mm Lead-Free Leadless Lead-
frame Package (LLP).
Target Applications
■3G Cellular Base Stations (WCDMA, TD-
SCDMA,CDMA2000)
■2G Cellular Base Stations (GSM/GPRS, EDGE,
CDMA1xRTT)
■Wireless LAN
■Broadband Wireless Access
■Satellite Communications
■Wireless Radio
■Automotive
■CATV Equipment
■Instrumentation and Test Equipment
■RFID Readers
■Data Converter Clocking
Features
■Multiple Frequency Options Available
—See Selection Guide Below
—Frequencies from: 553 MHz - 3132 MHz
■PLL Features
—Fractional-N Delta Sigma Modulator Order
programmable up to 4th order
—FastLock/Cycle Slip Reduction with Timeout Counter
—Partially integrated, adjustable Loop Filter
—Very low phase noise and spurs
■VCO Features
—Integrated tank inductor
—Low phase noise
■Other Features
—2.8 V to 3.2 V Operation
—Low Power-Down Current
—1.8 V MICROWIRE Support
—Package: 36 Lead LLP
Part Low Band High Band
LMX2531LQ1146E 553 - 592 MHz 1106 - 1184 MHz
LMX2531LQ1226E 592 - 634 MHz 1184 - 1268 MHz
LMX2531LQ1312E 634 - 680 MHz 1268 - 1360 MHz
LMX2531LQ1415E 680 - 735 MHz 1360 - 1470 MHz
LMX2531LQ1500E 749.5 - 755 MHz 1499 - 1510 MHz
LMX2531LQ1515E 725 - 790 MHz 1450 - 1580 MHz
LMX2531LQ1570E 765 - 818 MHz 1530 - 1636 MHz
LMX2531LQ1650E 795 - 850 MHz 1590 - 1700 MHz
LMX2531LQ1700E 831 - 885 MHz 1662 - 1770 MHz
LMX2531LQ1742 880 - 933 MHz 1760 - 1866 MHz
LMX2531LQ1778E 863 - 920 MHz 1726 - 1840 MHz
LMX2531LQ1910E 917 - 1014 MHz 1834 - 2028 MHz
LMX2531LQ2080E 952 - 1137 MHz 1904 - 2274 MHz
LMX2531LQ2265E 1089 - 1200 MHz 2178 - 2400 MHz
LMX2531LQ2570E 1168 - 1395 MHz 2336 - 2790 MHz
LMX2531LQ2820E 1355 - 1462 MHz 2710 - 2925 MHz
LMX2531LQ3010E 1455 - 1566 MHz 2910 - 3132 MHz
© 2010 National Semiconductor Corporation 201011 www.national.com
LMX2531 High Performance Frequency Synthesizer System with Integrated VCO
Functional Block Diagram
20101101
www.national.com 2
LMX2531
Connection Diagrams
36-Pin LLP (LQ) Package, D Version
(LMX2531LQ1146E/1226E/1312E/1415E/1515E/2820E/3010E)
20101104
36-Pin LLP (LQ) Package, A Version
(All Other Versions)
20101102
3 www.national.com
LMX2531
Pin Descriptions
Pin # Pin Name I/O Description
1 VccDIG - Power Supply for digital LDO circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should be
placed as close as possible to this pin and ground.
3 GND - Ground
2,4,5,7,
12, 13,
29, 35
NC - No Connect.
6 VregBUF - Internally regulated voltage for the VCO buffer circuitry. Connect to ground with a capacitor.
8 DATA I MICROWIRE serial data input. High impedance CMOS input. This pin must not exceed 2.75V. Data is
clocked in MSB first. The last bits clocked in form the control or register select bits.
9 CLK I MICROWIRE clock input. High impedance CMOS input. This pin must not exceed 2.75V. Data is clocked
into the shift register on the rising edge.
10 LE I MICROWIRE Latch Enable input. High impedance CMOS input. This pin must not exceed 2.75V. Data
stored in the shift register is loaded into the selected latch register when LE goes HIGH.
11 CE I
Chip Enable Input. High impedance CMOS input. This pin must not exceed 2.75V. When CE is brought
high the LMX2531 is powered up corresponding to the internal power control bits. Although the part can
be programmed when powered down, it is still necessary to reprogram the R0 register to get the part to
re-lock.
14, 15 NC - No Connect. Do NOT ground.
16 VccVCO - Power Supply for VCO regulator circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should
be placed as close as possible to this pin and ground.
17 VregVCO - Internally regulated voltage for VCO circuitry. Not intended to drive an external load. Connect to ground
with a capacitor and some series resistance.
18 VrefVCO - Internal reference voltage for VCO LDO. Not intended to drive an external load. Connect to ground with
a capacitor.
19 GND - Ground for the VCO circuitry.
20 GND - Ground for the VCO Output Buffer circuitry.
21 Fout O Buffered RF Output for the VCO.
22 VccBUF - Power Supply for the VCO Buffer circuitry. Input may range from 2.8 - 3.2 V. Bypass capacitors should
be placed as close as possible to this pin and ground.
23 Vtune I Tuning voltage input for the VCO. For connection to the CPout Pin through an external passive loop
filter.
24 CPout O Charge pump output for PLL. For connection to Vtune through an external passive loop filter.
25 FLout O An open drain NMOS output which is used for FastLock or a general purpose output.
26 VregPLL1 - Internally regulated voltage for PLL charge pump. Not intended to drive an external load. Connect to
ground with a capacitor.
27 VccPLL - Power Supply for the PLL. Input may range from 2.8 - 3.2 V. Bypass capacitors should be placed as
close as possible to this pin and ground.
28 VregPLL2 - Internally regulated voltage for RF digital circuitry. Not intended to drive an external load. Connect to
ground with a capacitor.
30 Ftest/LD O Multiplexed CMOS output. Typically used to monitor PLL lock condition.
31 OSCin I Oscillator input.
32 OSCin* I Oscillator complimentary input. When a single ended source is used, then a bypass capacitor should be
placed as close as possible to this pin and be connected to ground.
33 Test O This pin is for test purposes and should be grounded for normal operation.
34 GND - Ground
36 VregDIG - Internally regulated voltage for LDO digital circuitry.
www.national.com 4
LMX2531
Connection Diagram
20101111
Pin(s) Application Information
VccDIG
VccVCO
VccBUF
VccPLL
These pins are inputs to voltage regulators. Because the LMX2531 contains internal regulators, the power supply noise
rejection is very good and capacitors at this pin are not critical. An RC filter can be used to reduce supply noise, but if the
capacitor is too large and is placed too close to these pins, they can sometimes cause phase noise degradation in the 100
- 300 kHz offset range. Recommended values are from open to 1 μF. The series resistors serve to filter power supply noise
and isolate these pins from large capacitances.
VregDIG There is not really any reason to use any other values than the recommended value of 10 nF
VrefVCO If the VrefVCO capacitor is changed, it is recommended to keep this capacitor between 1/100 and 1/1000 of the value of
the VregVCO capacitor.
VregVCO
Because this pin is the output of a regulator, there are stability concerns if there is not sufficient series resistance. For
ceramic capacitors, the ESR (Equivalent Series Resistance) is too low, and it is recommended that a series resistance of
1 - 3.3Ω is necessary. If there is insufficient ESR, then there may be degradation in the phase noise, especially in the 100
- 300 kHz offset. Recommended values are from 1 μF to 10 μF.
VregPLL1
VregPLL2
The choice of the capacitor value at this pin involves a trade-off between integer spurs and phase noise in the 100 - 300
kHz offset range. Using a series resistor of about 220 mΩ in series with a capacitance that has an impedance of about 150
mΩ at the phase detector frequency seems to give an optimal trade-off. For instance, if the phase detector frequency is
2.5 MHz, then make this series capacitor 470 nF. If the phase detector frequency is 10 MHz, make this capacitance about
100 nF.
CLK
DATA
LE
Since the maximum voltage on these pins is less than the minimum Vcc voltage, level shifting may be required if the output
voltage of the microcontroller is too high. This can be accomplished with a resistive divider.
5 www.national.com
LMX2531
Pin(s) Application Information
CE
As with the CLK, DATA, and LE pins, level shifting may be required if the output voltage of the microcontroller is too high.
A resistive divider or a series diode are two ways to accomplish this. The diode has the advantage that no current flows
through it when the chip is powered down.
Ftest/LD It is an option to use the lock detect information from this pin.
Fout This is the high frequency output. This needs to be AC coupled, and matching may also be required. The value of the DC
blocking capacitor may be changed, depending on the output frequency.
CPout
Vtune
In most cases, it is sufficient to short these together, although there always the option of adding additional poles. C1_LF,
C2_LF, and R2_LF are used in conjunction with the internal loop filter to make a fourth order loop filter.
R2pLF This is the fastlock resistor, which can be useful in many cases, since the spurs are often better with low charge pump
currents, and the internal loop filter can be adjusted during fastlock.
OSCin This is the reference oscillator input pin. It needs to be AC coupled.
OSCin* If the device is being driven single-ended, this pin needs to be shunted to ground with a capacitor.
In addition to these suggestions be sure to also consult the evaluation board instructions at www.national.com which include
schematic, layout, and bill of material. In addition to this, these instructions also contain measured data, such as phase noise and
spurs.
www.national.com 6
LMX2531
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors
for availability and specifications.
Parameter Symbol Ratings Units
Power Supply Voltage
VCC
(VccDIG, VccVCO,
VccBUF, VccPLL)
-0.3 to 3.5
V
All other pins (Except
Ground) -0.3 to 3.0
Storage Temperature
Range TSTG -65 to 150 °C
Lead Temperature (solder 4 sec.) TL+ 260 °C
Junction Temperature TJ+ 125 °C
Recommended Operating Conditions
Parameter Symbol Min Typ Max Units
Power Supply Voltage
(VccDig, VccVCO, VccBUF) Vcc 2.8 3.0 3.2 V
Serial Interface and Power Control
Voltage Vi0 2.75 V
Ambient Temperature
(Note 5)TA-40 +85 °C
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for
which the device is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical
Characteristics. The guaranteed specifications apply only to the test conditions listed.
Package Thermal Information
The following package information assumes a JEDEC standard board with 9 thermal vias.
Package θJA θJC
LQA036D 35.5 °C/W 9.1 °C/W
LQA036A 35.5 °C/W 9.1 °C/W
7 www.national.com
LMX2531
Electrical Characteristics (VCC = 3.0 V, -40°C ≤ TA ≤ 85 °C; except as specified.)
Symbol Parameter Conditions Min Typ Max Units
Current Consumption
ICC
Power Supply Current Power
Supply Current
Divider Disabled
LMX2531LQ2265E
/2570E 38 44
mA
LMX2531LQ2820E
/3010E 38 46
All Other Options 34 41
Divider Enabled
LMX2531LQ2265E
/2570E 41 49
LMX2531LQ2820E
/3010E 44 52
All Other Options 37 46
ICCPD Power Down Current CE = 0 V, Part Initialized 7 µA
Oscillator
IIHOSC Oscillator Input High Current VIH = 2.75 V 100 µA
IILOSC Oscillator Input Low Current VIL = 0 -100 µA
fOSCin Frequency Range (Note 2) 5 80 MHz
vOSCin Oscillator Sensitivity 0.5 2.0 Vpp
PLL
fPD Phase Detector Frequency 32 MHz
ICPout
Charge Pump
Output Current Magnitude
ICP = 0 90 µA
ICP = 1 180 µA
ICP = 3 360 µA
ICP = 15 1440 µA
ICPoutTRI CP TRI-STATE Current 0.4 V < VCPout < 2.0 V 2 10 nA
ICPoutMM Charge Pump
Sink vs. Source Mismatch
VCPout = 1.2 V
TA = 25°C 2 8 %
ICPoutV
Charge Pump
Current vs. CP Voltage
Variation
0.4 V < VCPout < 2.0 V
TA = 25°C 4 %
ICPoutTCP Current vs. Temperature
Variation VCPout = 1.2 V 8 %
LN(f)
Normalized PLL 1/f Noise
LNPLL_flicker(10 kHz)
(Note 3)
ICP = 1X Charge Pump Gain
-94
dBc/Hz
ICP = 16X Charge Pump Gain -104
Normalized PLL Noise Floor
LNPLL_flat
(Note 4)
ICP = 1X Charge Pump Gain
-202
dBc/Hz
ICP = 16X Charge Pump Gain -212
www.national.com 8
LMX2531
Symbol Parameter Conditions Min Typ Max Units
VCO Frequencies
fFout
Operating Frequency Range
(All options have a frequency
divider, this applies before the
divider. The frequency after the
divider is half of what is shown)
LMX2531LQ1146E 1106 1184
MHz
LMX2531LQ1226E 1184 1268
LMX2531LQ1312E 1268 1360
LMX2531LQ1415E 1360 1470
LMX2531LQ1500E 1499 1510
LMX2531LQ1515E 1450 1580
LMX2531LQ1570E 1530 1636
LMX2531LQ1650E 1590 1700
LMX2531LQ1700E 1662 1770
LMX2531LQ1742 1760 1866
LMX2531LQ1778E 1726 1840
LMX2531LQ1910E 1834 2028
LMX2531LQ2080E 1904 2274
LMX2531LQ2265E 2178 2400
LMX2531LQ2570E 2336 2790
LMX2531LQ2820E 2710 2925
LMX2531LQ3010E 2910 3132
9 www.national.com
LMX2531
Symbol Parameter Conditions Min Typ Max Units
Other VCO Specifications
ΔTCL
Maximum Allowable
Temperature Drift for
Continuous Lock
(Note 5)
LMX2531LQ1742 65
°C
LMX2531LQ1500E/1570E/1650E/1146E/1226/1312E/
1415E/1515E 90
LMX2531LQ1700E/1778E/1910E/2080E/2265E/
2570E/2820E/3010E 125
pFout
Output Power to a 50 Ω Load
(Applies across entire tuning
range.)
Divider Disabled
LMX2531LQ1146E 1 4.0 7
dBm
LMX2531LQ1226E 1 3.5 7
LMX2531LQ1312E 1 3.5 7
LMX2531LQ1415E 0 3.0 6
LMX2531LQ1500E 1 3.5 7.0
LMX2531LQ1515E -1 2.5 5
LMX2531LQ1570E 2 4.5 8
LMX2531LQ1650E 2 4.5 8
LMX2531LQ1700E 1 3.5 7
LMX2531LQ1742 1 3.5 7
LMX2531LQ1778E 1 3.5 7
LMX2531LQ1910E 1 3.5 7
LMX2531LQ2080E 1 3.5 7
LMX2531LQ2265E 1 3.5 7
LMX2531LQ2570E 0 3.0 6
LMX2531LQ2820E -0.5 2.5 5.5
LMX2531LQ3010E -1.5 1.5 4.5
Divider Enabled
LMX2531LQ1146E -1 2.0 5
dBm
LMX2531LQ1226E -1 2.0 5
LMX2531LQ1312E -1 1.5 4
LMX2531LQ1415E -2 0.5 3
LMX2531LQ1500E 1 3.0 6.0
LMX2531LQ1515E -2 0.5 3
LMX2531LQ1570E 1 3.0 6
LMX2531LQ1650E 1 3.0 6
LMX2531LQ1700E 1 3.0 6
LMX2531LQ1742 1 3.0 6
LMX2531LQ1778E 1 3.0 6
LMX2531LQ1910E 1 3.0 6
LMX2531LQ2080E 0 2.5 5
LMX2531LQ2265E 0 2.5 5
LMX2531LQ2570E -1 1.5 4
LMX2531LQ2820E -2.5 0 2.5
LMX2531LQ3010E -3 -0.5 2
www.national.com 10
LMX2531
Symbol Parameter Conditions Min Typ Max Units
KVtune
Fine Tuning Sensitivity
(When a range is displayed in
the typical column, indicates the
lower sensitivity is typical at the
lower end of the tuning range,
and the higher tuning sensitivity
is typical at the higher end of the
tuning range.)
LMX2531LQ1146E 2.5
-5.5
MHz/V
LMX2531LQ1226E 3-6
LMX2531LQ1312E 3-6
LMX2531LQ1415E 3.5
-6.5
LMX2531LQ1500E 4-7
LMX2531LQ1515E 4-7
LMX2531LQ1570E 4-7
LMX2531LQ1650E 4-7
LMX2531LQ1700E 6-10
LMX2531LQ1742 4-7
LMX2531LQ1778E 6-10
LMX2531LQ1910E 8-14
LMX2531LQ2080E 9-20
LMX2531LQ2265E 10-16
LMX2531LQ2570E 10-23
LMX2531LQ2820E 12-28
LMX2531LQ3010E 13-29
HSFout
Harmonic Suppression
(Applies Across Entire Tuning
Range)
2nd Harmonic
50 Ω Load
Divider
Disabled
LMX2531LQ1146E
/1226E/1312E
/1415E/1515E
-35 -25
dBc
LMX2531LQ2820E
/3010E -40
All Other Options -30 -25
Divider
Enabled
LMX2531LQ1146E
/1226E/1312E
/1415E/1515E
-30 -20
LMX2531LQ2820E
/3010E -30 -15
All Other Options -20 -15
3rd Harmonic
50 Ω Load
Divider
Disabled
LMX2531LQ1146E
/1226E/1312E -35 -30
LMX2531LQ2820E
/3010E -50
All Other Options -40 -35
Divider
Enabled
LMX2531LQ1146E
/1226E/1312E
/1570E/1650E
-20 -15
LMX2531LQ2820E
/3010E -40 -20
All Other Options -25 -20
PUSHFout Frequency Pushing Creg = 0.1uF, VDD ± 100mV, Open Loop 300 kHz/V
PULLFout Frequency Pulling VSWR = 2:1, Open Loop ±600 kHz
ZFout Output Impedance 50 Ω
11 www.national.com
LMX2531
Symbol Parameter Conditions Min Typ Max Units
VCO Phase Noise (Note 6)
L(f)Fout
Phase Noise
(LMX2531LQ1146E)
fFout = 1146 MHz
DIV2 = 0
10 kHz Offset -96
dBc/Hz
100 kHz Offset -121
1 MHz Offset -142
5 MHz Offset -156
fFout = 573 MHz
DIV2 = 1
10 kHz Offset -101
100 kHz Offset -126
1 MHz Offset -147
5 MHz Offset -156
L(f)Fout
Phase Noise
(LMX2531LQ1226E)
fFout = 1226 MHz
DIV2 = 0
10 kHz Offset -95
dBc/Hz
100 kHz Offset -121
1 MHz Offset -142
5 MHz Offset -155
fFout = 613 MHz
DIV2 = 1
10 kHz Offset -101
100 kHz Offset -126
1 MHz Offset -147
5 MHz Offset -155
L(f)Fout
Phase Noise
(LMX2531LQ1312E)
fFout = 1314 MHz
DIV2 = 0
10 kHz Offset -95
dBc/Hz
100 kHz Offset -121
1 MHz Offset -140
5 MHz Offset -154
fFout = 657 MHz
DIV2 = 1
10 kHz Offset -101
100 kHz Offset -126
1 MHz Offset -146
5 MHz Offset -154
L(f)Fout
Phase Noise
(LMX2531LQ1415E)
fFout = 1415 MHz
DIV2 = 0
10 kHz Offset -95
dBc/Hz
100 kHz Offset -121
1 MHz Offset -141
5 MHz Offset -154
fFout = 707.5 MHz
DIV2 = 1
10 kHz Offset -100
100 kHz Offset -126
1 MHz Offset -146
5 MHz Offset -154
L(f)Fout
Phase Noise
(LMX2531LQ1500E)
fFout = 1500 MHz
DIV2 = 1
10 kHz Offset -97
dBc/Hz
100 KHz Offset -120
1 MHz Offset -142
5 MHz Offset -155
fFout = 750 MHz
DIV2 = 1
10 kHz Offset -103
100 kHz Offset -126
1 MHz Offset -131
5 MHz Offset -155
L(f)Fout
Phase Noise
(LMX2531LQ1515E)
fFout = 1515 MHz
DIV2 = 0
10 kHz Offset -96
dBc/Hz
100 kHz Offset -122
1 MHz Offset -142
5 MHz Offset -153
fFout = 757.5 MHz
DIV2 = 1
10 kHz Offset -99
100 kHz Offset -125
1 MHz Offset -145
5 MHz Offset -154
www.national.com 12
LMX2531
Symbol Parameter Conditions Min Typ Max Units
L(f)Fout
Phase Noise
(LMX2531LQ1570E)
fFout = 1583 MHz
DIV2 = 0
10 kHz Offset -93
dBc/Hz
100 kHz Offset -118
1 MHz Offset -140
5 MHz Offset -154
fFout = 791.5 MHz
DIV2 = 1
10 kHz Offset -99
100 kHz Offset -122
1 MHz Offset -144
5 MHz Offset -155
L(f)Fout
Phase Noise
(LMX2531LQ1650E)
fFout = 1645 MHz
DIV2 = 0
10 kHz Offset -93
dBc/Hz
100 kHz Offset -118
1 MHz Offset -140
5 MHz Offset -154
fFout = 822.5 MHz
DIV2 = 1
10 kHz Offset -99
100 kHz Offset -122
1 MHz Offset -144
5 MHz Offset -155
L(f)Fout
Phase Noise
(LMX2531LQ1700E)
fFout = 1716 MHz
DIV2 = 0
10 kHz Offset -92
dBc/Hz
100 kHz Offset -117
1 MHz Offset -139
5 MHz Offset -153
fFout = 858 MHz
DIV2 = 1
10 kHz Offset -98
100 kHz Offset -122
1 MHz Offset -144
5 MHz Offset -154
L(f)Fout
Phase Noise
(LMX2531LQ1742)
fFout= 1813 MHz
DIV2 = 0
10 kHz Offset -92
dBc/Hz
100 kHz Offset -117
1 MHz Offset -140
5 MHz Offset -152
fFout = 906.5 MHz
DIV2 = 1
10 kHz Offset -99
100 kHz Offset -122
1 MHz Offset -143
5 MHz Offset -152
L(f)Fout
Phase Noise
(LMX2531LQ1778E)
fFout = 1783 MHz
DIV2 = 0
10 kHz Offset -92
dBc/Hz
100 kHz Offset -117
1 MHz Offset -139
5 MHz Offset -152
fFout = 891.5 MHz
DIV2 = 1
10 kHz Offset -97
100 kHz Offset -122
1 MHz Offset -144
5 MHz Offset -154
L(f)Fout
Phase Noise
(LMX2531LQ1910E)
fFout = 1931 MHz
DIV2 = 0
10 kHz Offset -89
dBc/Hz
100 kHz Offset -115
1 MHz Offset -138
5 MHz Offset -151
fFout = 965.5 MHz
DIV2 = 1
10 kHz Offset -95
100 kHz Offset -121
1 MHz Offset -143
5 MHz Offset -155
13 www.national.com
LMX2531
Symbol Parameter Conditions Min Typ Max Units
L(f)Fout
Phase Noise
(LMX2531LQ2080E)
fFout = 2089 MHz
DIV2 = 0
10 kHz Offset -87
dBc/Hz
100 kHz Offset -113
1 MHz Offset -136
5 MHz Offset -150
fFout = 1044.5 MHz
DIV2 = 1
10 kHz Offset -93
100 kHz Offset -119
1 MHz Offset -142
5 MHz Offset -154
L(f)Fout
Phase Noise
(LMX2531LQ2265E)
fFout = 2264 MHz
DIV2 = 0
10 kHz Offset -88
dBc/Hz
100 kHz Offset -113
1 MHz Offset -136
5 MHz Offset -150
fFout = 1132 MHz
DIV2 = 1
10 kHz Offset -94
100 kHz Offset -118
1 MHz Offset -141
5 MHz Offset -154
L(f)Fout
Phase Noise
(LMX2531LQ2570E)
fFout = 2563 MHz
DIV2 = 0
10 kHz Offset -86
dBc/Hz
100 kHz Offset -112
1 MHz Offset -135
5 MHz Offset -149
fFout = 1281.5 MHz
DIV2 = 1
10 kHz Offset -91
100 kHz Offset -117
1 MHz Offset -139
5 MHz Offset -152
L(f)Fout
Phase Noise
(LMX2531LQ2820E)
fFout = 2818 MHz
DIV2 = 0
10 kHz Offset -84
dBc/Hz
100 kHz Offset -111
1 MHz Offset -133
5 MHz Offset -148
fFout = 1409 MHz
DIV2 = 1
10 kHz Offset -90
100 kHz Offset -117
1 MHz Offset -138
5 MHz Offset -150
L(f)Fout
Phase Noise
(LMX2531LQ3010E)
fFout = 3021 MHz
DIV2 = 0
10 kHz Offset -83
dBc/Hz
100 kHz Offset -110
1 MHz Offset -132
5 MHz Offset -147
fFout = 1510.5 MHz
DIV2 = 1
10 kHz Offset -88
100 kHz Offset -116
1 MHz Offset -137
5 MHz Offset -148
www.national.com 14
LMX2531
Symbol Parameter Conditions Min Typ Max Units
Digital Interface (DATA, CLK, LE, CE, Ftest/LD, FLout)
VIH High-Level Input Voltage 1.6 2.75 V
VIL Low-Level Input Voltage 0.4 V
IIH High-Level Input Current VIH = 1.75 -3.0 3.0 µA
IIL Low-Level Input Current VIL = 0 V -3.0 3.0 µA
VOH High-Level Output Voltage IOH = 500 µA 2.0 2.65 V
VOL Low-Level Output Voltage IOL = -500 µA 0.0 0.4 V
MICROWIRE Timing
tCS Data to Clock Set Up Time See Data Input Timing 25 ns
tCH Data to Clock Hold Time See Data Input Timing 20 ns
tCWH Clock Pulse Width High See Data Input Timing 25 ns
tCWL Clock Pulse Width Low See Data Input Timing 25 ns
tES Clock to Enable Set Up Time See Data Input Timing 25 ns
tCES Enable to Clock Set Up Time See Data Input Timing 25 ns
tEWH Enable Pulse Width High See Data Input Timing 25 ns
Note 2: There are program bits that need to be set based on the OSCin frequency. Refer to the following sections: 2.7.8 XTLSEL[2:0] -- Crystal Select, 2.8.1
XTLDIV[1:0] -- Division Ratio for the Crystal Frequency, 2.8.2 XTLMAN[11:0] -- Manual Crystal Mode, 2.9.1 XTLMAN2 -- MANUAL CRYSTAL MODE SECOND
ADJUSTMENT, and2.9.2 LOCKMODE -- FREQUENCY CALIBRATION MODE. Not all bit settings can be used for all frequency choices of OSCin. For instance,
automatic modes described in 2.7.8 XTLSEL[2:0] -- Crystal Select do not work below 8 MHz.
Note 3: One of the specifications for modeling PLL in-band phase noise is the PLL 1/f noise normalized to 1 GHz carrier frequency and 10 kHz offset, LPLL_flicker
(10 kHz). From this normalized index of PLL 1/f noise, the PLL 1/f noise can be calculated for any carrier and offset frequency as:
LNPLL_flicker(f) = LPLL_flicker(10 kHz) - 10·log(10 kHz / f) + 20·log( Fout / 1 GHz ). Flicker noise can dominate at low offsets from the carrier and has a 10 dB/decade
slope and improves with higher charge pump currents and at higher offset frequencies . To accurately measure LPLL_flicker(10 kHz) it is important to use a high
phase detector frequency and a clean reference to make it such that this measurement is on the 10 dB/decade slope close to the carrier. LPLL_flicker(f) can be
masked by the reference oscillator performance if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker
(f) and LPLL_flat. In other words,LPLL(f) = 10·log(10(LNPLL_flat / 10 ) + 10(LNPLL_flicker (f) / 10 )
Note 4: A specification used for modeling PLL in-band phase noise floor is the Normalized PLL noise floor, LNPLL_flat, and is defined as:
LNPLL_flat = L(f) – 20·log(N) – 10·log(fPD). LPLL_flat is the single side band phase noise in a 1 Hz Bandwidth and fPD is the phase detector frequency of the synthesizer.
LPLL_flat contributes to the total noise, L(f). To measure LPLL_flat the offset frequency must be chosen sufficiently smaller then the loop bandwidth of the PLL, and
yet large enough to avoid a substantial noise contribution from the reference and PLL flicker noise. LPLL_flat can be masked by the reference oscillator performance
if a low power or noisy source is used. The total PLL in-band phase noise performance is the sum of LPLL_flicker(f) and LPLL_flat. In other
words,LPLL(f) = 10·log(10(LNPLL_flat / 10 ) + 10(LNPLL_flicker (f) / 10 )
Note 5: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies that the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for
continuous lock, then it will be necessary to reload the R0 register to ensure that it stays in lock. Regardless of what temperature the part was initially programmed
at, the temperature can never drift outside the frequency range of -40°C ≤TA≤ 85°C without violating specifications.
Note 6: The VCO phase noise is measured assuming that the loop bandwidth is sufficiently narrow that the VCO noise dominates. The maximum limits apply
only at center frequency and over temperature, assuming that the part is reloaded at each test frequency. Over frequency, the phase noise can vary 1 to 2 dB,
with the worst case performance typically occurring at the highest frequency. Over temperature, the phase noise typically varies 1 to 2 dB, assuming the part is
reloaded.
15 www.national.com
LMX2531
Serial Data Timing Diagram
20101103
The DATA is clocked into a shift register on each rising edge of the CLK signal. On the rising edge of the LE signal, the data is
sent from the shift registers to an actual counter. There are several other considerations as well.
•A slew rate of at least 30 V/μs is recommended for the CLK, DATA, and LE signals.
•After the programming is complete, the CLK, DATA, and LE signals should be returned to a low state.
•It is recommended to put a small delay between the falling edge of the last CLK pulse and the rising edge of the LE pulse for
optimal noise immunity and the most reliable programming.
•Although it is strongly recommended to keep LE low after programming, LE can be kept high if bit R5[23] is changed to 0 (from
its default value of 1). If this bit is changed, then the operation of the part is not guaranteed because it is not tested under these
conditions.
•If the CLK and DATA lines are toggled while the in VCO is in lock, as is sometimes the case when these lines are shared with
other parts, the phase noise may be degraded during the time of this programming.
•If the part is not programmed, the values of the registers in this part have to be assumed to be random. Therefore, the current
consumption and spurs generated by this part can be random. If this is an issue, the CE pin can be held low for more consistent
behavior.
www.national.com 16
LMX2531
Typical Performance Characteristics
OSCin Input Impedance
20101106
Frequency
(MHz)
Powered Up (kΩ) Powered Down (kΩ)
Real Imaginary Magnitude Real Imaginary Magnitude
1 4.98 -2.70 5.66 6.77 -8.14 10.59
5 3.44 -3.04 4.63 5.73 -6.72 9.03
10 1.42 -2.67 3.02 1.72 -5.24 5.51
20 0.52 -1.63 1.71 0.53 -2.94 2.98
30 0.29 -1.22 1.25 0.26 -2.12 2.14
40 0.18 -0.92 0.94 0.17 -1.58 1.59
50 0.13 -0.74 0.75 0.14 -1.24 1.25
60 0.10 -0.63 0.64 0.10 -1.06 1.06
70 0.09 -0.56 0.56 0.09 -0.95 0.95
80 0.07 -0.50 0.50 0.08 -0.86 0.87
90 0.07 -0.46 0.46 0.07 -0.80 0.80
100 0.06 -0.41 0.42 0.07 -0.72 0.72
110 0.06 -0.37 0.38 0.07 -0.65 0.65
120 0.05 -0.34 0.34 0.06 -0.59 0.59
130 0.05 -0.32 0.32 0.06 -0.55 0.55
140 0.04 -0.29 0.30 0.05 -0.50 0.50
150 0.04 -0.27 0.28 0.05 -0.47 0.47
17 www.national.com
LMX2531
1.0 Functional Description
The LMX2531 is a low power, high performance frequency
synthesizer system which includes the PLL, VCO, and par-
tially integrated loop filter. The following sections give a dis-
cussion of the various blocks of this device.
1.1 REFERENCE OSCILLATOR INPUT
Because the VCO frequency calibration algorithm is based on
clocks from the OSCin pin, there are certain bits that need to
be set depending on the OSCin frequency.
XTLSEL (R6[22:20]) and XTLDIV (R7[9:8]) are both need to
be set based on the OSCin frequency, fOSCin. For some op-
tions and for low OSCin frequencies, the
XTLMAN (R7[21:10]) and XTLMAN2 (R8[4]) words need to
be set to the correct value.
1.2 R DIVIDER
The R divider divides the OSCin frequency down to the phase
detector frequency. The R divider value, R, is restricted to the
values of 1, 2, 4, 8, 16, and 32. If R is greater than 8, then this
also puts restrictions on the fractional denominator, FDEN,
than can be used. This is discussed in greater depth in later
sections.
1.3 PHASE DETECTOR AND CHARGE PUMP
The phase detector compares the outputs of the R and N di-
viders and puts out a correction current corresponding to the
phase error. The phase detector frequency, fPD, can be cal-
culated as follows:
fPD = fOSCin / R
Choosing R = 1 yields the highest possible phase detector
frequency and is optimum for phase noise, although there are
restrictions on the maximum phase detector frequency which
could force the R value to be larger. The far out PLL noise
improves 3 dB for every doubling of the phase detector fre-
quency, but at lower offsets, this effect is much less due to
the PLL 1/f noise. Aside from getting the best PLL phase
noise, higher phase detector frequencies also make it easier
to filter the noise that the delta-sigma modulator produces,
which peaks at an offset frequency of fPD/2 from the carrier.
The LMX2531 also has 16 levels of charge pump currents and
a highly flexible fractional modulus. Increasing the charge
pump current improves the phase noise about 3 dB per dou-
bling of the charge pump current, although there are small
diminishing returns as the charge pump current increases.
From a loop filter design and PLL phase noise perspective,
one might think to always design with the highest possible
phase detector frequency and charge pump current. Howev-
er, if one considers the worst case fractional spurs that occur
at an output frequency equal to 1 channel spacing away from
a multiple of the fOSCin, then this gives reason to reconsider.