TPS74801DRCR - TEXAS INSTRUMENTS

December, 2008 − Rev. 4

1Publication Order Number:

MC74LVX4066/D

MC74LVX4066

Quad Analog Switch/

Multiplexer/Demultiplexer

High−Performance Silicon−Gate CMOS

The MC74LVX4066 utilizes silicon−gate CMOS technology to

achieve fast propagation delays, low ON resistances, and low

OFF−channel leakage current. This bilateral switch/multiplexer/

demultiplexer controls analog and digital voltages that may vary

across the full power−supply range (from VCC to GND).

The LVX4066 is identical in pinout to the metal−gate CMOS

MC14066 and the high−speed CMOS HC4066A. Each device has four

independent switches. The device has been designed so that the ON

resistances (RON) are much more linear over input voltage than RON

of metal−gate CMOS analog switches.

The ON/OFF control inputs are compatible with standard CMOS

outputs; with pull−up resistors, they are compatible with LSTTL

outputs.

Features

•Fast Switching and Propagation Speeds

•High ON/OFF Output Voltage Ratio

•Low Crosstalk Between Switches

•Diode Protection on All Inputs/Outputs

•Wide Power−Supply Voltage Range (VCC − GND) = 2.0 to 6.0 Volts

•Analog Input Voltage Range (VCC − GND) = 2.0 to 6.0 Volts

•Improved Linearity and Lower ON Resistance over Input Voltage

than the MC14016 or MC14066

•Low Noise

•Chip Complexity: 44 FETs or 11 Equivalent Gates

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

MARKING

DIAGRAMS

A = Assembly

Location

WL, L = Wafer Lot

Y = Year

WW, W = Work Week

G or G= Pb−Free Package

TSSOP−14

DT SUFFIX

CASE 948G

14

1

SOEIAJ−14

M SUFFIX

CASE 965

SOIC−14

D SUFFIX

CASE 751A

14

1

14

LVX4066

ALYWG

14

1

See detailed ordering and shipping information in the package

dimensions section on page 2 of this data sheet.

ORDERING INFORMATION

1

14

http://onsemi.com

LVX

4066

ALYWG

G

1

14

LVX4066G

AWLYWW

(Note: Microdot may be in either location)

MC74LVX4066

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2

LOGIC DIAGRAM

XAYA

12

A ON/OFF CONTROL 13

XBYB

43

B ON/OFF CONTROL 5

XCYC

89

C ON/OFF CONTROL 6

XDYD

11 10

D ON/OFF CONTROL 12

ANALOG

OUTPUTS/INPUTS

ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD

PIN 14 = VCC

PIN 7 = GND

PIN CONNECTION (Top View)

11

12

13

14

8

9

105

4

3

2

1

7

6

YD

XD

D ON/OFF

CONTROL

A ON/OFF

CONTROL

VCC

XC

YC

XB

YB

YA

XA

GND

C ON/OFF

CONTROL

B ON/OFF

CONTROL

FUNCTION TABLE

On/Off Control

Input

Off

On

L

H

State of

Analog Switch

ORDERING INFORMATION

Device Package Shipping†

MC74LVX4066DR2 SOIC−14 2500 Tape & Reel

MC74LVX4066DR2G SOIC−14

(Pb−Free)

2500 Tape & Reel

MC74LVX4066DTR2 TSSOP−14* 2500 Tape & Reel

MC74LVX4066DTR2G TSSOP−14*

(Pb−Free)

2500 Tape & Reel

MC74LVX4066M SOEIAJ−14 50 Units / Rail

MC74LVX4066MG SOEIAJ−14

(Pb−Free)

50 Units / Rail

MC74LVX4066MEL SOEIAJ−14 2000 Tape & Reel

MC74LVX4066MELG SOEIAJ−14

(Pb−Free)

2000 Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74LVX4066

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Into or Out of ON/OFF Control Pins

ÎÎÎÎÎ

± 20

ÎÎÎ

mA

ÎÎÎÎ

Is

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Current Into or Out of Switch Pins

ÎÎÎÎÎ

± 20

ÎÎÎ

mA

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

500

450

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

ÎÎÎÎ

TL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

ÎÎÎÎÎ

260

ÎÎÎ

_C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress

ratings only. Functional operation above the Recommended Operating Conditions is not

implied. Extended exposure to stresses above the Recommended Operating Conditions may

affect device reliability.

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Positive DC Supply Voltage (Referenced to GND)

ÎÎÎ

2.0

ÎÎÎ

6.0

ÎÎÎ

V

ÎÎÎÎ

VIS

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Analog Input Voltage (Referenced to GND)

ÎÎÎ

GND

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Digital Input Voltage (Referenced to GND)

ÎÎÎ

GND

ÎÎÎ

VCC

ÎÎÎ

V

ÎÎÎÎ

VIO*

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Static or Dynamic Voltage Across Switch

ÎÎÎ

−

ÎÎÎ

1.2

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 85

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time, ON/OFF Control

Inputs (Figure 10) VCC = 3.3 V ± 0.3 V

VCC = 5.0 V ± 0.5 V

ÎÎÎ

0

ÎÎÎ

100

20

ÎÎÎ

ns/V

*For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may

be drawn; i.e., the current out of the switch may contain both VCC and switch input

components. The reliability of the device will be unaffected unless the Maximum Ratings are

exceeded.

DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Voltage

ON/OFF Control Inputs (Note 1)

ÎÎÎÎÎÎÎÎ

Ron = Per Spec

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎÎÎ

1.5

2.1

3.15

3.85

ÎÎÎÎ

1.5

2.1

3.15

3.85

ÎÎÎÎÎ

1.5

2.1

3.15

3.85

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Voltage

ON/OFF Control Inputs (Note 1)

ÎÎÎÎÎÎÎÎ

Ron = Per Spec

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎÎÎ

0.5

0.9

1.35

1.65

ÎÎÎÎ

0.5

0.9

1.35

1.65

ÎÎÎÎÎ

0.5

0.9

1.35

1.65

ÎÎ

V

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ON/OFF Control Inputs

ÎÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5V

ÎÎÎÎÎ

± 0.1

ÎÎÎÎ

± 1.0

ÎÎÎÎÎ

± 1.0

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply

Current (per Package)

ÎÎÎÎÎÎÎÎ

Vin = VCC or GND VIO = 0 V

ÎÎÎ

5.5

ÎÎÎÎÎ

4.0

ÎÎÎÎ

40

ÎÎÎÎÎ

160

ÎÎ

mA

1. Specifications are for design target only. Not final specification limits.

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

I/O pins must be connected to a

properly terminated line or bus.

MC74LVX4066

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4

DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

Ron

ÎÎÎÎÎÎÎÎÎ

Maximum “ON” Resistance

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC to GND

|IS| v 10 mA (Figures 1, 2)

ÎÎÎ

2.0†

3.0

4.5

5.5

ÎÎÎÎÎ

−

40

25

20

ÎÎÎÎ

−

45

30

25

ÎÎÎÎÎ

−

50

35

30

ÎÎ

W

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or GND

(Endpoints)

|IS| v 10 mA (Figures 1, 2)

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎÎÎ

−

30

25

20

ÎÎÎÎ

−

35

30

25

ÎÎÎÎÎ

−

40

35

30

ÎÎÎÎ

DRon

ÎÎÎÎÎÎÎÎÎ

Maximum Difference in “ON”

Resistance Between Any Two

Channels in the Same Package

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = 1/2 (VCC − GND)

IS v 2.0 mA

ÎÎÎ

3.0

4.5

5.5

ÎÎÎÎÎ

15

10

ÎÎÎÎ

20

12

ÎÎÎÎÎ

25

15

ÎÎ

W

ÎÎÎÎ

Ioff

ÎÎÎÎÎÎÎÎÎ

Maximum Off−Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎ

Vin = VIL

VIO = VCC or GND

Switch Off (Figure 3)

ÎÎÎ

5.5

ÎÎÎÎÎ

0.1

ÎÎÎÎ

0.5

ÎÎÎÎÎ

1.0

ÎÎ

mA

ÎÎÎÎ

Ion

ÎÎÎÎÎÎÎÎÎ

Maximum On−Channel Leakage

Current, Any One Channel

ÎÎÎÎÎÎÎÎ

Vin = VIH

VIS = VCC or GND (Figure 4)

ÎÎÎ

5.5

ÎÎÎÎÎ

0.1

ÎÎÎÎ

0.5

ÎÎÎÎÎ

1.0

ÎÎ

mA

†At supply voltage (VCC) approaching 2 V the analog switch−on resistance becomes extremely non−linear. Therefore, for low−voltage operation,

it is recommended that these devices only be used to control digital signals (See Figure 1a).

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎÎÎÎÎÎ

Guaranteed Limit

ÎÎ

Unit

ÎÎÎÎÎ

– 55 to 25_C

ÎÎÎÎ

v 85_C

ÎÎÎÎÎ

v 125_C

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, Analog Input to Analog Output

(Figures 8 and 9)

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎÎÎ

4.0

3.0

1.0

ÎÎÎÎ

6.0

5.0

2.0

ÎÎÎÎÎ

8.0

6.0

2.0

ÎÎ

ns

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 11)

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎÎÎ

30

20

15

ÎÎÎÎ

35

25

18

ÎÎÎÎÎ

40

30

22

20

ÎÎ

ns

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay, ON/OFF Control to Analog Output

(Figures 10 and 1 1)

ÎÎÎ

2.0

3.0

4.5

5.5

ÎÎÎÎÎ

20

12

8.0

ÎÎÎÎ

25

14

10

ÎÎÎÎÎ

30

15

12

ÎÎ

ns

ÎÎÎÎ

C

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Maximum Capacitance ON/OFF Control Input

ÎÎÎ

−

ÎÎÎÎÎ

10

ÎÎÎÎ

10

ÎÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Control Input = GND

Analog I/O

Feedthrough

ÎÎÎ

−

ÎÎÎÎÎ

35

1.0

ÎÎÎÎ

35

1.0

ÎÎÎÎÎ

35

1.0

CPD Power Dissipation Capacitance (Per Switch) (Figure 13)*

Typical @ 25°C, VCC = 5.0 V

pF

15

* Used to determine the no−load dynamic power consumption: PD = CPD VCC2f + ICC VCC.

MC74LVX4066

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5

ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted)

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

VCC

V

ÎÎÎÎ

Limit*

25_C

ÎÎ

Unit

ÎÎÎÎ

BW

ÎÎÎÎÎÎÎÎÎÎÎ

Maximum On−Channel Bandwidth or

Minimum Frequency Response (Figure 5)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 MHz Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VOS

Increase fin Frequency Until dB Meter Reads – 3 dB

RL = 50 W, CL = 10 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

150

160

ÎÎ

MHz

ÎÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎÎ

Off−Channel Feedthrough Isolation

(Figure 6)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin  Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 W, CL = 50 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

− 50

ÎÎ

dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 W, CL = 10 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

− 37

ÎÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎÎ

Feedthrough Noise, Control to Switch

(Figure 7)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Vin v 1 MHz Square Wave (tr = tf = 6 ns)

Adjust RL at Setup so that IS = 0 A

RL = 600 W, CL = 50 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

100

200

ÎÎ

mVPP

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

RL = 10 kW, CL = 10 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

50

100

ÎÎÎÎ

−

ÎÎÎÎÎÎÎÎÎÎÎ

Crosstalk Between Any Two Switches

(Figure 12)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin  Sine Wave

Adjust fin Voltage to Obtain 0 dBm at VIS

fin = 10 kHz, RL = 600 W, CL = 50 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

– 70

ÎÎ

dB

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1.0 MHz, RL = 50 W, CL = 10 pF

ÎÎÎ

4.5

5.5

ÎÎÎÎ

– 80

ÎÎÎÎ

THD

ÎÎÎÎÎÎÎÎÎÎÎ

Total Harmonic Distortion (Figure 14)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

fin = 1 kHz, RL = 10 kW, CL = 50 pF

THD = THDMeasured − THDSource

VIS = 4.0 VPP sine wave

VIS = 5.0 VPP sine wave

ÎÎÎ

4.5

5.5

ÎÎÎÎ

0.10

0.06

ÎÎ

%

*Guaranteed limits not tested. Determined by design and verified by qualification.

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6

Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25°C Figure 1b. Typical On Resistance, VCC = 2.0 V

Figure 1c. Typical On Resistance, VCC = 3.0 V

Figure 2. On Resistance Test Set−Up

PLOTTER

MINI COMPUTER

PROGRAMMABLE

POWER

SUPPLY

DC ANALYZER

VCC

+-

ANALOG IN COMMON OUT

GND

DEVICE

UNDER TEST

Figure 1d. Typical On Resistance, VCC = 4.5 V

Figure 1e. Typical On Resistance, VCC = 5.5 V

350

Ron (Ohms)

Vin (Volts)

250

150

50

0

0.5 1

300

200

100

1.5 2 2.50

400

125°C

-55°C

25°C

85°C

35

Ron (Ohms)

Vin (Volts)

25

15

5

0

1

30

20

10

20

125°C

-55°C

25°C

85°C

3

14

Ron (Ohms)

Vin (Volts)

10

6

2

0

12

8

4

3450

125°C

-55°C

25°C

85°C

18

16

14

Ron (Ohms)

Vin (Volts)

10

6

2

0

12

8

4

3450

125°C

-55°C

25°C

85°C

16

6

Ron (Ohms)

Vin (Volts)

250

150

50

00.5 1

200

100

1.5 2 2.50

Is = 1mA

Is = 9mA

Is = 5mA

Is = 15mA

20

18

4

MC74LVX4066

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7

Figure 3. Maximum Off Channel Leakage Current,

Any One Channel, Test Set−Up

OFF

7

14

VCC

A

VCC

GND

VCC

SELECTED

CONTROL

INPUT

VIL

Figure 4. Maximum On Channel Leakage Current,

Test Set−Up

ON

14

VCC

N/C

A

GND

VCC

7

SELECTED

CONTROL

INPUT

VIH

Figure 5. Maximum On−Channel Bandwidth

Test Set−Up

ON

14

VCC

0.1mFCL*

fin dB

METER

*Includes all probe and jig capacitance.

VOS

7

SELECTED

CONTROL

INPUT

VCC

Figure 6. Off−Channel Feedthrough Isolation,

Test Set−Up

OFF

7

14

VCC

0.1mFCL*

fin dB

METER

*Includes all probe and jig capacitance.

VOS

RL

VIS

SELECTED

CONTROL

INPUT

Figure 7. Feedthrough Noise, ON/OFF Control to

Analog Out, Test Set−Up

14

VCC

CL*

*Includes all probe and jig capacitance.

OFF/ON

VCC

GND

Vin ≤1 MHz

tr = tf = 3 ns

CONTROL

VCC/2

RL

IS

RLVOS

7

SELECTED

CONTROL

INPUT

VCC/2

VCC

GND

ANALOG IN

ANALOG OUT 50%

tPLH tPHL

50%

Figure 8. Propagation Delays, Analog In to

Analog Out

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8

POSITIONWHEN TESTING tPLZ AND tPZL

Figure 9. Propagation Delay Test Set−Up

ON

14

VCC

*Includes all probe and jig capacitance.

TEST

POINT

ANALOG OUTANALOG IN

CL*

7

SELECTED

CONTROL

INPUT

VCC

trtf

VCC

GND

HIGH

IMPEDANCE

VOL

VOH

HIGH

IMPEDANCE

CONTROL

ANALOG

OUT

90%

50%

10%

50%

10%

90%

tPZH tPHZ

tPZL tPLZ

Figure 10. Propagation Delay, ON/OFF Control

to Analog Out

ON/OFF

VCC

TEST

POINT

14

VCC

1 kW

POSITIONWHEN TESTING tPHZ AND tPZH

CL*

1

2

1

2

Figure 11. Propagation Delay Test Set−Up

1

2

7

SELECTED

CONTROL

INPUT

Figure 12. Crosstalk Between Any Two Switches,

Test Set−Up

RL

ON

14

VCC OR GND CL*

*Includes all probe and jig capacitance.

OFF

RL

VIS

RLCL*

VOS

fin

0.1 mF

VCC/2 VCC/2

7

SELECTED

CONTROL

INPUT

VCC/2

Figure 13. Power Dissipation Capacitance

Test Set−Up

14

VCC

N/C

OFF/ON

A

N/C

7

SELECTED

CONTROL

INPUT

ON/OFF CONTROL

ON

VCC

0.1 mF

CL*

fin

RL

TO

DISTORTION

METER

*Includes all probe and jig capacitance.

VOS

VIS

7

SELECTED

CONTROL

INPUT

VCC

Figure 14. Total Harmonic Distortion, Test Set−Up

*Includes all probe and jig capacitance.

VCC

VCC/2

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9

0

-10

-20

-30

-40

-50

1.0 2.0

FREQUENCY (kHz)

dBm

-60

-70

-80

-90

FUNDAMENTAL FREQUENCY

DEVICE

SOURCE

Figure 15. Plot, Harmonic Distortion

3.0

APPLICATION INFORMATION

The ON/OFF Control pins should be at VCC or GND logic

levels, VCC being recognized as logic high and GND being

recognized as a logic low. Unused analog inputs/outputs

may be left floating (not connected). However, it is

advisable to tie unused analog inputs and outputs to VCC or

GND through a low value resistor. This minimizes crosstalk

and feedthrough noise that may be picked−up by the unused

I/O pins.

The maximum analog voltage swings are determined by

the supply voltages VCC and GND. The positive peak analog

voltage should not exceed VCC. Similarly, the negative peak

analog voltage should not go below GND. In the example

below, the difference between VCC and GND is six volts.

Therefore, using the configuration in Figure 16, a maximum

analog signal of six volts peak−to−peak can be controlled.

When voltage transients above VCC and/or below GND

are anticipated on the analog channels, external diodes (Dx)

are recommended as shown in Figure 17. These diodes

should be small signal, fast turn−on types able to absorb the

maximum anticipated current surges during clipping. An

alternate method would be to replace the Dx diodes with

Mosorbs (Mosorb™ is an acronym for high current surge

protectors). Mosorbs are fast turn−on devices ideally suited

for precise DC protection with no inherent wear out

mechanism.

ANALOG O/I

ON

14

VCC = 6.0 V

ANALOG I/O

+ 6.0 V

0 V

+ 6.0 V

0 V

OTHER CONTROL

INPUTS

(VCC OR GND)

ON

16

VCC

Dx

VCC

Dx

Figure 16. 6.0 V Application Figure 17. Transient Suppressor Application

7

SELECTED

CONTROL

INPUT

Dx

OTHER CONTROL

INPUTS

(VCC OR GND)

7

SELECTED

CONTROL

INPUT

VCC

MC74LVX4066

http://onsemi.com

10

+5 V

14

LVX4066

CONTROL

INPUTS

7

5

6

14

15

LSTTL/

NMOS

ANALOG

SIGNALS

R* R* R* R*

ANALOG

SIGNALS

R* = 2 TO 10 kW

VDD = 5 V VCC = 2.0 TO 7.0 V

ANALOG

SIGNALS

ANALOG

SIGNALS

116 14

CONTROL

INPUTS

78

MC14504

13

3

5

7

9

11

14

2

4

6

10

5

6

14

15

CHANNEL 4

CHANNEL 3

CHANNEL 2

CHANNEL 1

1 OF 4

SWITCHES

COMMON I/O

1234

CONTROL INPUTS

INPUT

OUTPUT

0.01 mF

LF356 OR

EQUIVALENT

a. Using Pull-Up Resistors b. Using LVXT4066

Figure 18. LSTTL/NMOS to CMOS Interface

Figure 19. TTL/NMOS−to−CMOS Level Converter

Analog Signal Peak−to−Peak Greater than 5 V

Figure 20. 4−Input Multiplexer Figure 21. Sample/Hold Amplifier

+

-

1 OF 4

SWITCHES

+5 V

14

CONTROL

INPUTS

7

5

6

14

15

LSTTL/

NMOS/

ABT/

ALS

ANALOG

SIGNALS

ANALOG

SIGNALS

1 OF 4

SWITCHES

1 OF 4

SWITCHES

1 OF 4

SWITCHES

LVXT4066

LVX4066

MC74LVX4066

http://onsemi.com

11

PACKAGE DIMENSIONS

SOIC−14

D SUFFIX

CASE 751A−03

ISSUE J NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.127

(0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

−A−

−B−

G

P7 PL

14 8

7

1

M

0.25 (0.010) B M

S

B

M

0.25 (0.010) A S

T

−T−

F

RX 45

SEATING

PLANE D14 PL K

C

J

M

_DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A8.55 8.75 0.337 0.344

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.228 0.244

R0.25 0.50 0.010 0.019

__ __

7.04

14X

0.58

14X

1.52

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

7X

MC74LVX4066

http://onsemi.com

12

PACKAGE DIMENSIONS

TSSOP−14

DT SUFFIX

CASE 948G−01

ISSUE B

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.50 0.60 0.020 0.024

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

S

U0.15 (0.006) T

2X L/2

S

U

M

0.10 (0.004) V S

T

L−U−

SEATING

PLANE

0.10 (0.004)

−T−

ÇÇÇ

SECTION N−N

DETAIL E

JJ1

K

K1

ÉÉÉ

DETAIL E

F

M

−W−

0.25 (0.010)

8

14

7

1

PIN 1

IDENT.

H

G

A

D

C

B

S

U0.15 (0.006) T

−V−

14X REFK

N

7.06

14X

0.36 14X

1.26

0.65

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

MC74LVX4066

http://onsemi.com

13

PACKAGE DIMENSIONS

SOEIAJ−14

M SUFFIX

CASE 965−01

ISSUE B

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.004 0.008

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 1.42 --- 0.056

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

0.13 (0.005) M0.10 (0.004)

D

Z

E

1

14 8

7

eA

b

VIEW P

c

L

DETAIL P

M

A

b

c

D

E

e

L

M

Z

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

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MC74LVX4066/D

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