MC74LVX4066 Quad Analog Switch/ Multiplexer/Demultiplexer High-Performance Silicon-Gate CMOS The MC74LVX4066 utilizes silicon-gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF-channel leakage current. This bilateral switch/multiplexer/ demultiplexer controls analog and digital voltages that may vary across the full power-supply range (from VCC to GND). The LVX4066 is identical in pinout to the metal-gate CMOS MC14066 and the high-speed CMOS HC4066A. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal-gate CMOS analog switches. The ON/OFF control inputs are compatible with standard CMOS outputs; with pull-up resistors, they are compatible with LSTTL outputs. Features * * * * * * * * * * Fast Switching and Propagation Speeds High ON/OFF Output Voltage Ratio Low Crosstalk Between Switches Diode Protection on All Inputs/Outputs Wide Power-Supply Voltage Range (VCC - GND) = 2.0 to 6.0 Volts Analog Input Voltage Range (VCC - GND) = 2.0 to 6.0 Volts Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066 Low Noise Chip Complexity: 44 FETs or 11 Equivalent Gates Pb-Free Packages are Available* http://onsemi.com MARKING DIAGRAMS 14 SOIC-14 D SUFFIX CASE 751A 14 1 LVX4066G AWLYWW 1 14 14 1 LVX 4066 ALYWG G TSSOP-14 DT SUFFIX CASE 948G 1 14 LVX4066 ALYWG SOEIAJ-14 M SUFFIX CASE 965 14 1 1 A = Assembly Location WL, L = Wafer Lot Y = Year WW, W = Work Week G orMicrodot G = Pb-Free (Note: may be inPackage either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2008 December, 2008 - Rev. 4 1 Publication Order Number: MC74LVX4066/D MC74LVX4066 LOGIC DIAGRAM 1 XA 2 YA PIN CONNECTION (Top View) 13 A ON/OFF CONTROL 4 XB 3 YB ANALOG OUTPUTS/INPUTS 5 B ON/OFF CONTROL 8 XC 9 YC 6 C ON/OFF CONTROL 11 XD 12 D ON/OFF CONTROL 10 XA 1 14 YA 2 13 YB 3 12 XB B ON/OFF CONTROL C ON/OFF CONTROL GND 4 11 VCC A ON/OFF CONTROL D ON/OFF CONTROL XD 5 10 YD 6 9 YC 7 8 XC YD ANALOG INPUTS/OUTPUTS = XA, XB, XC, XD PIN 14 = VCC PIN 7 = GND FUNCTION TABLE On/Off Control Input State of Analog Switch L H Off On ORDERING INFORMATION Package Shipping MC74LVX4066DR2 SOIC-14 2500 Tape & Reel MC74LVX4066DR2G SOIC-14 (Pb-Free) 2500 Tape & Reel MC74LVX4066DTR2 TSSOP-14* 2500 Tape & Reel MC74LVX4066DTR2G TSSOP-14* (Pb-Free) 2500 Tape & Reel MC74LVX4066M SOEIAJ-14 50 Units / Rail MC74LVX4066MG SOEIAJ-14 (Pb-Free) 50 Units / Rail MC74LVX4066MEL SOEIAJ-14 2000 Tape & Reel MC74LVX4066MELG SOEIAJ-14 (Pb-Free) 2000 Tape & Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 2 MC74LVX4066 IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS Symbol Parameter Value Unit - 0.5 to + 7.0 V V VCC Positive DC Supply Voltage (Referenced to GND) VIS Analog Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 Vin Digital Input Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V Iin DC Current Into or Out of ON/OFF Control Pins 20 mA Is DC Current Into or Out of Switch Pins 20 mA PD Power Dissipation in Still Air, 500 450 mW Tstg Storage Temperature - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds 260 _C SOIC Package TSSOP Package Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating -- SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V CC ). Unused outputs must be left open. I/O pins must be connected to a properly terminated line or bus. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC Positive DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIS Analog Input Voltage (Referenced to GND) GND VCC V Vin Digital Input Voltage (Referenced to GND) GND VCC V VIO* Static or Dynamic Voltage Across Switch TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time, ON/OFF Control Inputs (Figure 10) VCC = 3.3 V 0.3 V VCC = 5.0 V 0.5 V - 1.2 V - 55 + 85 _C 0 0 100 20 ns/V *For voltage drops across the switch greater than 1.2 V (switch on), excessive VCC current may be drawn; i.e., the current out of the switch may contain both VCC and switch input components. The reliability of the device will be unaffected unless the Maximum Ratings are exceeded. IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIII IIIIIIIII IIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII DC ELECTRICAL CHARACTERISTIC Digital Section (Voltages Referenced to GND) VCC V Guaranteed Limit Symbol Parameter - 55 to 25_C v 85_C v 125_C Unit VIH Minimum High-Level Voltage ON/OFF Control Inputs (Note 1) Ron = Per Spec 2.0 3.0 4.5 5.5 1.5 2.1 3.15 3.85 1.5 2.1 3.15 3.85 1.5 2.1 3.15 3.85 V VIL Maximum Low-Level Voltage ON/OFF Control Inputs (Note 1) Ron = Per Spec 2.0 3.0 4.5 5.5 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 0.5 0.9 1.35 1.65 V Iin Maximum Input Leakage Current ON/OFF Control Inputs Vin = VCC or GND 5.5V 0.1 1.0 1.0 mA ICC Maximum Quiescent Supply Current (per Package) Vin = VCC or GND VIO = 0 V 5.5 4.0 40 160 mA Test Conditions 1. Specifications are for design target only. Not final specification limits. http://onsemi.com 3 MC74LVX4066 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIII IIIIIIIII IIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIII II IIIIIIII III IIIII IIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIII IIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIII IIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII DC ELECTRICAL CHARACTERISTICS Analog Section (Voltages Referenced to GND) Symbol Ron - 55 to 25_C v 85_C v 125_C Unit Vin = VIH VIS = VCC to GND |IS| v 10 mA (Figures 1, 2) 2.0 3.0 4.5 5.5 - 40 25 20 - 45 30 25 - 50 35 30 W Vin = VIH VIS = VCC or GND (Endpoints) |IS| v 10 mA (Figures 1, 2) 2.0 3.0 4.5 5.5 - 30 25 20 - 35 30 25 - 40 35 30 Parameter Test Conditions Maximum "ON" Resistance Guaranteed Limit VCC V DRon Maximum Difference in "ON" Resistance Between Any Two Channels in the Same Package Vin = VIH VIS = 1/2 (VCC - GND) IS v 2.0 mA 3.0 4.5 5.5 15 10 10 20 12 12 25 15 15 W Ioff Maximum Off-Channel Leakage Current, Any One Channel Vin = VIL VIO = VCC or GND Switch Off (Figure 3) 5.5 0.1 0.5 1.0 mA Ion Maximum On-Channel Leakage Current, Any One Channel Vin = VIH VIS = VCC or GND (Figure 4) 5.5 0.1 0.5 1.0 mA At supply voltage (VCC) approaching 2 V the analog switch-on resistance becomes extremely non-linear. Therefore, for low-voltage operation, it is recommended that these devices only be used to control digital signals (See Figure 1a). IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII IIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIII III IIIII IIII IIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII II IIIIIIIIIIIIIIII III IIIII IIII IIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, ON/OFF Control Inputs: tr = tf = 6 ns) Symbol Parameter Guaranteed Limit VCC V - 55 to 25_C v 85_C v 125_C Unit tPLH, tPHL Maximum Propagation Delay, Analog Input to Analog Output (Figures 8 and 9) 2.0 3.0 4.5 5.5 4.0 3.0 1.0 1.0 6.0 5.0 2.0 2.0 8.0 6.0 2.0 2.0 ns tPLZ, tPHZ Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 11) 2.0 3.0 4.5 5.5 30 20 15 15 35 25 18 18 40 30 22 20 ns tPZL, tPZH Maximum Propagation Delay, ON/OFF Control to Analog Output (Figures 10 and 1 1) 2.0 3.0 4.5 5.5 20 12 8.0 8.0 25 14 10 10 30 15 12 12 ns ON/OFF Control Input - 10 10 10 pF Control Input = GND Analog I/O Feedthrough - - 35 1.0 35 1.0 35 1.0 C Maximum Capacitance Typical @ 25C, VCC = 5.0 V CPD 15 Power Dissipation Capacitance (Per Switch) (Figure 13)* * Used to determine the no-load dynamic power consumption: P D = CPD VCC http://onsemi.com 4 2f + ICC VCC . pF MC74LVX4066 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIIIIIIIIIII III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIIIIIIIIIII III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIIIIIIIIIII III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIII IIIIIII IIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIII IIIIIIIIIIIIII III IIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII ADDITIONAL APPLICATION CHARACTERISTICS (Voltages Referenced to GND Unless Noted) VCC V Limit* 25_C fin = 1 MHz Sine Wave Adjust fin Voltage to Obtain 0 dBm at VOS Increase fin Frequency Until dB Meter Reads - 3 dB RL = 50 W, CL = 10 pF 4.5 5.5 150 160 MHz fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 4.5 5.5 - 50 - 50 dB fin = 1.0 MHz, RL = 50 W, CL = 10 pF 4.5 5.5 - 37 - 37 Vin v 1 MHz Square Wave (tr = tf = 6 ns) Adjust RL at Setup so that IS = 0 A RL = 600 W, CL = 50 pF 4.5 5.5 100 200 RL = 10 kW, CL = 10 pF 4.5 5.5 50 100 fin Sine Wave Adjust fin Voltage to Obtain 0 dBm at VIS fin = 10 kHz, RL = 600 W, CL = 50 pF 4.5 5.5 - 70 - 70 fin = 1.0 MHz, RL = 50 W, CL = 10 pF 4.5 5.5 - 80 - 80 Symbol Parameter Test Conditions BW Maximum On-Channel Bandwidth or Minimum Frequency Response (Figure 5) Off-Channel Feedthrough Isolation (Figure 6) - - - THD Feedthrough Noise, Control to Switch (Figure 7) Crosstalk Between Any Two Switches (Figure 12) Total Harmonic Distortion (Figure 14) fin = 1 kHz, RL = 10 kW, CL = 50 pF THD = THDMeasured - THDSource VIS = 4.0 VPP sine wave VIS = 5.0 VPP sine wave *Guaranteed limits not tested. Determined by design and verified by qualification. http://onsemi.com 5 Unit mVPP dB % 4.5 5.5 0.10 0.06 MC74LVX4066 400 250 350 Is = 1mA 200 -55C 300 Ron (Ohms) Ron (Ohms) 25C 150 Is = 5mA 100 Is = 9mA 250 200 85C 150 125C 100 50 50 0 Is = 15mA 0 0.5 1 1.5 2 0 0 2.5 0.5 1.5 1 Vin (Volts) 2 Vin (Volts) Figure 1a. Typical On Resistance, VCC = 2.0 V, T = 25C Figure 1b. Typical On Resistance, VCC = 2.0 V 35 20 18 30 16 25 12 125C 85C 25C 10 -55C 14 20 Ron (Ohms) Ron (Ohms) 2.5 125C 85C 25C -55C 15 10 8 6 4 5 2 0 0 2 1 3 0 4 1 0 2 3 4 Vin (Volts) Vin (Volts) Figure 1c. Typical On Resistance, VCC = 3.0 V Figure 1d. Typical On Resistance, VCC = 4.5 V 18 PLOTTER 16 125C 85C 25C 14 Ron (Ohms) 12 10 -55C 8 PROGRAMMABLE POWER SUPPLY - MINI COMPUTER + DC ANALYZER VCC DEVICE UNDER TEST 6 4 2 ANALOG IN COMMON OUT 0 0 1 2 3 4 5 6 GND Vin (Volts) Figure 2. On Resistance Test Set-Up Figure 1e. Typical On Resistance, VCC = 5.5 V http://onsemi.com 6 5 MC74LVX4066 VCC VCC VCC VCC 14 GND 14 A A VCC OFF 7 SELECTED CONTROL INPUT VIL 7 Figure 3. Maximum Off Channel Leakage Current, Any One Channel, Test Set-Up VCC VIS 14 VIH VOS 14 ON 0.1mF CL* 7 SELECTED CONTROL INPUT Figure 4. Maximum On Channel Leakage Current, Test Set-Up VOS VCC fin N/C ON GND SELECTED CONTROL INPUT fin dB METER OFF 0.1mF CL* RL dB METER SELECTED CONTROL INPUT VCC 7 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 5. Maximum On-Channel Bandwidth Test Set-Up VCC VCC/2 Figure 6. Off-Channel Feedthrough Isolation, Test Set-Up VCC/2 14 RL RL OFF/ON VOS IS VCC CL* VCC GND Vin 1 MHz tr = tf = 3 ns 7 ANALOG IN SELECTED CONTROL INPUT 50% GND tPHL tPLH CONTROL 50% ANALOG OUT *Includes all probe and jig capacitance. Figure 7. Feedthrough Noise, ON/OFF Control to Analog Out, Test Set-Up Figure 8. Propagation Delays, Analog In to Analog Out http://onsemi.com 7 MC74LVX4066 VCC tr tf 14 ANALOG IN ANALOG OUT ON TEST POINT VCC 90% 50% 10% CONTROL GND CL* 7 SELECTED CONTROL INPUT tPZL tPLZ HIGH IMPEDANCE 50% VCC ANALOG OUT tPZH Figure 9. Propagation Delay Test Set-Up VOH HIGH IMPEDANCE VIS VCC 2 POSITIONWHEN TESTING tPLZ AND tPZL 14 RL 2 VCC fin 1 0.1 mF TEST POINT ON/OFF VOS ON 1 kW 14 2 90% tPHZ Figure 10. Propagation Delay, ON/OFF Control to Analog Out 1 POSITIONWHEN TESTING tPHZ AND tPZH VCC VOL 50% *Includes all probe and jig capacitance. 1 10% OFF VCC OR GND CL* RL RL SELECTED CONTROL INPUT SELECTED CONTROL INPUT CL* VCC/2 RL CL* VCC/2 7 7 VCC/2 *Includes all probe and jig capacitance. *Includes all probe and jig capacitance. Figure 11. Propagation Delay Test Set-Up Figure 12. Crosstalk Between Any Two Switches, Test Set-Up VCC A VIS VCC 14 N/C OFF/ON VOS 0.1 mF N/C fin ON RL 7 CL* TO DISTORTION METER VCC/2 SELECTED CONTROL INPUT 7 SELECTED CONTROL INPUT VCC ON/OFF CONTROL *Includes all probe and jig capacitance. Figure 13. Power Dissipation Capacitance Test Set-Up Figure 14. Total Harmonic Distortion, Test Set-Up http://onsemi.com 8 MC74LVX4066 0 -10 FUNDAMENTAL FREQUENCY -20 dBm -30 -40 -50 DEVICE -60 SOURCE -70 -80 -90 1.0 3.0 2.0 FREQUENCY (kHz) Figure 15. Plot, Harmonic Distortion APPLICATION INFORMATION The ON/OFF Control pins should be at VCC or GND logic levels, VCC being recognized as logic high and GND being recognized as a logic low. Unused analog inputs/outputs may be left floating (not connected). However, it is advisable to tie unused analog inputs and outputs to VCC or GND through a low value resistor. This minimizes crosstalk and feedthrough noise that may be picked-up by the unused I/O pins. The maximum analog voltage swings are determined by the supply voltages VCC and GND. The positive peak analog voltage should not exceed VCC. Similarly, the negative peak analog voltage should not go below GND. In the example below, the difference between VCC and GND is six volts. Therefore, using the configuration in Figure 16, a maximum analog signal of six volts peak-to-peak can be controlled. When voltage transients above VCC and/or below GND are anticipated on the analog channels, external diodes (Dx) are recommended as shown in Figure 17. These diodes should be small signal, fast turn-on types able to absorb the maximum anticipated current surges during clipping. An alternate method would be to replace the Dx diodes with Mosorbs (MosorbTM is an acronym for high current surge protectors). Mosorbs are fast turn-on devices ideally suited for precise DC protection with no inherent wear out mechanism. VCC VCC = 6.0 V + 6.0 V 14 ANALOG I/O ON ANALOG O/I Dx + 6.0 V SELECTED CONTROL INPUT 7 16 Dx ON 0V 0V VCC Dx VCC OTHER CONTROL INPUTS (VCC OR GND) Dx SELECTED CONTROL INPUT 7 Figure 16. 6.0 V Application OTHER CONTROL INPUTS (VCC OR GND) Figure 17. Transient Suppressor Application http://onsemi.com 9 MC74LVX4066 +5 V +5 V 14 ANALOG SIGNALS R* R* R* R* LVX4066 LSTTL/ NMOS 6 CONTROL INPUTS 15 ANALOG SIGNALS LVXT4066 LSTTL/ NMOS/ ABT/ ALS 5 14 14 ANALOG SIGNALS ANALOG SIGNALS 5 6 14 CONTROL INPUTS 15 7 7 R* = 2 TO 10 kW a. Using Pull-Up Resistors b. Using LVXT4066 Figure 18. LSTTL/NMOS to CMOS Interface VDD = 5 V 13 1 VCC = 2.0 TO 7.0 V 16 14 ANALOG SIGNALS 3 LVX4066 5 7 ANALOG SIGNALS MC14504 2 5 9 4 6 11 6 14 CONTROL INPUTS 10 15 7 14 8 Figure 19. TTL/NMOS-to-CMOS Level Converter Analog Signal Peak-to-Peak Greater than 5 V CHANNEL 4 1 OF 4 SWITCHES CHANNEL 3 1 OF 4 SWITCHES CHANNEL 2 1 OF 4 SWITCHES CHANNEL 1 1 OF 4 SWITCHES COMMON I/O INPUT 1 OF 4 SWITCHES + OUTPUT LF356 OR EQUIVALENT 0.01 mF 1 2 3 4 CONTROL INPUTS Figure 20. 4-Input Multiplexer Figure 21. Sample/Hold Amplifier http://onsemi.com 10 MC74LVX4066 PACKAGE DIMENSIONS SOIC-14 D SUFFIX CASE 751A-03 ISSUE J NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. -A- 14 8 -B- P 7 PL 0.25 (0.010) B M 7 1 G -T- 0.25 (0.010) M T B S A DIM A B C D F G J K M P R J M K D 14 PL F R X 45 _ C SEATING PLANE M S SOLDERING FOOTPRINT 7X 7.04 14X 1.52 1 14X 0.58 1.27 PITCH DIMENSIONS: MILLIMETERS http://onsemi.com 11 MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 MC74LVX4066 PACKAGE DIMENSIONS TSSOP-14 DT SUFFIX CASE 948G-01 ISSUE B 14X K REF 0.10 (0.004) 0.15 (0.006) T U M T U V S S S N 2X 14 L/2 M B -U- L PIN 1 IDENT. N F 7 1 0.15 (0.006) T U 0.25 (0.010) 8 S DETAIL E K A -V- EEE CCC CCC EEE K1 J J1 SECTION N-N C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.10 0.193 0.200 B 4.30 4.50 0.169 0.177 C --- 1.20 --- 0.047 D 0.05 0.15 0.002 0.006 F 0.50 0.75 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J1 0.09 0.16 0.004 0.006 -W- K 0.19 0.30 0.007 0.012 K1 0.19 0.25 0.007 0.010 L 6.40 BSC 0.252 BSC M 0_ 8_ 0_ 8_ SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 14X 0.36 14X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 12 MC74LVX4066 PACKAGE DIMENSIONS SOEIAJ-14 M SUFFIX CASE 965-01 ISSUE B 14 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). LE 8 Q1 E HE L 7 1 M_ DETAIL P Z D VIEW P A e A1 b 0.13 (0.005) c M 0.10 (0.004) DIM A A1 b c D E e HE L LE M Q1 Z MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --1.42 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.004 0.008 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.056 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. 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