Rev. 1.2 3/12 Copyright © 2012 by Silicon Laboratories Si8410/20/21 / Si8422/23
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
LOW-POWER, SINGLE AND DUAL-CHANNEL
DIGITAL ISOLATORS
Features
Applications
Safety Regulatory Approvals
Description
Silicon Lab's family of ultra-low-power digital isolators are CMOS devices offering
substantial data rate, propagation delay, power, size, reliability, and external BOM
advantages when compared to legacy isolation technologies. The operating
parameters of these products remain stable across wide temperature ranges and
throughout device service life for ease of design and highly uniform performance.
All device versions have Schmitt trigger inputs for high noise immunity and only
require VDD bypass capacitors.
Data rates up to 150 Mbps are supported, and all devices achieve worst-case
propagation delays of less than 10 ns. Ordering options include a choice of
isolation ratings (up to 5 kV) and a selectable fail-safe operating mode to control
the default outp ut state during power loss. All products are safety certified by UL,
CSA, and VDE, and products in wide-body packages support reinforced insulation
withstanding up to 5 kVRMS.
High-speed operation
DC to 150 Mbps
No start-up initialization required
Wide Operating Supply Voltage:
2.6–5.5 V
Up to 5000 VRMS isolation
High electromagnetic immunity
Ultra low power (typical)
5 V Operation:
< 2.6 mA/channel at 1 Mbps
< 6.8 mA/channel at 100 Mbps
2.70 V Operation:
< 2.3 mA/channel at 1 Mbps
< 4.6 mA/channel at 100 Mbps
Schmitt trigger inputs
Selectable fail-safe mode
Default high or low output
Precise timing (typical)
11 ns propagation delay max
1.5 ns pulse width distortion
0.5 ns channel-channel skew
2 ns propagation delay skew
5 ns minimum pulse width
Transient immunity 45 kV/µs
Wide temperature range
–40 to 125 °C at 150 Mbps
RoHS compliant packages
SOIC-16 wide body
SOIC-8 narrow body
Industrial automation systems
Medical electronics
Hybrid electric vehicles
Isolated switch mode supplies
Isolated ADC, DAC
Motor control
Power inverters
Communication systems
UL 1577 recognized
Up to 5000 VRMS for 1 minute
CSA component notice 5A approval
IEC 60950-1, 61010-1, 60601-1
(reinforced insulation)
VDE certification conformity
IEC 60747-5-2
(VDE0884 Part 2)
EN60950-1 (reinforced insulation)
Ordering Information:
See page 29.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2 Rev. 1.2
Rev. 1.2 3
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.1. Theory of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
2.2. Eye Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
3. Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
3.1. Device Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.2. Under Voltage Lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
3.3. Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.4. Fail-Safe Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.5. Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4. Pin Descriptions (Wide-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
5. Pin Descriptions (Narrow-Body SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
7. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
8. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
9. Package Outline: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
10. Land Pattern: 8-Pin Narrow Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
12. Top Marking: 8-Pin Narrow-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
4 Rev. 1.2
1. Electrical Specifications
Table 1. Electrical Characteristics
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Locko ut
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteres is VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 4.8 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakag e Curr en t IL——±10µA
Output Impedance1ZO—50—
DC Supply Current (All inputs 0 V or at Supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2 5
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0
1.1 3.0
1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5
1.9 5.3
2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8
2.8 4.2
4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8
2.8 4.2
4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.4
1.9 5.1
2.9 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 p F on all ou tp uts)
Si8410Bx
VDD1
VDD2
—
—2.1
1.5 3.1
2.1 mA
Si8420Bx
VDD1
VDD2
—
—3.6
2.6 5.4
3.6 mA
Si8421Bx
VDD1
VDD2
—
—3.2
3.2 4.5
4.5 mA
Si8422Bx
VDD1
VDD2
—
—3.2
3.2 4.5
4.5 mA
Si8423Bx
VDD1
VDD2
—
—3.4
2.5 5.1
3.5 mA
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
6 Rev. 1.2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.1
5.0 3.1
6.3 mA
Si8420Bx
VDD1
VDD2
—
—3.7
9.8 5.4
12.3 mA
Si8421Bx
VDD1
VDD2
—
—6.8
6.8 8.5
8.5 mA
Si8422Bx
VDD1
VDD2
—
—6.8
6.8 8.5
8.5 mA
Si8423Bx
VDD1
VDD2
—
—3.4
9.2 5.1
11.5 mA
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si841xBx, Si842xBx
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
All Models
Output Rise Time trCL = 15 pF — 2.0 4.0 ns
Output Fall Time tfCL = 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time3tSU —1540µs
Table 1. Electrical Characteristics (Continued)
(VDD1 = 5 V ±10%, VDD2 = 5 V ±10%, TA=–40 to 125ºC)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of
the value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2 7
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Figure 1. Propagation Delay Timing
Typical
Input tPLH tPHL
Typical
Output trtf
90%
10%
90%
10%
1.4 V
1.4 V
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
8 Rev. 1.2
Table 2. Electrical Characteristics
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Lockout
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteresis VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.4 3.1 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakage Current IL——±10µA
Output Impedance (S i8410/20)1ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output p ins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2 9
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all output s)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0
1.1 3.0
1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5
1.9 5.3
2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8
2.8 4.2
4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8
2.8 4.2
4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.4
1.9 5.1
2.9 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0
1.3 3.0
1.8 mA
Si8420Bx
VDD1
VDD2
—
—3.5
2.3 5.3
3.2 mA
Si8421Bx
VDD1
VDD2
—
—3.0
3.0 4.4
4.4 mA
Si8422Bx
VDD1
VDD2
—
—3.0
3.0 4.4
4.4 mA
Si8423Bx
VDD1
VDD2
—
—3.4
2.2 5.1
3.1 mA
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output p ins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
10 Rev. 1.2
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0
3.6 3.0
4.5 mA
Si8420Bx
VDD1
VDD2
—
—4.5
7.0 5.3
8.8 mA
Si8421Bx
VDD1
VDD2
—
—5.3
5.3 6.6
6.6 mA
Si8422Bx
VDD1
VDD2
—
—5.3
5.3 6.6
6.6 mA
Si8423Bx
VDD1
VDD2
—
—3.4
6.6 5.1
8.3 mA
Timing Characteristics
Si841xAx, Si842xA x
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew2tPSK(P-P) — — 40 ns
Channel-Channel Skew tPSK — — 35 ns
Si841xBx, Si842xB x
Maximum Data Rate 0 — 150 Mbps
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH – tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew2tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output p ins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2 11
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
All Models
Output Rise Time trCL= 15 pF — 2.0 4.0 ns
Output Fall Time tfCL= 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time3tSU —1540µs
Table 2. Electrical Characteristics (Continued)
(VDD1 = 3.3 V ±10%, VDD2 = 3.3 V ±10%, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output p ins should be appropriately terminated with controlled
impedance PCB traces.
2. tPSK(P-P) is the magnitude of the difference in propagation delay times measured between different units operating at
the same supply voltages, load, and ambient temperature.
3. Start-up time is the time period from the application of power to valid data at the output.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
12 Rev. 1.2
Table 3. Electrical Characteristics1
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
VDD Undervoltage Threshold VDDUV+ VDD1, VDD2 rising 2.15 2.3 2.5 V
VDD Negative-Going Locko ut
Hysteresis VDDHYS 45 75 95 mV
Positive-Going Input Threshold VT+ All inputs rising 1.6 — 1.9 V
Negative-Going Input Threshold VT– All inputs falling 1.1 — 1.4 V
Input Hysteres is VHYS 0.40 0.45 0.50 V
High Level Input Voltage VIH 2.0 — — V
Low Level Input Voltage VIL ——0.8V
High Level Output Voltage VOH loh = –4 mA VDD1,VDD2 –0.
42.3 — V
Low Level Output Voltage VOL lol = 4 mA — 0.2 0.4 V
Input Leakag e Curr en t IL——±10µA
Output Impedance2ZO—50—
DC Supply Current (All inputs 0 V or at supply)
Si8410Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.0
1.0
3.0
1.0
1.5
1.5
4.5
1.5
mA
Si8420Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.3
1.7
5.8
1.7
2.0
2.6
8.7
2.6
mA
Si8421Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
1.7
1.7
3.7
3.7
2.6
2.6
5.6
5.6
mA
Si8422Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
3.7
3.7
1.7
1.7
5.6
5.6
2.6
2.6
mA
Notes:
1. Specifications in this table are also vali d at VDD1 = 2.6 V an d VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2 13
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Si8423Ax, Bx
VDD1
VDD2
VDD1
VDD2
All inputs 0 DC
All inputs 0 DC
All inputs 1 DC
All inputs 1 DC
—
—
—
—
5.4
1.7
1.3
1.7
8.1
2.6
2.0
2.6
mA
1 Mbps Supply Current (All inputs = 500 kHz square wave, CL= 15 pF on all outputs)
Si8410Ax, Bx
VDD1
VDD2
—
—2.0
1.1 3.0
1.7 mA
Si8420Ax, Bx
VDD1
VDD2
—
—3.5
1.9 5.3
2.9 mA
Si8421Ax, Bx
VDD1
VDD2
—
—2.8
2.8 4.2
4.2 mA
Si8422Ax, Bx
VDD1
VDD2
—
—2.8
2.8 4.2
4.2 mA
Si8423Ax, Bx
VDD1
VDD2
—
—3.3
1.8 5.0
2.8 mA
10 Mbps Supply Current (All inputs = 5 MHz square wave, CL= 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0
1.1 3.0
1.7 mA
Si8420Bx
VDD1
VDD2
—
—3.5
2.1 5.3
3.0 mA
Si8421Bx
VDD1
VDD2
—
—2.9
2.9 4.3
4.3 mA
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also vali d at VDD1 = 2.6 V an d VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
14 Rev. 1.2
Si8422Bx
VDD1
VDD2
—
—2.9
2.9 4.3
4.3 mA
Si8423Bx
VDD1
VDD2
—
—3.4
2.0 5.1
2.9 mA
100 Mbps Supply Current (All inputs = 50 MHz square wave, CL = 15 pF on all outputs)
Si8410Bx
VDD1
VDD2
—
—2.0
2.0 3.0
3.0 mA
Si8420Bx
VDD1
VDD2
—
—3.5
5.5 5.3
6.9 mA
Si8421Bx
VDD1
VDD2
—
—4.6
4.6 5.8
5.8 mA
Si8422Bx
VDD1
VDD2
—
—4.6
4.6 5.8
5.8 mA
Si8423Bx
VDD1
VDD2
—
—3.4
5.2 5.1
6.5 mA
Timing Characteristics
Si841xAx, Si842xAx
Maximum Data Rate 0 — 1.0 Mbps
Minimum Pulse Width — — 250 ns
Propagation Delay tPHL, tPLH See Figure 1 — — 35 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — — 25 ns
Propagation Delay Skew3tPSK(P-P) ——40ns
Channel-Channel Skew tPSK ——35ns
Si841xBx, Si842xBx
Maximum Data Rate 0 — 150 Mbps
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also vali d at VDD1 = 2.6 V an d VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Rev. 1.2 15
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Minimum Pulse Width — — 6.0 ns
Propagation Delay tPHL, tPLH See Figure 1 4.0 8.0 11 ns
Pulse Width Distortion
|tPLH - tPHL|PWD See Figure 1 — 1.5 3.0 ns
Propagation Delay Skew3tPSK(P-P) —2.03.0ns
Channel-Channel Skew tPSK —0.51.5ns
All Models
Output Rise Time trCL= 15 pF — 2.0 4.0 ns
Output Fall Time tfCL= 15 pF — 2.0 4.0 ns
Peak Eye Diagram Jitter tJIT(PK) See Figure 6 — 350 — ps
Common Mode Transient
Immunity CMTI VI=V
DD or 0 V 20 45 — kV/µs
Start-up Time4tSU —1540µs
Table 4. Absolute Maximum Ratings1
Parameter Symbol Min Typ Max Unit
Storage Temperature2TSTG –65 — 150 C°
Operating Temperature TA–40 — 125 C°
Supply Voltage VDD1, VDD2 –0.5 — 6.0 V
Input Voltage VI–0.5 — VDD + 0.5 V
Output Voltage VO–0.5 — VDD + 0.5 V
Output Current Drive Channel IO——10mA
Lead Solder Temperature (10 s) — — 260 C°
Maximum Isolation Voltage (1 s) NB SOIC-8 — — 4500 VRMS
Maximum Isolation Voltage (1 s) WB SOIC-16 — — 6500 VRMS
Notes:
1. Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation
should be restricted to conditions as specified in the operational sections of this data sheet.
2. VDE certifies storage temperature from –40 to 150 °C.
Table 3. Electrical Characteristics1 (Continued)
(VDD1 = 2.70 V, VDD2 = 2.70 V, TA= –40 to 125 °C)
Parameter Symbol Test Condition Min Typ Max Unit
Notes:
1. Specifications in this table are also vali d at VDD1 = 2.6 V an d VDD2 = 2.6 V when the operating temperature range is
constrained to TA= 0 to 85 °C.
2. The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination of the
value of the on-chip series termination resistor and channel resistance of the output driver FET. When driving loads
where transmission line effects will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3. tPSK(P-P) is the magnitude of the difference in propagation delay times measu re d between different units operating at
the same supply voltages, load, and ambient temperature.
4. Start-up time is the time period from the application of power to valid data at the output.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
16 Rev. 1.2
Table 5. Recommended Operating Conditions
Parameter Symbol Test Condition Min Typ Max Unit
Ambient Operating Temperature* TA150 Mbps, 15 pF, 5 V –40 25 125 C°
Supply Voltage VDD1 2.70 — 5.5 V
VDD2 2.70 — 5.5 V
*Note: The maximum ambient temperature is dependent up on data frequency, output loa ding , the numb er of operating
channels, and supply voltage.
Table 6. Regulatory Information*
CSA
The Si84xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic ins ulation working volt-
age.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si84xx is certified according to IEC 60747-5- 2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 891 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic ins ulation working volt-
age.
UL
The Si84xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic insulation.
*Note: Regulatory Certifications apply to 2.5 k V RMS rated devices which are production tested to 3.0 kVRMS for 1 sec.
Regulatory Certifications apply to 5.0 kVRMS rated devices which are production tested to 6.0 kVRMS for 1 sec.
For more information, see "6. Ordering Guide" on page 29.
Rev. 1.2 17
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Table 7. Insulation and Safety-Related Specifications
Parameter Symbol Test Condition Value Unit
WB
SOIC-16 NB
SOIC-8
Nominal Air Gap (Clearance)1L(IO1) 8.0 min 4.9 min mm
Nominal External Tracking (Creepage)1L(IO2) 8.0 min 4.01 min mm
Minimum Internal Gap (Internal Clearance) 0.014 0.008 mm
Tracking Resistance
(Proof Tracking Index) PTI IEC60112 600 600 VRMS
Erosion Depth ED 0.019 0.040 mm
Resistance (Input-Output)2RIO 101,2 101,2
Capacitance (Input-Output)2CIO f = 1 MHz 2.0 1.0 pF
Input Capacitance3CI4.0 4.0 pF
Notes:
1. The values in this table correspond to the nominal creepage and clearance values as detailed in “7. Pa ckage Outline:
16-Pin Wide Body SOIC”, “9. Package Outline: 8-Pin Narrow Body SOIC”. VDE certifies the clearance and creepage
limits as 8.5 mm minimum for the WB SOIC-16 package and 4.7 mm minimum for the NB SOIC-8 package. UL does
not impose a clearance and creepage minimum for component level certifications. CSA certifies the clearance and
creepage limits as 3.9 mm minimum for the NB SOIC-8 and 7.6 mm minimum for the WB SOIC-16 package.
2. To determine resistance and capacitance, the Si84xx is converted into a 2-terminal device. Pins 1–8 (1–4, NB SOIC-8)
are shorted together to form the first terminal and pins 9–16 (5–8, NB SOIC-8) are shorted together to form the second
terminal. The parameters are then measured between these two terminals.
3. Measured from input pin to ground.
Table 8. IEC 60664-1 (VDE 0844 Part 2) Ratings
Parameter Test Conditions Specification
NB SOIC8 WB SOIC 16
Basic Isolation Group Material Group I I
Installation Classification
Rated Mains Voltages < 150 VRMS I-IV I-IV
Rated Mains Voltages < 300 VRMS I-III I-IV
Rated Mains Voltages < 400 VRMS I-II I-III
Rated Mains Voltages < 600 VRMS I-II I-III
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
18 Rev. 1.2
Table 9. IEC 60747-5-2 Insulation Characteristics for Si84xxxx*
Parameter Symbol Test Condition Characteristic Unit
WB
SOIC-16 NB SOIC-8
Maximum Working Insulation
Voltage VIORM 891 560 Vpeak
Input to Output Test Voltage
Method b1
(VIORM x1.875=V
PR, 100%
Production Test, tm= 1 sec,
Partial Discharge < 5 pC)
1671 1050
Transient Overvoltage VIOTM t = 60 sec 6000 4000 Vpeak
Pollution Degree
(DIN VDE 0110, Table 1) 22
Insulation Resistance at TS,
VIO =500V RS>109>109
*Note: Maintenance of the safety data is ensured by protective circuits. The Si84xx provides a climate classification of
40/125/21.
Table 10. IEC Safety Limiting Values1
Parameter Symbol Test Condition Min Typ Max Unit
WB
SOIC-16 NB
SOIC-8
Case Temperature TS— — 150 150 °C
Safety Input, Output, or
Supply Current ISJA = 140 °C/W (NB SOIC-8),
100 °C (WB SOIC-16),
VI=5.5V, T
J=150°C, T
A=25°C
— — 220 160 mA
Device Power
Dissipation2PD— — 150 150 mW
Notes:
1. Maximum value allowed in the event of a failure; al so see the thermal derating curve in Figures 2 and 3.
2. The Si84xx is tested with VDD1 = VDD2 = 5.5 V, TJ=150ºC, C
L= 15 pF, input a 150 Mbps 50% duty cycle square
wave.
Rev. 1.2 19
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Figure 3. (NB SOIC-8) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Table 11. Thermal Characteristics
Parameter Symbol WB SOIC-16 NB SOIC-8 Unit
IC Junction-to-Air Thermal Resistance JA 100 140 ºC/W
0 20015010050
500
250
125
0
Case Temperature (ºC)
Safety-Limiting Values (mA)
460
375 VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
360
220
0 20015010050
400
200
100
0
Case Temperature (ºC)
Safety-Limiting Values (mA)
320
300 VDD1, VDD2 = 2.70 V
VDD1, VDD2 = 3.3 V
VDD1, VDD2 = 5.5 V
270
160
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
20 Rev. 1.2
2. Functional Description
2.1. Theory of Operation
The operation of an Si84xx channel is analogous to that of an opto coupler, except an RF carrier is modulated
instead of light. This simple architecture provides a robust isolated data path and requires no special
considerations or initialization at start-up. A simplified block diagram for a single Si84xx channel is shown in
Figure 4.
Figure 4. Simplified Channel Diagram
A channel consists of an RF Transmitter and RF Receiver separated by a semiconductor-based isolation barrier.
Referring to the Transmitter, input A modulates the carrier provided by an RF oscillator using on/off keying. The
Receiver contains a demodulat or that decodes the input state according to its RF energy content and applies the
result to output B via the output driver. This RF on/off keying scheme is superior to pulse code schemes as it
provides best-in-class noise immunity, low power consumption, and better immunity to magnetic fields. See
Figure 5 for more details.
Figure 5. Modulation Scheme
RF
OSCILLATOR
MODULATOR DEMODULATOR
A B
Semiconductor-
Based Isolation
Barrier
Transmitter Receiver
Input Signal
Output Signal
Modulation Signal
Rev. 1.2 21
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
2.2. Eye Diagram
Figure 6 illustrates an eye-diagram taken on an Si8422. For the data source, the test used an Anritsu (MP1763C)
Pulse Pattern Generator set to 1000 ns/div. The output of the generator's clock and data from an Si8422 were
captured on an oscilloscope. The results illustrate that data integrity was maintained even at the high data rate of
150 Mbps. The results also show that 2 ns pulse width distortion and 250 ps peak jitter were exhibited.
Figure 6. Eye Diagram
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
22 Rev. 1.2
3. Device Operation
Device behavior during start-up, normal operation, and shutdown is shown in Figure 7, where UVLO+ and UVLO-
are the positive-going and negative-going thresholds respectively. Refer to Table 12 to determine outputs when
power supply (VDD) is not present.
Table 12. Si84xx Logic Operation Table
VI Input1,4VDDI State1,2,3 VDDO State1,2,3 VO Output1,4Comments
HP P H
Normal operation.
LP P L
X5UP P H6 (Si8422/23)
L6 (Si8410/20/21) Upon transition of VDDI from unpowered to
powered, VO re turns to the same st a te as VI in
less than 1 µs.
X5P UP Undetermined Upon transition of VDDO from unpowered to
powered, VO returns to the same state as VI
within 1 µs.
Notes:
1. VDDI and VDDO are the input and output power supplies. VI and VO are the respective input and output terminals.
2. Powered (P) state is defined as 2.70 V < VDD < 5.5 V.
3. Unpowered (UP) state is defined as VDD = 0 V.
4. X = not applicable; H = Logic High; L = Logic Low.
5. Note that an I/O can power the die for a given side through an internal diode if its source has adequate current.
6. See "6. Ordering Guide" on page 29 for details. This is the selectable fail-safe operating mode (ordering option). Some
devices have default output state = H, and some have default output state = L, depending on the ordering part number
(OPN).
Rev. 1.2 23
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3.1. Device Startup
Outputs are held low during power up until VDD is above the UVLO th re shold for time period tSTART. Following this,
the outputs follow the states of inputs.
3.2. Under Voltage Lockout
Under Voltage Lockout (UVLO) is provided to prevent erroneous operation during device startup and shutdown or
when VDD is be low its specified operating circuits range. Both Side A and Side B ea ch ha ve the ir own und ervo ltage
lockout monitors. Each side can enter or exit UVLO independently. For example, Side A unconditionally enters
UVLO when VDD1 falls below VDD1(UVLO–) and exits UVLO when VDD1 rises above VDD1(UVLO+). Side B operates
the same as Side A with respect to its VDD2 supply.
Figure 7. Device Behavior during Normal Operation
INPUT
VDD1
UVLO-
VDD2
UVLO+
UVLO-
UVLO+
OUTPUT
tSTART tSTART tSTART tPHL tPLH
tSD
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
24 Rev. 1.2
3.3. Layout Recommendations
To ensure safety in the end user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically
separated from the safety extra-low voltage circuits (SELV is a circuit with <30 VAC) by a certain distance
(creepage/clear ance). I f a com ponent, such as a digital isolator, straddles this isolation barrier, it must meet those
creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating
(commonly referred to as working voltage protection). Table 6 on page 16 and Table 7 on page 17 detail the
working voltage and creepage/clearance capabilities of the Si84xx. These tables also detail the component
standards (UL1577, IEC60747, CSA 5A), which are readily accepted by certification bodies to provide proof for
end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-1, etc.)
requirements before starting an y des ign tha t uses a digital isolator.
3.3.1. Supply Bypass
The Si841x/2x family requires a 0.1 µF bypass capacitor between VDD1 and GND1 and VDD2 and GND2. The
capacitor should be placed as close a s possible to the p ackage. To enhance the robustness of a design, it is further
recommended that the user also add 1 µF bypass capacitors and include 100 resistors in series with the inputs
and outputs if the system is excessively noisy.
3.3.2. Pin Connections
No connect pins are not internally connected. They can be left floating, tied to VDD, or tied to GND.
3.3.3. Output Pin Termination
The nominal output impedance of an isolator driver channel is approximately 50 , ±40%, which is a combination
of the value of the on-chip series termination resistor and cha nnel resist ance of the output driver FET. When driving
loads where transmission line effect s will be a factor, output pins should be appropriately terminated with controlled
impedance PCB traces.
3.4. Fail-Safe Operating Mode
Si84xx devices feature a selectable (by ordering option) mode whereby the default output state (when the input
supply is unpowered) can either be a logic high or logic low when the output supply is powered. See Table 1 2 on
page 22 and "6. Ordering Guide" on page 29 for more information.
Rev. 1.2 25
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
3.5. Typical Performance Characteristics
The typical performance ch ar acteristics depicted in the following diagra ms are for informa tio n p urpose s only. Refer
to Tables 1, 2, and 3 for actual specification limits.
Figure 8. Si8410 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 9. Si8420 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 10. Si8421 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
Figure 11. Si8410 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 12. Si8420 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 13. Si8422 Typical VDD1 or VDD2 Supply
Current vs. Data Rate 5, 3.3, and 2.70 V
Operation (15 pF Load)
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (M b p s)
Current (m A)
5V
3.3V
2.70V
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mb p s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbp s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
0 102030405060708090100110120130140150
Data Ra te (Mb p s)
Current (m A)
5V
3.3V
2.70V
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbp s)
Cur r en t (mA)
5V
2.70V
3.3V
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbp s)
Cur r en t (mA)
5V
3.3V
2.70V
26 Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
Figure 14. Si8423 Typical VDD1 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
Figure 15. Si8423 Typical VDD2 Supply Current
vs. Data Rate 5, 3.3, and 2.70 V Operation
(15 pF Load)
Figure 16. Propagation Delay
vs. Temperature
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mb p s)
Cur r en t (mA)
5V
3.3V
2.70V
0
5
10
15
20
25
30
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
Data Rate (Mbp s)
Cur r en t (mA)
5V
2.70V
3.3V
5
6
7
8
9
10
-40 -20 0 20 40 60 80 100 120
Temperature (Degrees C)
Delay (n s )
Rising Edge
Falling Edge
Rev. 1.2 27
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
4. Pin Descriptions (Wide-Body SOIC)
Name SOIC-16 Pin#
Si8410 SOIC-16 Pin#
Si842x Type Description
GND1 1 1 Ground Side 1 ground.
NC* 2, 5, 6, 8,10,
11, 12, 15 2, 6, 8,10,
11, 15 No Connect NC
VDD1 3 3 Supply Side 1 power sup p ly.
A1 4 4 Digital I/O Side 1 digital input or output.
A2 NC 5 Digital I/O Side 1 digital input or output.
GND1 7 7 Ground Side 1 ground.
GND2 9 9 Ground Side 2 ground.
B2 NC 12 Digital I/O Side 2 digital input or output.
B1 13 13 Digital I/O Side 2 digital input or output.
VDD2 14 14 Supply Side 2 power sup p ly.
GND2 16 16 Ground Side 2 ground.
*Note: No Connect. These pins are not internally connected. They can be left floating, tied to VDD or tied to GND.
GND1
NC
A1
VDD1
GND2
B1
NC
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
NC
GND1
NC
NC
VDD2
NC
Si8410 WB SOIC-16
NC
NC
GND1
A2
NC
A1
VDD1
GND2
B1
NC
B2
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
RF
XMITR RF
RCVR
NC
GND1
NC
NC
VDD2
NC
Si8420/23 WB SOIC-16
GND1
A2
NC
A1
VDD1
GND2
B1
NC
B2
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR RF
RCVR
RF
XMITR
RF
RCVR
NC
GND1
NC
NC
VDD2
NC
Si8421 WB SOIC-16
GND1
A2
NC
A1
VDD1
GND2
B1
NC
B2
GND2
I
s
o
l
a
t
i
o
n
RF
XMITR
NC
GND1
NC
NC
VDD2
NC
Si8422 WB SOIC-16
RF
RCVR
RF
XMITR
RF
XMITR
RF
RCVR
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
28 Rev. 1.2
5. Pin Descriptions (Narrow-Body SOIC)
Name SOIC-8 Pin#
Si842x Type Description
VDD1 1 Supply Side 1 power supply.
GND1 4 Ground Side 1 ground.
A1 2 Digital I/O Side 1 digital input or output.
A2 3 Digital I/O Side 1 digital input or output.
B1 7 Digital I/O Side 2 digital input or output.
B2 6 Digital I/O Side 2 digital input or output.
VDD2 8 Supply Side 2 power supply.
GND2 5 Ground Side 2 ground.
I
s
o
l
a
t
i
o
n
VDD1 VDD2
A1 B1
A2 B2
RF
XMITR
RF
RCVR
GND1 GND2
Si8422 NB SOIC-8
RF
RCVR
RF
XMITR
RF
RCVR RF
XMITR
I
s
o
l
a
t
i
o
n
VDD1 VDD2
A1 B1
RF
XMITR RF
RCVR
A2 B2
RF
XMITR RF
RCVR
GND1 GND2
Si8423 NB SOIC-8
Rev. 1.2 29
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
6. Ordering Guide
Table 13. Ordering Guide1
Ordering Part
Number (OPN)
Number of
Inputs
VDD1 Side
Number of
Inputs
VDD2 Side
Maximum
Data Rate
(Mbps)
Default
Output
State
Isolation
Rating Temp
Range Package
Type
Si8422AB-B-IS 1 1 1 High
2.5 kV rms –40 to 125 °C NB SOIC-8
Si8422BB-B-IS 1 1 150 High
Si8423AB-B-IS 2 0 1 High
Si8423BB-B-IS 2 0 150 High
Si8410AD-A-IS2 1 0 1 Low
5.0 kV rms –40 to 125 °C WB SOIC- 16
Si8410BD-A-IS21 0 150 Low
Si8420AD-A-IS22 0 1 Low
Si8420BD-A-IS22 0 150 Low
Si8421AD-B-IS21 1 1 Low
Si8421BD-B-IS21 1 150 Low
Si8422AD-B-IS 1 1 1 High
Si8422BD-B-IS 1 1 150 High
Si8423AD-B-IS 2 0 1 High
Si8423BD-B-IS 2 0 150 High
Notes:
1. All packages are RoHS-compliant with peak reflow temperatures of 260 °C according to th e JEDEC industry standard
classifications and peak solder temperatures.
Moisture sensitivity level is MSL2A for wide-body SOIC-16 packages.
Moisture sensitivity level is MSL2A for narrow-body SOIC-8 packages.
2. Refer to Si8410/20/21 data sheet for information regarding 2.5 kV rated versions of these products.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
30 Rev. 1.2
7. Package Outline: 16-Pin Wide Body SOIC
Figure 17 illustrates the package details for the Si84xx Digital Isolator. Table 14 lists the values for the dimens ions
shown in the illustration.
Figure 17. 16-Pin Wide Body SOIC
Table 14. Package Diagram Dimensions
Symbol
Millimeters
Min Max
A — 2.65
A1 0.1 0.3
D 10.3 BSC
E 10.3 BSC
E1 7.5 BSC
b 0.31 0.51
c 0.20 0.33
e 1.27 BSC
h 0.25 0.75
L 0.4 1.27
0° 7°
Rev. 1.2 31
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
8. Land Pattern: 16-Pin Wide-Body SOIC
Figure 18 illustrates the recommended land pattern details for the Si84xx in a 16-pin wide-body SOIC. Table 15
lists the values for the dimensions shown in the illustration.
Figure 18. 16-Pin SOIC Land Pattern
Table 15. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension Feature (mm)
C1 Pad Column Spacing 9.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.90
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
32 Rev. 1.2
9. Package Outline: 8-Pin Narrow Body SOIC
Figure 19 illustrates the package details for the Si84xx. Table 16 lists the values for the dimensions shown in the
illustration.
Figure 19. 8-pin Small Outline Integrated Circuit (SOIC) Package
Table 16. Package Diagram Dimensions
Symbol Millimeters
Min Max
A 1.35 1.75
A1 0.10 0.25
A2 1.40 REF 1.55 REF
B 0.33 0.51
C 0.19 0.25
D 4.80 5.00
E 3.80 4.00
e 1.27 BSC
H 5.80 6.20
h 0.25 0.50
L 0.40 1.27
08
Rev. 1.2 33
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
10. Land Pattern: 8-Pin Narrow Body SOIC
Figure 20 illustrates the recommended land pattern details for the Si84xx in an 8-pin narrow-body SOIC. Table 17
lists the values for the dimensions shown in the illustration.
Figure 20. PCB Land Pattern: 8-Pin Narrow Body SOIC
Table 17. PCM Land Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension Feature (mm)
C1 Pad Column Spacing 5.40
E Pad Row Pitch 1.27
X1 Pad Width 0.60
Y1 Pad Length 1.55
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X173-8 N for
Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
34 Rev. 1.2
11. Top Marking: 16-Pin Wide Body SOIC
Figure 21. Isolator Top Marking
Table 18. Top Marking Explanation
Line 1 Marking: Base Part Number
Ordering Options
(See Ordering Gui de fo r mo re
information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of reverse channels (1, 0)1,2
S = Speed Grade
A = 1 Mbps; B = 150 Mbps
V = Insulation rating
A=1kV; B=2.5kV; C=3.75kV; D=5kV
Line 2 Marking: YY = Year
WW = Workweek Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
TTTTTT = Mfg Code Manufacturing code from assembly house.
Line 3 Marking: Circle = 1.5 mm Diameter
(Center-Justified) “e3” Pb-Free Symbol.
Country of Origin ISO Code
Abbreviation TW = Taiwan.
Notes:
1. The Si8422 has one reverse chann el.
2. The Si8423 has zero reverse channels.
Si84XYSV
YYWWTTTTTT
TW
e3
Rev. 1.2 35
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
12. Top Marking: 8-Pin Narrow-Body SOIC
Figure 22. Isolator Top Marking
Table 19. Top Marking Explanations
Line 1 Marking: Base Part Number
Ordering Options
(See Ordering Guid e fo r mo re
information).
Si84 = Isolator product series
XY = Channel Configuration
X = # of data channels (2, 1)
Y = # of rever se ch an n els (1 , 0) 1,2
S = Speed Grade
A = 1 Mbps; B = 15 0 Mbps
V = Insulation rating
A=1kV; B=2.5kV; C=3.75kV; D=5kV
Line 2 Marking: YY = Year
WW = Workweek Assigned by assembly subcontractor. Corresponds to
the year and workweek of the mold date.
R = Product (OPN) Revision
F = Wafer Fa b
Line 3 Marking: Circle = 1.1 mm Diameter
Left-Justified “e3” Pb-Free Symbol.
First two characters of the manufacturing code.
A = Assembly Site
I = Internal Code
XX = Serial Lot Number
Last four characters of the manufacturing code.
Notes:
1. The Si8422 has one reverse chann el.
2. The Si8423 has zero reverse channels.
Si84XYSV
YYWWRF
AIXX
e3
36 Rev. 1.2
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 1.0
Updated “ Features” on page 1.
Updated transient immunity
Removed Block Diagram from page 1.
Added chip graphics on page 1.
Added Peak Eye Diagram jitter in Tables 1, 2, and 3.
Updated transient immunity
Moved Table 12 to page 22.
Added "3. Device Operation" on page 22.
Added "3.4. Fail-Safe Operating Mode" on page 24.
Moved “Typical Performance Characteristics” to
page 25.
Deleted RF Radiated Emissions section.
Deleted RF Magnetic and Common-Mode Transient
Immunity section.
Updated MSL ra tin g to M SL2 A.
Revision 1.0 to Revision 1.1
Numerous text edits.
Added notes to Tables 18 and 19.
Revision 1.1 to Revision 1.2
Updated Timing Characteristics in Tables 1, 2, and 3.
Rev. 1.2 37
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
NOTES:
Si8410/20/21 (5 kV)
Si8422/23 (2.5 & 5 kV)
38 Rev. 1.2
CONTACT INFORMATION
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