ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E (R) Data Sheet December 16, 2008 QUAD, 16.5kV ESD Protected, 3.0V to 5.5V, Low Power, RS-422 Transmitters The Intersil ISL32x7xE are 16.5kV IEC61000-4-2 ESD Protected, 3.0V to 5.5V powered, QUAD transmitters for balanced communication using the RS-422 standard. These drivers have very low output leakage currents (10A), so they present a low load to the RS-422 bus. Driver (Tx) outputs are tri-statable, and incorporate a hot plug feature to keep them disabled during power-up and down. Versions are available with a common EN/EN (`172 pinout), a two channel EN12/EN34 (`174 pinout), or a versatile combination of individual and group channel enables (see Table 1). The ISL32372E, ISL32374E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or from unterminated stubs in multidrop and multipoint applications. Drivers on the other versions are not limited, so they can achieve the 10Mbps or 32Mbps data rates. All versions are offered in Industrial and Extended Industrial (-40C to +125C) temperature ranges. A 50% smaller footprint (compared to the TSSOP) is available with the ISL32179E's QFN package. This device also features a logic supply pin (VL), that sets the switching points of the enable and DI inputs to be compatible with a lower supply voltage in mixed voltage systems. Two speed select pins allow the ISL32179E user to select from three slew rate options for 460kbps, 10Mbps, or 32Mbps data rates. Individual channel and group enable pins increase the ISL32179E's flexibility. FN6824.0 Features * IEC61000 ESD Protection on RS-422 Outputs . . 16.5kV - Class 3 ESD Level on all Other Pins . . . . . . 12kV HBM - High Machine Model ESD Level on all Pins . . . . . 700V * Wide Supply Range . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V * Specified for +125C Operation * Available in Industry Standard Pinouts (`172/'174) or in a Space Saving QFN (ISL32179E) with Added Features * Logic Supply Pin (VL) Eases Operation in Mixed Supply Systems (ISL32179E Only) * User Selectable Data Rate (ISL32179E Only) * Hot Plug - Tx Outputs Remain Three-state During Power-up and Power-Down * Low Tx Leakage Allows > 256 Devices on the Bus * High Data Rates . . . . . . . . . . . . . . . . . . . . . up to 32Mbps * Low Quiescent Supply Current . . . . . . . . . . 0.8mA (Max) - Low Shutdown Supply Current . . . . . . . . . . . . . . . 60A * Current Limiting and Thermal Shutdown for Driver Overload Protection * Tri-statable Tx Outputs * 5V Tolerant Logic Inputs When VCC 5V * Pb-free (RoHS compliant) Applications * Telecom Equipment * Motor Controllers / Encoders * Programmable Logic controllers * Industrial/Process Control Networks TABLE 1. SUMMARY OF FEATURES PART NUMBER FUNCTION DATA RATE (Mbps) SLEW-RATE LIMITED? HOT PLUG? VL PIN? TX ENABLE TYPE QUIESCENT ICC (mA) LOW POWER SHUTDOWN? PIN COUNT ISL32172E 4 Tx 32 NO YES NO EN, EN <1 NO 16 ISL32272E 4 Tx 10 NO YES NO EN, EN <1 NO 16 ISL32372E 4 Tx 0.46 YES YES NO EN, EN <1 NO 16 ISL32174E 4 Tx 32 NO YES NO EN12, EN34 <1 NO 16 ISL32274E 4 Tx 10 NO YES NO EN12, EN34 <1 NO 16 ISL32374E 4 Tx 0.46 YES YES NO EN12, EN34 <1 NO 16 ISL32179E 4 Tx 32, 10, 0.46 SELECTABLE YES YES INDIV. AND GROUP ENABLES <1 YES 24 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Pinouts ISL32174E, ISL32274E, ISL32374E (16 LD N-SOIC, TSSOP) TOP VIEWS ISL32172E, ISL32272E, ISL32372E (16 LD N-SOIC, TSSOP) TOP VIEWS 16 VCC DI1 1 15 DI4 Y1 2 14 Y4 Z1 3 EN 4 13 Z4 EN12 4 Z2 5 12 EN Z2 5 DI1 1 Y1 2 Z1 3 D D D 16 VCC 15 DI4 D D 14 Y4 13 Z4 12 EN34 D 11 Z3 11 Z3 Y2 6 DI2 7 10 Y3 DI2 7 10 Y3 GND 8 9 DI3 GND 8 9 DI3 Y2 6 D D Y1 DI1 SHDNEN VCC VL DI4 ISL32179E (24 LD QFN) TOP VIEW 24 23 22 21 20 19 EN2 3 16 EN4 EN 4 15 EN3 Z2 5 14 EN Y2 6 13 Z3 7 8 9 10 11 12 Y3 17 Z4 DI3 2 SPB EN1 GND 18 Y4 SPA 1 DI2 Z1 Ordering Information PART NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. # ISL32172EFBZ ISL32172 EFBZ -40 to +125 16 Ld SOIC M16.15 ISL32172EFVZ 32172 EFVZ -40 to +125 16 Ld TSSOP MDP0044 ISL32172EIBZ ISL32172 EIBZ -40 to +85 16 Ld SOIC M16.15 ISL32172EIVZ 32172 EIVZ -40 to +85 16 Ld TSSOP MDP0044 ISL32174EFBZ ISL32174 EFBZ -40 to +125 16 Ld SOIC M16.15 ISL32174EFVZ 32174 EFVZ -40 to +125 16 Ld TSSOP MDP0044 ISL32174EIBZ ISL32174 EIBZ -40 to +85 16 Ld SOIC M16.15 ISL32174EIVZ 32174 EIVZ -40 to +85 16 Ld TSSOP MDP0044 ISL32179EFRZ 321 79EFRZ -40 to +125 24 Ld QFN L24.4x4C ISL32179EIRZ 321 79EIRZ -40 to +85 24 Ld QFN L24.4x4C ISL32272EFBZ ISL32272 EFBZ -40 to +125 16 Ld SOIC M16.15 ISL32272EFVZ 32272 EFVZ -40 to +125 16 Ld TSSOP MDP0044 ISL32272EIBZ ISL32272 EIBZ -40 to +85 16 Ld SOIC M16.15 ISL32272EIVZ 32272 EIVZ -40 to +85 16 Ld TSSOP MDP0044 2 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Ordering Information (Continued) PART NUMBER (Notes 1, 2) PART MARKING TEMP. RANGE (C) PACKAGE (Pb-Free) PKG. DWG. # ISL32274EFBZ ISL32274 EFBZ -40 to +125 16 Ld SOIC M16.15 ISL32274EFVZ 32274 EFVZ -40 to +125 16 Ld TSSOP MDP0044 ISL32274EIBZ ISL32274 EIBZ -40 to +85 16 Ld SOIC M16.15 ISL32274EIVZ 32274 EIVZ -40 to +85 16 Ld TSSOP MDP0044 ISL32372EFBZ ISL32372 EFBZ -40 to +125 16 Ld SOIC M16.15 ISL32372EFVZ 32372 EFVZ -40 to +125 16 Ld TSSOP MDP0044 ISL32372EIBZ ISL32372 EIBZ -40 to +85 16 Ld SOIC M16.15 ISL32372EIVZ 32372 EIVZ -40 to +85 16 Ld TSSOP MDP0044 ISL32374EFBZ ISL32374 EFBZ -40 to +125 16 Ld SOIC M16.15 ISL32374EFVZ 32374 EFVZ -40 to +125 16 Ld TSSOP MDP0044 ISL32374EIBZ ISL32374 EIBZ -40 to +85 16 Ld SOIC M16.15 ISL32374EIVZ 32374 EIVZ -40 to +85 16 Ld TSSOP MDP0044 NOTES: 1. Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020 Truth Tables ISL32179E INPUTS ISL32172E, ISL32272E, ISL32372E INPUTS OUTPUTS ENX EN EN DIX SPA SPB ZX YX OUTPUTS COMMENTS EN EN DIX ZX YX 0 X X X X X Z Z Chan X outputs disabled X 0 1/0 0/1 1/0 X 0 1 X X X Z Z All outputs disabled 1 X 0/1 1/0 0/1 1 X 0 1/0 1 1 0 1 X Z Z 1 1 X 0/1 1 1 1 X 0 1/0 0 1 1 1 X 0/1 0 1 1 X 0 1/0 X* 0 1 1 X 0/1 X* 0 NOTE: Z = Tri-state ISL32174E, ISL32274E, ISL32374E INPUTS OUTPUTS EN12 EN34 DIX Z1 Y1 Z2 Y2 Z3 Y3 Z4 Y4 0 0 X Z Z Z Z Z Z Z Z 0 1 1/0 Z Z Z Z 0/1 1/0 0/1 1/0 1 0 1/0 0/1 1/0 0/1 1/0 Z Z Z Z 1 1 1/0 0/1 1/0 0/1 1/0 0/1 1/0 0/1 1/0 0/1 1/0 Individual ENX controls chan X (32Mbps) 1/0 0/1 0/1 1/0 Individual ENX controls chan X (10Mbps) 1/0 0/1 0/1 1/0 Individual ENX controls chan X (460kbps) 1/0 0/1 NOTE: *Keep SPA = 1 for lowest current in SHDN. If using individual channel enables, and the SHDN mode, connect EN and EN to VCC for the lowest SHDN current. ISL32179E enters SHDN when SHDNEN = 1 and all channels are disabled. Z = Tri-state. NOTE: Z = Tri-state 3 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Pin Descriptions PIN FUNCTION EN, EN Group driver output enables, that are internally pulled high to VCC. All ISL32x72E driver outputs, Y and Z, are enabled by driving EN high OR EN low, and the outputs are high impedance when EN is low AND EN is high (i.e., if using only the active high EN, connect EN directly to VCC or VL; if using only the active low EN, connect EN directly to GND). On the ISL32179E accomplish group enable by connecting all the ENX pins to VCC or VL, and then use the EN or EN pin as previously described. If the group driver enable function isn't required (see Note), connect EN to VCC, or connect EN to GND. (ISL32x72E and ISL32179E only) EN12, EN34 Paired driver output enables, that are internally pulled high to VCC. Driving EN12 (EN34) high enables Channel 1 and 2 (3 and 4) outputs (Y and Z). Driving EN12 (EN34) low disables Channel 1 and 2 (3 and 4) outputs. If the driver enable function isn't required (see Note), connect EN12 and EN34 to VCC. (ISL32x74E only) ENx Individual driver output enables that are internally pulled high to VCC. Forcing ENx high (along with EN high OR EN low) enables the channel X outputs (Y and Z). Driving ENX low disables the Channel X outputs, regardless of the states of EN and EN. Connect both EN and EN to VCC for the lowest SHDN current if utilizing SHDN mode (see SHDNEN below). If the individual driver enable function isn't required (see Note), connect ENX to VCC. (ISL32179E only) SHDNEN Low power SHDN mode enable. A high level allows the ISL32179E to enter a low power mode when all channels are disabled. A low level prevents the device from entering the low power mode. (ISL32179E only) DIx Driver input. A low on DI forces the corresponding channel's output Y low and output Z high. Similarly, a high on DI forces output Y high and output Z low. SPA, SPB GND Speed select inputs that are internally pulled-high. See ISL32179E Truth Table on page 3. (ISL32179E only) Ground connection. This is also the potential of the QFN thermal pad. Yx 16.5kV IEC61000-4-2 ESD Protected RS-422 level, noninverting transmitter output. Zx 16.5kV IEC61000-4-2 ESD Protected RS-422 level, inverting transmitter output. VCC VL System power supply input (3.0V to 5.5V). On devices with a VL pin, power-up VCC first. Logic power supply input. Connecting the VL pin to the lower voltage power supply of a logic device (e.g., UART or controller) interfacing with the ISL32179E tailors its logic pin (DI, EN (all varieties), SHDNEN, and SP) VIL/VIH levels to values compatible with the lower supply voltage. Power-up this supply after VCC, and keep VL VCC. (ISL32179E only) NOTE: Unused EN pins of any type should not be left floating, even though they have internal pull-ups. 4 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Operating Circuits (1 of 4 Channels Shown) NETWORK USING GROUP ENABLES +3.3V TO 5V +3.3V TO 5V + 16 VCC 0.1F 0.1F + 16 VCC ISL32x73E 3 RO ISL32x72E R A 2 B 1 RT 2 Y 3 Z D 12 EN DI 1 EN 4 EN 12 EN GND GND 4 8 8 NETWORK USING PAIRED ENABLES +3.3V TO 5V +3.3V TO 5V + 16 VCC 0.1F 0.1F + 16 VCC ISL32x75E A1 2 3 RO1 4 R EN12 4 ISL32x74E RT B1 1 2 Y1 3 Z1 D DI1 1 EN12 GND GND 8 8 NETWORK WITH VL PIN FOR INTERFACING TO LOWER VOLTAGE LOGIC DEVICES 1.8V +3.3V TO 5V +3.3V TO 5V + 22 21 VCC LOGIC DEVICE (P, ASIC, UART) 0.1F 0.1F 21 VCC VL 9 SHDNEN 15 EN 4 EN 1 RO1 A1 24 RT B1 23 2 EN1 GND 10 USING INDIVIDUAL CHANNEL ENABLES AND CONFIGURED FOR LOWEST SHDN SUPPLY CURRENT NOTE: POWER-UP VCC BEFORE VL 5 20 VL SHDNEN 22 ISL32179E EN 14 EN1-EN4 2,3,15,16 Y DI 23 Z D EN 4 VCC ISL32x77E R 2.5V + 24 1 VCC LOGIC DEVICE P, ASIC, UART) GND 9 USING ACTIVE HIGH GROUP ENABLE AND CONFIGURED FOR LOWEST SHDN SUPPLY CURRENT NOTE: POWER-UP VCC BEFORE VL FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Absolute Maximum Ratings Thermal Information VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V VL to GND (ISL32179E Only) . . . . . . . . . . . . . -0.3V to (VCC +0.3V) Input Voltages DI, EN (all varieties) . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 7V Output Voltages Y, Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Output Current Y, Z (Per Output, Continuous, TJ 125C) . . . . . . . . . . . . 100mA ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . See Specification Table Thermal Resistance (Typical) JA (C/W) JC (C/W) 16 Ld SOIC Package (Note 3) . . . . . . . 80 N/A 16 Ld TSSOP Package (Note 3) . . . . . 105 N/A 24 Ld QFN Package (Notes 4, 5). . . . . 42 5 Maximum Junction Temperature (Plastic Package) . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range ISL32x7xEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C ISL32x7xEI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379 for details. 5. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25C; Unless Otherwise Specified.(Notes 6, 10) PARAMETER SYMBOL TEST CONDITIONS TEMP (C) MIN (Note 9) TYP Full 2.5 - MAX (Note 9) UNITS DC CHARACTERISTICS Differential VOUT VOD No Load RL = 100 (RS-422) (see Figure 1) Single-Ended VOUT (Y or Z) VO VCC VCC 3V Full 2 2.6 - V VCC 4.5V Full 3 4 - V IO = -20mA, VOH Full 2.4 2.7 - V IO = 20mA, VOL Full - 0.2 0.4 V VOD RL = 100 (see Figure 1) Full - 0.01 0.2 V VOC RL = 100 (see Figure 1) Full - 2.6 3 V Change in Magnitude of Driver Common-Mode VOUT for Complementary Output States VOC RL = 100 (see Figure 1) Full - 0.01 0.2 V Input High Voltage (Logic Pins, Note 14) VIH1 VL = VCC if ISL32179E Full 2.2 - - V VCC 5.5V, DI Full 2.7 - - V VCC 5.5V, ENs Full 2.4 - - V Change in Magnitude of Driver Differential VOUT for Complementary Output States Driver Common-Mode VOUT VIH2 VIH2E Input Low Voltage (Logic Pins, Note 14) 6 VCC 3.6V VIH3 2.7V VL < 3.0V (ISL32179E Only) Full 2 - - V VIH4 2.3V VL < 2.7V (ISL32179E Only) Full 1.6 - - V VIH5 1.6V VL < 2.3V (ISL32179E Only) Full 0.72*VL - - V VIH6 1.5V VL < 1.6V (ISL32179E Only) 25 - 0.45*VL - V VIL1 VL = VCC if ISL32179E Full - - 0.8 V VIL2 VL 2.7V (ISL32179E Only) Full - - 0.6 V VIL3 2.3V VL < 2.7V (ISL32179E Only) Full - - 0.6 V VIL4 1.6V VL < 2.3V (ISL32179E Only) Full - - 0.22*VL V VIL5 1.5V VL < 1.6V (ISL32179E Only) 25 - 0.25*VL - V FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25C; Unless Otherwise Specified.(Notes 6, 10) (Continued) PARAMETER SYMBOL Logic Input Current Output Leakage Current (Y, Z) Thermal Shutdown Threshold TEMP (C) MIN (Note 9) TYP MAX (Note 9) UNITS - 1 A IIN1 DIX = 0V or VCC Full -1 IIN2 SP, EN, EN, ENX, SHDNEN = 0V or VCC Full -15 9 15 A IIN3 EN12, EN34 = 0V or VCC Full -30 18 30 A IOZ EN = 0, VCC = 0V to 5.5V, -0.25 VO 6V Full -10 - 10 A EN = 0, VCC = 3V to 5.5V, VO = 0V to VCC 25 -8 - 8 nA IOSD1 Driver Short-Circuit Current, VO = High or Low TEST CONDITIONS (Note 16) -30 - 30 nA EN = 1, VY or VZ = 0V (Note 7) Full - - 150 mA EN = 1, VY or VZ = VCC (Note 7) Full - - 200 mA Full - 160 - C DI = 0V or VCC, EN = 1 Full - 0.6 0.8 mA DI = 0V or VCC, All outputs disabled (Note 15), SHDNEN = 1 (ISL32179E only) Full - 60 90 A IEC61000-4-2, From Bus Pins to GND Air Gap 25 - 16.5 - kV Contact TSD SUPPLY CURRENT No-Load Supply Current ICC Shutdown Supply Current ISHDN ESD PERFORMANCE RS-422 Pins (Y, Z) 25 - 9 - kV Human Body Model, From Bus Pins to GND 25 - 15 - kV HBM, per MIL-STD-883 Method 3015 25 - 12 - kV Machine Model 25 - 700 - V VOD = 1.5V, CD = 820pF (see Figure 4) Full 460 4000 - kbps tPLH, tPHL RDIFF = 100, CD = 50pF (see Figure 2) Full - 90 300 ns RDIFF = 100, CD = 50pF (see Figure 2) Full - 55 150 ns All Pins DRIVER SWITCHING CHARACTERISTICS (ISL32372E, ISL32374E, ISL32179E, 460kbps) Maximum Data Rate fMAX Driver Single-Ended Output Delay Driver Single-Ended Output Skew tSSK Ch-to-Ch Output Delay Skew tSKCC (Figure 2, Note 11) Full - 60 200 ns Part-to-Part Output Delay Skew tSKPP (Figure 2, Note 8) Full - - 300 ns Driver Differential Output Skew tDSK RDIFF = 100, CD = 50pF (see Figure 2) Full - 2 60 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 100, CD = 50pF (see Figure 2) Full 60 100 220 ns Driver Enable to Output High tZH SW = GND (see Figure 3, Note 12) Full - - 200 ns Driver Enable to Output Low tZL SW = VCC (see Figure 3, Note 12) Full - - 200 ns Driver Disable from Output High tHZ SW = GND (see Figure 3) Full - - 100 ns Driver Disable from Output Low tLZ SW = VCC (see Figure 3) Full - - 100 ns Driver Enable from SHDN to High tSDH ISL32179E Only, SW = GND (see Figure 3, Note 13) Full - - 750 ns Driver Enable from SHDN to Low tSDL ISL32179E Only, SW = VCC (see Figure 3, Note 13) Full - - 750 ns VOD = 1.5V, CD = 400pF (see Figure 4) Full 10 20 - Mbps tPLH, tPHL RDIFF = 100, CD = 50pF (see Figure 2) Full - 13 25 ns RDIFF = 100, CD = 50pF (see Figure 2) Full - 2 9 ns DRIVER SWITCHING CHARACTERISTICS (ISL32272E, ISL32274E, ISL32179E, 10Mbps) Maximum Data Rate fMAX Driver Single-Ended Output Delay Driver Single-Ended Output Skew tSSK Ch-to-Ch Output Delay Skew tSKCC (Figure 2, Note 11) Full - 6 12 ns Part-to-Part Output Delay Skew tSKPP (Figure 2, Note 8) Full - - 20 ns Driver Differential Output Skew tDSK RDIFF = 100, CD = 50pF (see Figure 2) Full - 2 6 ns Driver Differential Rise or Fall Time tR, tF RDIFF = 100, CD = 50pF (see Figure 2) Full 7 11 20 ns Driver Enable to Output High tZH SW = GND (see Figure 3, Note 12) Full - - 20 ns Driver Enable to Output Low tZL SW = VCC (see Figure 3, Note 12) Full - - 20 ns 7 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Electrical Specifications Test Conditions: VCC = 3.0V to 3.6V and 4.5V to 5.5V; VL = VCC (ISL32179E only); Typicals are at VCC = 3.3V or VCC = 5V, TA = +25C; Unless Otherwise Specified.(Notes 6, 10) (Continued) PARAMETER SYMBOL Driver Disable from Output High TEST CONDITIONS TEMP (C) MIN (Note 9) TYP tHZ SW = GND (see Figure 3) Full - - tLZ MAX (Note 9) UNITS 20 ns SW = VCC (see Figure 3) Full - - 20 ns Driver Enable from SHDN to High tSDH ISL32179E Only, SW = GND (see Figure 3, Note 13) Full - - 750 ns Driver Enable from SHDN to Low tSDL ISL32179E Only, SW = VCC (see Figure 3, Note 13) Full - - 750 ns Driver Disable from Output Low DRIVER SWITCHING CHARACTERISTICS (ISL32172E, ISL32174E, ISL32179E, 32Mbps) Maximum Data Rate fMAX Driver Single-Ended Output Delay VOD = 1.5V, CD = 100pF (see Figure 4) Full 32 50 - Mbps tPLH, tPHL RDIFF = 100, CD = 50pF (see Figure 2) Full 3 8 15 ns RDIFF = 100, CD = 50pF (see Figure 2) Full - 1 3.5 ns Ch-to-Ch Output Delay Skew tSKCC (Figure 2, Note 11) Full - 3 5.5 ns Part-to-Part Output Delay Skew tSKPP (Figure 2, Note 8) Full - - 8 ns Driver Differential Output Skew tDSK RDIFF = 100, CD = 50pF (see Figure 2) Full - 0.5 2 ns Driver Differential Rise or Fall Time tR, tF Driver Single-Ended Output Skew tSSK RDIFF = 100, CD = 50pF (see Figure 2) Full - 7 12 ns tZH SW = GND (see Figure 3, Note 12) Full - - 20 ns Driver Enable to Output Low tZL SW = VCC (see Figure 3, Note 12) Full - - 20 ns Driver Disable from Output High tHZ SW = GND (see Figure 3) Full - - 20 ns tLZ Driver Enable to Output High SW = VCC (see Figure 3) Full - - 20 ns Driver Enable from SHDN to High tSDH ISL32179E Only, SW = GND (see Figure 3, Note 13) Full - - 750 ns Driver Enable from SHDN to Low tSDL ISL32179E Only, SW = VCC (see Figure 3, Note 13) Full - - 750 ns Driver Disable from Output Low NOTES: 6. All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to device ground unless otherwise specified. 7. Applies to peak current. See "Typical Performance Curves" beginning on page 12 for more information. 8. tSKPP is the magnitude of the difference in propagation delays of the specified terminals of two units tested with identical test conditions (VCC, temperature, etc.). 9. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 10. EN = 0 indicates that the output(s) under test are disabled via the appropriate logic pin settings. EN = 1 indicates that the logic pins are set to enable the output(s) under test. 11. Channel-to-channel skew is the magnitude of the worst case delta between any two propagation delays of any two outputs on the same IC, at the same test conditions. 12. For ISL32179E, keep SHDNEN low to avoid entering SHDN. 13. Keep SHDNEN high to enter SHDN when all transmitters are disabled (ISL32179E only). 14. Logic Pins are the DIs, the enable variants, and SHDNEN. 15. Only one of the SPX pins low, plus EN1-EN4 low with EN and EN high, or EN low and EN high with EN1-EN4 high. 16. Temperature range is -20C to +40C. 8 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Test Circuits and Waveforms RL/2 EN VCC OR VL Z DI VOD D Y VOC RL/2 FIGURE 1. DC DRIVER TEST CIRCUITS DI LOWER OF VCC OR VL 1.5V 1.5V 0V tPHL tPLH VOH OUT (Y) VCC OR VL 50% EN tSSK Z DI 50% tSSK tPLH tPHL RDIFF D VOL CD VOH 50% 50% OUT (Z) Y VOL SIGNAL GENERATOR tDDLH DIFF OUT (Y - Z) tDDHL 90% 0V 10% tR -VOD tF tSSK = |tPLH(Y OR Z) - tPHL(Z OR Y)| FIGURE 2A. TEST CIRCUIT +VOD 90% 0V 10% tDSK = |tDDLH - tDDHL| FIGURE 2B. MEASUREMENT POINTS FIGURE 2. DRIVER PROPAGATION DELAY AND DIFFERENTIAL TRANSITION TIMES EN Z DI 110 VCC D SIGNAL GENERATOR SW Y 3V OR VL EN 1.5V 1.5V GND 0V 50pF tZH tSDH tHZ OUTPUT HIGH VOH - 0.5V PARAMETER OUTPUT DI SW tHZ Y/Z 1/0 GND tLZ Y/Z 0/1 VCC tZH (Note 12) Y/Z 1/0 GND tZL (Note 12) Y/Z 0/1 VCC tSDH (Note 13) Y/Z 1/0 GND tSDL (Note 13) Y/Z 0/1 FIGURE 3A. TEST CIRCUIT VOH 50% OUT (Y, Z) 0V tZL tSDL OUT (Y, Z) tLZ VCC 50% OUTPUT LOW VCC VOL + 0.5V V OL FIGURE 3B. MEASUREMENT POINTS FIGURE 3. DRIVER ENABLE AND DISABLE TIMES 9 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Test Circuits and Waveforms (Continued) VCC OR VL EN + Z DI 100 D CD Y LOWER OF VCC OR VL DI 0V VOD - SIGNAL GENERATOR +VOD DIFF OUT (Y - Z) -VOD 0V FIGURE 4B. MEASUREMENT POINTS FIGURE 4A. TEST CIRCUIT FIGURE 4. DRIVER DATA RATE Application Information RS-422 is a differential (balanced) data transmission standard for use in long haul or noisy environments. RS-422 is a point-to-multipoint (multidrop) standard, which allows only one driver and up to 10 (assuming one unit load devices) receivers on each bus. Driver Features These RS-422 drivers are differential output devices that deliver at least 2V across a 100 load. The drivers feature low propagation delay skew to maximize bit width, and to minimize EMI. The 460kbps driver outputs are slew rate limited to minimize EMI, and to reduce reflections in unterminated or improperly terminated networks. Outputs of the 10Mbps and 32Mbps drivers are not limited, so faster output transition times allow the higher data rates. Driver Enable Functions All product types include functionality to allow disabling of the Tx outputs. The ISL32x72E types feature group (all four Tx) enable functions that are active high (EN) or active low (EN). Drivers enable when EN = 1, or when EN = 0, and they disable only when EN = 0 and EN = 1. ISL32x74E versions use active high paired enable functions (EN12 and EN34) that enable (when high) or disable (when low) the corresponding pairs of Tx. All four of these enable pins have internal pull-up resistors to VCC, but unused enable pins that need to be high (e.g., EN when using the EN input for enable control, or EN12 and EN34 when using always enabled drivers) should always be connected externally to VCC. If VCC transients might exceed 7V, then inserting a series resistor between the input(s) and VCC limits the current that will flow if the input's ESD protection starts conducting. The ISL32179E has the most flexible enable scheme. Its six enable pins allow for group, paired, or individual channel enable control. Figure 5 details the ISL32179E's internal enable logic. To utilize a group enable function, connect all the ENx pins high, and handle the EN and EN pins as described in the previous paragraph. For paired enables, connect EN and EN high (for the lowest current in SHDN mode, if SHDN is used) and tie EN1 and EN2 together, and 10 EN3 and EN4 together. For individual channel enables, again connect EN and EN high, and drive the appropriate ENX (active high) for the particular channel. All of the enable pins incorporate pull-up resistors to VCC, but unused enable pins of any type should be externally connected high, rather than being left floating. Connecting to VCC is the best choice, but VL may be utilized as long as SHDN power isn't a primary concern (for each VL connected input, ICC increases by ((VCC - VL)/600k). If VCC or VL transients might exceed 7V, then inserting a series resistor between the input(s) and the supply limits the current that will flow if the input's ESD protection starts conducting. 1 OF 4 CHANNELS ENX VCC VCC CHX EN EN EN VCC FIGURE 5. ISL32179E ENABLE LOGIC Wide Supply Range These ICs are designed to operate with a wide range of supply voltages from 3.0V to 5.5V, and they meet the RS-422 specifications for that full supply voltage range. 5.5V TOLERANT LOGIC PINS Logic input pins (driver inputs, enables, SHDNEN) contain no ESD nor parasitic diodes to VCC (nor to VL), so they withstand input voltages exceeding 5.5V regardless of the VCC and VL voltages. Input voltages up to 7V are easily tolerated. Logic Supply (VL Pin, ISL32179E Only) Note: Power-up VCC before powering up the VL supply. If unused enable pins are connected to VL rather than to VCC, then a small ICC ((VCC - VL)/600k) will flow due to the internal pull-up resistor connecting to VCC. The ISL32179E includes a VL pin that powers the logic inputs (driver inputs, enables, SHDNEN). These pins interface with "logic" devices such as UARTs, ASICs, and FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E controllers, and today most of these devices use power supplies significantly lower than 3.3V. Thus, the logic device's low VOH might not exceed the VIH of a 3.3V or 5V powered DI or enable input. Connecting the VL pin to the power supply of the logic device (as shown in Figure 6) reduces the DI and enable input switching points to values compatible with the logic device's output levels. Tailoring the logic pin input switching points to the supply voltage of the UART, ASIC, or controller eliminates the need for a level shifter/translator between the two ICs. VCC = +3.3V VCC = +2V Hot Plug Function When a piece of equipment powers up, there is a period of time where the processor or ASIC driving the RS-422 control lines (EN, EN, ENx) is unable to ensure that the RS-422 Tx outputs remain disabled. If the equipment is connected to the bus, a driver activating prematurely during power-up may drive invalid data on the bus. To avoid this scenario, this family incorporates a "Hot Plug" function. During power-up, circuitry monitoring VCC ensures that the Tx outputs remain disabled for a period of time, regardless of the state of the enable pins. This gives the processor/ASIC a chance to stabilize and drive the RS-422 control lines to the proper states. ESD Protection VIH 2 DI EN GND TXD VOH 2 VIH 2 DEN VOH 2 ISL32172E GND UART/PROCESSOR VCC = +3.3V VCC = +2V VL DI EN GND VIH = 0.85V TXD VOH 2 VIH = 0.85V DEN VOH 2 ISL32179E All pins on these devices include class 3 (>12kV) Human Body Model (HBM) ESD protection structures, but the RS-422 pins (driver outputs) incorporate advanced structures allowing them to survive ESD events in excess of 15kV HBM, and 16.5kV to IEC61000-4-2. The RS-422 pins are particularly vulnerable to ESD damage because they typically connect to an exposed port on the exterior of the finished product. Simply touching the port pins, or connecting a cable, can cause an ESD event that might destroy unprotected ICs. These new ESD structures protect the device whether or not it is powered up, and without degrading the RS-422 common mode range of -0.3V to +6V. This built-in ESD protection eliminates the need for board level protection structures (e.g., transient suppression diodes), and the associated, undesirable capacitive load they present. IEC61000-4-2 Testing GND UART/PROCESSOR FIGURE 6. USING VL PIN TO ADJUST LOGIC LEVELS VL can be anywhere from VCC down to 1.5V, and Table 2 indicates typical VIH and VIL values for various VL settings so the user can ascertain whether or not a particular VL voltage meets his needs. TABLE 2. VIH AND VIL vs VL FOR VCC = 3.3V OR 5V The IEC61000 test method applies to finished equipment, rather than to an individual IC. Therefore, the pins most likely to suffer an ESD event are those that are exposed to the outside world (the RS-422 pins in this case), and the IC is tested in its typical application configuration (power applied) rather than testing each pin-to-pin combination. The IEC61000 standard's lower current limiting resistor coupled with the larger charge storage capacitor yields a test that is much more severe than the HBM test. The extra ESD protection built into this device's RS-422 pins allows the design of equipment meeting level 4 criteria without the need for additional board level protection on the RS-422 port. VL (V) VIH (V) VIL (V) 1.6 0.7 0.45 2 0.85 0.6 2.3 1.1 0.75 2.7 1.4 (DI), 1.1 (ENs) 0.85 2.7 2 0.8 For this test method, a charged probe tip moves toward the IC pin until the voltage arcs to it. The current waveform delivered to the IC pin depends on approach speed, humidity, temperature, etc., so it is difficult to obtain repeatable results. The RS-422 pins withstand 16.5kV air-gap discharges. 3.3 2.2 0.8 CONTACT DISCHARGE TEST METHOD AIR-GAP DISCHARGE TEST METHOD During the contact discharge test, the probe contacts the tested pin before the probe tip is energized, thereby eliminating the variables associated with the air-gap 11 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E discharge. The result is a more repeatable and predictable test, but equipment limits prevent testing devices at voltages higher than 9kV. Devices in this family survive 9kV contact discharges on the RS-422 pins. Data Rate, Cables, and Terminations exceeds the RS-422 specification. A novel design sets the short circuit current limit depending on the VCC value, so unlike some competing devices, the VCC = 5V short circuit current is only slightly higher than the corresponding VCC = 3.3V level (see Figure 12). RS-422 is intended for network lengths up to 4000', but the maximum system data rate decreases as the transmission length increases. Devices operating at 32Mbps handle lengths up to 328' (100m) in 5V systems, and lengths up to 200' (62m) in 3.3V systems (see Figures 31 and 32). The 460kbps versions can operate at full data rates with lengths of thousands of feet. Note that system jitter requirements may limit a network to shorter distances. In the event of a major short circuit condition, devices also include a thermal shutdown feature that disables the drivers whenever the die temperature becomes excessive. This eliminates the power dissipation, allowing the die to cool. The drivers automatically re-enable after the die temperature drops about 20. If the fault persists, the thermal shutdown/re-enable cycle repeats until the fault is cleared. Twisted pair is the cable of choice for RS-422 networks. Twisted pair cables tend to pick up noise and other electromagnetically induced voltages as common mode signals, which are effectively rejected by the differential receivers in RS-422 ICs. With TA = +125C and VCC = 5.5V, four 100 differentially terminated drivers in the TSSOP package put the IC at the edge of its maximum allowed junction temperature. Using larger termination resistors, a lower maximum supply voltage, or one of the packages with a lower thermal resistance (JA) provides more safety margin. When designing for +125C operation, be sure to measure the application's switching current, and include this in the thermal calculations. Proper termination is imperative, when using the 10Mbps or 32Mbps devices, to minimize reflections. Short networks using the 460kbps versions need not be terminated, but, terminations are recommended unless power dissipation is an overriding concern. In point-to-point, or point-to-multipoint (multiple receivers on bus) networks, the main cable should be terminated in its characteristic impedance (typically 120) at the end farthest from the driver. In multi-receiver applications, stubs connecting receivers to the main cable should be kept as short as possible. Built-In Driver Overload Protection High Temperature Operation Low Power Shutdown Mode (ISL32179E Only) These BiCMOS transmitters all use a fraction of the power required by their bipolar counterparts, but the QFN version includes a shutdown feature that reduces the already low quiescent ICC by 90%. The ISL32179E enters shutdown (SHDN) whenever the SHDNEN pin is high and all four drivers are disabled (see "Pin Descriptions" on page 4). Note that the enable times from SHDN are longer than the enable times when the IC isn't in SHDN. The driver output stages incorporate short circuit current limiting circuitry which ensures that the output current never Typical Performance Curves VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. 4.3 +85C DIFFERENTIAL OUTPUT VOLTAGE (V) DRIVER OUTPUT CURRENT (mA) 110 100 +25C 90 80 +85C 70 +25C 60 +125C 50 +125C 40 30 20 VCC = 3.3V 10 VCC = 5V 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 DIFFERENTIAL OUTPUT VOLTAGE (V) 4.5 5.0 FIGURE 7. DRIVER OUTPUT CURRENT vs DIFFERENTIAL OUTPUT VOLTAGE 12 RDIFF = 100 4.1 VCC = 5V 3.9 3.7 3.5 3.3 3.1 2.9 VCC = 3.3V 2.7 2.5 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 FIGURE 8. DRIVER DIFFERENTIAL OUTPUT VOLTAGE vs TEMPERATURE FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves +25C 140 100 +125C +25C 80 +85C VCC = 3.3V RDIFF = +125C 60 40 20 VOL 0 0 1.0 1.5 2.0 2.5 Y OR Z OUTPUT VOLTAGE (V) +125C +25C +85C 100 60 40 20 VOL 0 0 0.5 VOH 1.0 1.5 2.0 2.5 3.0 3.5 Y OR Z OUTPUT VOLTAGE (V) 150 4.5 5.0 VCC = 5V EN = VCC VCC = 3.3V 100 OUTPUT CURRENT (mA) 450 400 350 300 Y OR Z = LOW 50 0 -50 VCC = 3.3V -100 250 VCC = 3.3V 200 -40 -25 VCC = 5V -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 -150 -0.5 0 Y OR Z = HIGH 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 OUTPUT VOLTAGE (V) FIGURE 12. DRIVER OUTPUT CURRENT vs SHORT CIRCUIT VOLTAGE FIGURE 11. SUPPLY CURRENT vs TEMPERATURE 60 94 VL = 1.6V TO VCC tSSK 92 VCC = 5V 50 90 40 SKEW (ns) PROPAGATION DELAY (ns) 4.0 FIGURE 10. DRIVER SINGLE-ENDED (Y OR Z) OUTPUT CURRENT vs OUTPUT VOLTAGE 500 VCC = 5V VCC = 5V RDIFF = +125C 80 3.0 3.3 FIGURE 9. DRIVER SINGLE-ENDED (Y OR Z) OUTPUT CURRENT vs OUTPUT VOLTAGE ICC (A) 120 VOH 0.5 +25C +85C +85C DRIVER OUTPUT CURRENT (mA) DRIVER OUTPUT CURRENT (mA) 120 VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued) 88 86 tDDLH tSSK VCC = 3.3V 30 VL = 1.6V TO VCC 20 84 tDDHL 10 82 tDSK 80 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 FIGURE 13. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL32372E, ISL32374E, ISL32179E, 460kbps OPTION) 13 0 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) VCC = 3.3V OR 5V 80 95 110 125 FIGURE 14. DRIVER SKEW vs TEMPERATURE (ISL32372E, ISL32374E, ISL32179E, 460kbps OPTION) FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Typical Performance Curves VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued) 20 3.0 VL = 1.6V to VCC 18 17 2.5 tDDLH tSSK VL = 1.6V, VCC = 3.3V OR 5V 16 SKEW (ns) PROPAGATION DELAY (ns) 19 tDDHL 15 14 2.0 1.5 13 12 tDDLH 11 1.0 VL = VCC = 3.3V OR 5V tDSK tDDHL 10 -40 -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 0.5 -40 110 125 FIGURE 15. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL32272E, ISL32274E, ISL32179E, 10Mbps OPTION) -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 FIGURE 16. DRIVER SKEW vs TEMPERATURE (ISL32272E, ISL32274E, ISL32179E, 10Mbps OPTION) 1.2 16 15 1.0 13 tDDLH 12 SKEW (ns) 0.8 VL = 1.6V, VCC = 3.3V OR 5V tDDHL 11 10 tDSK 8 tDDLH tDDHL -25 -10 5 20 35 50 65 TEMPERATURE (C) 80 95 FIGURE 17. DRIVER DIFFERENTIAL PROPAGATION DELAY vs TEMPERATURE (ISL32172E, ISL32174E, ISL32179E, 32Mbps OPTION) VH DI 0 Z 1.5 Y 0 0 Y-Z -1 -2 -3 TIME (40ns/DIV) FIGURE 19. DRIVER WAVEFORMS, LOW TO HIGH (ISL32372E, ISL32374E, ISL32179E) 14 5 20 35 50 65 TEMPERATURE (C) 80 95 110 125 RDIFF = 100, CD = 50pF VH DI 0 3.0 Y 1.5 Z 0 VH = VCC OR VL DRIVER OUTPUT (V) DRIVER OUTPUT (V) 2 -10 FIGURE 18. DRIVER SKEW vs TEMPERATURE (ISL32172E, ISL32174E, ISL32179E, 32Mbps OPTION) VH = VCC OR VL 3 -25 VCC = 3.3V, VL = 1.6V TO VCC RDIFF = 100, CD = 50pF DRIVER INPUT (V) DRIVER OUTPUT (V) VCC = 3.3V, VL = 1.6V TO VCC 0 -40 110 125 DRIVER OUTPUT (V) 6 -40 VL 3V, VCC = 3.3V OR 5V 0.2 VL 3V, VCC = 3.3V OR 5V 7 1 VL = 1.6V to VCC, VCC = 3.3V OR 5V tSSK 0.6 0.4 9 3.0 VL = 1.6V, VCC = 3.3V OR 5V tDSK DRIVER INPUT (V) PROPAGATION DELAY (ns) 14 3 2 1 0 -1 -2 -3 Y-Z TIME (40ns/DIV) FIGURE 20. DRIVER WAVEFORMS, HIGH TO LOW (ISL32372E, ISL32374E, ISL32179E) FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E VCC = 5V, VL = 1.6V TO VCC DI 0 5.0 Z 2.5 Y 0 DRIVER INPUT (V) VH 2 Y-Z 0 5.0 Y 2.5 Z 0 -2 -4 -5 5 4 2 0 Y-Z -2 -4 -5 TIME (40ns/DIV) TIME (40ns/DIV) DI 0 3.0 Z 1.5 Y 0 DRIVER INPUT (V) VH DRIVER OUTPUT (V) VCC = 3.3V, VL = 1.6V TO VCC RDIFF = 100, CD = 50pF 2 1 Y-Z 0 -1 -2 -3 VH DI 0 3.0 Y 1.5 Z 0 3 2 1 0 Y-Z -1 -2 -3 TIME (10ns/DIV) TIME (10ns/DIV) FIGURE 23. DRIVER WAVEFORMS, LOW TO HIGH (ISL32272E, ISL32274E, ISL32179E) FIGURE 24. DRIVER WAVEFORMS, HIGH TO LOW (ISL32272E, ISL32274E, ISL32179E) VH DI 0 5.0 Z 2.5 Y 0 DRIVER OUTPUT (V) VCC = 5V, VL = 1.6V TO VCC RDIFF = 100, CD = 50pF DRIVER INPUT (V) DRIVER OUTPUT (V) VCC = 5V, VL = 1.6V TO VCC RDIFF = 100, CD = 50pF VH = VCC OR VL VH = VCC OR VL 3 DRIVER OUTPUT (V) DRIVER OUTPUT (V) DRIVER OUTPUT (V) VCC = 3.3V, VL = 1.6V TO VCC FIGURE 22. DRIVER WAVEFORMS, HIGH TO LOW (ISL32372E, ISL32374E, ISL32179E) RDIFF = 100, CD = 50pF VH DI 0 5.0 Y 2.5 Z 0 VH = VCC OR VL DRIVER OUTPUT (V) DRIVER OUTPUT (V) VH = VCC OR VL 5 4 2 Y-Z 0 -2 -4 -5 TIME (10ns/DIV) FIGURE 25. DRIVER WAVEFORMS, LOW TO HIGH (ISL32272E, ISL32274E, ISL32179E) 15 DRIVER INPUT (V) FIGURE 21. DRIVER WAVEFORMS, LOW TO HIGH (ISL32372E, ISL32374E, ISL32179E) DRIVER INPUT (V) 0 VH DI VH = VCC OR VL VH = VCC OR VL 5 4 RDIFF = 100, CD = 50pF DRIVER INPUT (V) RDIFF = 100, CD = 50pF DRIVER OUTPUT (V) DRIVER OUTPUT (V) DRIVER OUTPUT (V) VCC = 5V, VL = 1.6V TO VCC VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued) DRIVER OUTPUT (V) Typical Performance Curves 5 4 2 0 Y-Z -2 -4 -5 TIME (10ns/DIV) FIGURE 26. DRIVER WAVEFORMS, HIGH TO LOW (ISL32272E, ISL32274E, ISL32179E) FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E VH DI 0 Z 1.5 Y 0 DRIVER OUTPUT (V) DRIVER OUTPUT (V) 2 Y-Z 0 -1 -2 -3 0 3.0 Y 1.5 Z 0 3 2 1 0 Y-Z -1 -2 -3 TIME (10ns/DIV) TIME (10ns/DIV) FIGURE 28. DRIVER WAVEFORMS, HIGH TO LOW (ISL32172E, ISL32174E, ISL32179E) DI 0 5.0 Z 2.5 Y 0 VCC = 5V, VL = 1.6V TO VCC RDIFF = 100, CD = 50pF VH DI 0 5.0 Y 2.5 Z 0 VH = VCC OR VL 5 4 2 DRIVER INPUT (V) VH DRIVER OUTPUT (V) RDIFF = 100, CD = 50pF VH = VCC OR VL DRIVER OUTPUT (V) DRIVER OUTPUT (V) DRIVER OUTPUT (V) FIGURE 27. DRIVER WAVEFORMS, LOW TO HIGH (ISL32172E, ISL32174E, ISL32179E) VCC = 5V, VL = 1.6V TO VCC VH DI VH = VCC OR VL VH = VCC OR VL 3 1 RDIFF = 100, CD = 50pF Y-Z 0 -2 -4 -5 TIME (10ns/DIV) FIGURE 29. DRIVER WAVEFORMS, LOW TO HIGH (ISL32172E, ISL32174E, ISL32179E) 16 DRIVER INPUT (V) 3.0 VCC = 3.3V, VL = 1.6V TO VCC DRIVER INPUT (V) RDIFF = 100, CD = 50pF DRIVER INPUT (V) DRIVER OUTPUT (V) VCC = 3.3V, VL = 1.6V TO VCC VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued) DRIVER OUTPUT (V) Typical Performance Curves 5 4 2 0 Y-Z -2 -4 -5 TIME (10ns/DIV) FIGURE 30. DRIVER WAVEFORMS, HIGH TO LOW (ISL32172E, ISL32174E, ISL32179E) FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E 3 DI DRIVER OUTPUT (V) DRIVER OUTPUT (V) 0 DRIVER + CABLE DELAY (~288ns) 3.0 1.5 Y-Z 0 -1.5 -3.0 3.0 +85C 1.5 Y-Z 0 -1.5 +125C -3.0 TIME (80ns/DIV) FIGURE 31. WORST CASE (NEGATIVE) FIVE PULSE DRIVER WAVEFORMS DRIVING 200 FEET (62m) OF CAT5 CABLE (SINGLE TERMINATED WITH 121) (ISL32172E, ISL32174E, ISL32179E) 32Mbps VCC = VL = 4.5V 5 DI 0 DRIVER OUTPUT (V) DRIVER OUTPUT (V) 32Mbps VCC = VL = 3V DRIVER + CABLE DELAY 4.5 3.0 1.5 0 -1.5 -3.0 -4.5 4.5 3.0 1.5 0 -1.5 -3.0 -4.5 (~472ns) DRIVER INPUT (V) VCC = VL = 3.3V or 5V, TA = +25C; Unless Otherwise Specified. VL notes apply to the ISL32179E only. (Continued) DRIVER INPUT (V) Typical Performance Curves Y-Z +85C Y-Z +125C TIME (80ns/DIV) FIGURE 32. WORST CASE (NEGATIVE) FIVE PULSE DRIVER WAVEFORMS DRIVING 328 FEET (100m) OF CAT5 CABLE (SINGLE TERMINATED WITH 121) (ISL32172E, ISL32174E, ISL32179E) Die Characteristics SUBSTRATE AND QFN THERMAL PAD POTENTIAL (POWERED UP): GND TRANSISTOR COUNT: 1682 PROCESS: Si Gate BiCMOS 17 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Small Outline Plastic Packages (SOIC) M16.15 (JEDEC MS-012-AC ISSUE C) N INDEX AREA H 0.25(0.010) M 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE B M INCHES E -B1 2 3 L SEATING PLANE -A- A D h x 45 -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M SYMBOL MIN MAX MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.3859 0.3937 9.80 10.00 3 E 0.1497 0.1574 3.80 4.00 4 e B S 0.050 BSC - 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 1.27 BSC H N NOTES: MILLIMETERS 16 0 16 8 0 7 8 Rev. 1 6/05 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 18 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Package Outline Drawing L24.4x4C 24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 2, 10/06 4X 2.5 4.00 A 20X 0.50 B PIN 1 INDEX AREA PIN #1 CORNER (C 0 . 25) 24 19 1 4.00 18 2 . 50 0 . 15 13 0.15 (4X) 12 7 0.10 M C A B 0 . 07 24X 0 . 23 +- 0 . 05 4 24X 0 . 4 0 . 1 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C C 0 . 90 0 . 1 BASE PLANE ( 3 . 8 TYP ) SEATING PLANE 0.08 C SIDE VIEW ( 2 . 50 ) ( 20X 0 . 5 ) C 0 . 2 REF 5 ( 24X 0 . 25 ) 0 . 00 MIN. 0 . 05 MAX. ( 24X 0 . 6 ) DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 19 FN6824.0 December 16, 2008 ISL32172E, ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E Thin Shrink Small Outline Package Family (TSSOP) MDP0044 0.25 M C A B D THIN SHRINK SMALL OUTLINE PACKAGE FAMILY A (N/2)+1 N MILLIMETERS SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE PIN #1 I.D. E E1 1 (N/2) B 0.20 C B A 2X N/2 LEAD TIPS TOP VIEW 0.05 e C SEATING PLANE H A 1.20 1.20 1.20 1.20 1.20 Max A1 0.10 0.10 0.10 0.10 0.10 0.05 A2 0.90 0.90 0.90 0.90 0.90 0.05 b 0.25 0.25 0.25 0.25 0.25 +0.05/-0.06 c 0.15 0.15 0.15 0.15 0.15 +0.05/-0.06 D 5.00 5.00 6.50 7.80 9.70 0.10 E 6.40 6.40 6.40 6.40 6.40 Basic E1 4.40 4.40 4.40 4.40 4.40 0.10 e 0.65 0.65 0.65 0.65 0.65 Basic L 0.60 0.60 0.60 0.60 0.60 0.15 L1 1.00 1.00 1.00 1.00 1.00 Reference Rev. F 2/07 0.10 M C A B b 0.10 C N LEADS SIDE VIEW NOTES: 1. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.15mm per side. 2. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm per side. SEE DETAIL "X" 3. Dimensions "D" and "E1" are measured at dAtum Plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. c END VIEW L1 A A2 GAUGE PLANE 0.25 L A1 0 - 8 DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 20 FN6824.0 December 16, 2008