CY7C1484BV25-250AXI - CYPRESS SEMICONDUCTOR

CY7C1484BV25

72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-75258 Rev. *D Revised January 4, 2016

72-Mbit (2 M × 36) Pipeline d DCD Sync SRAM

Features

■Supports bus operation up to 250 MHz

■Available speed grades are 250 MHz

■Registered inputs and outputs for pipelined operation

■Optimal for performance (double cycle deselect)

■Depth expansion without wait state

■2.5 V core power supply (VDD)

■2.5 V I/O supply (VDDQ)

■Fast clock to output times

❐3.0 ns (for 250 MHz device)

■Provide high performance 3-1-1-1 access rate

■User selectable burst counter supporting Intel® Pentium®

interleaved or linear burst sequences

■Separate processor and controller address strobes

■Synchronous self timed writes

■Asynchronous output enable

■CY7C1484BV25 available in JEDEC-standard Pb-free 100-pin

TQFP package

■“ZZ” sleep mode option

Functional Description

The CY7C1484BV25 SRAM integrates 2 M × 36 SRAM cells with

advanced synchronous peripheral circuitry and a 2-bit counter

for internal burst operation. All synchronous inputs are gated by

registers controlled by a positive edge triggered Clock Input

(CLK). The synchronous inputs include all addresses, all data

inputs, address pipelining Chip Enable (CE1), depth expansion

Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,

ADSP

, and ADV), Write Enables (BWX and BWE), and Global

Write (GW). Asynchronous inputs include the Output Enable

(OE) and the ZZ pin.

Addresses and chip enables are registered at the rising edge of

clock when either Address Strobe Processor (ADSP) or Address

Strobe Controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate a self timed write cycle. This part supports byte write

operations (see Pin Definitions on page 5 and Truth Table on

page 8 for more information). Write cycles can be one to four

bytes wide as controlled by the byte write control inputs. GW

active LOW causes all bytes to be written. This device

incorporates an additional pipelined enable register, which

delays turning off the output buffers an additional cycle when a

deselect is executed. This feature allows depth expansion

without penalizing system performance.

For a complete list of related documentation, click here.

Selection Guide

Description 250 MHz Unit

Maximum Access Time 3.0 ns

Maximum Operating Current 450 mA

Maximum CMOS Standby Current 120 mA

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 2 of 21

Logic Block Diagram – CY7C1484BV25

ADDRESS

ADV

CLK

BURST

COUNTER AND

LOGIC

CLR

ADSP

ADSC

MODE

BW D

BW C

BW B

BW A

BWE

CE1

CE2

CE3

DQ D, DQP D

BYTE

WRITE REGISTER

DQ c,DQP C

BYTE

WRITE REGISTER

DQ B,DQP B

BYTE

WRITE REGISTER

DQ A, DQP A

BYTE

WRITE REGISTER

ENABLE

OUTPUT

REGISTERS

SENSE

AMPS

MEMORY

ARRAY OUTPUT

BUFFERS

DQ A, DQP A

BYTE

WRITE DRIVER

DQ B,DQP B

BYTE

WRITE DRIVER

DQ c,DQP C

BYTE

WRITE DRIVER

DQ D, DQP D

BYTE

WRITE DRIVER

INPUT

REGISTERS

A0,A1,A

A[1:0]

SLEEP

CONTROL

DQs

DQP

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 3 of 21

Contents

Pin Configurations ...........................................................4

Pin Definitions ..................................................................5

Functional Overview ........................................................6

Single Read Accesses ................................................6

Single Write Accesses Initiated by ADSP ................... 6

Single Write Accesses Initiated by ADSC ...................6

Burst Sequences .........................................................6

Sleep Mode .................................................................7

Interleaved Burst Address Table

(MODE = Floating or VDD) ................................................. 7

Linear Burst Address Table (MODE = GND) ...............7

ZZ Mode Electrical Characteristics ..............................7

Truth Table ........................................................................8

Truth Table for Read/Write .............................................. 9

Maximum Ratings ........................................................... 10

Operating Range ............................................................. 10

Electrical Characteristics ...............................................10

Capacitance .................................................................... 11

Thermal Resistance ........................................................11

AC Test Loads and Waveforms ..................................... 11

Switching Characteristics .............................................. 12

Switching Waveforms .................................................... 13

Ordering Information ...................................................... 17

Ordering Code Definitions ......................................... 17

Package Diagrams .......................................................... 18

Acronyms ........................................................................ 19

Document Conventions ................................................. 19

Units of Measure ....................................................... 19

Document History Page ................................................. 20

Sales, Solutions, and Legal Information ...................... 21

Worldwide Sales and Design Support ....................... 21

Products .................................................................... 21

PSoC® Solutions ...................................................... 21

Cypress Developer Community ................................. 21

Technical Support ..................................................... 21

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 4 of 21

Pin Configurations

Figure 1. 100-pin TQFP (14 × 20 × 1.4 mm) pinout

VSS

VDD

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1484BV25

(2 M × 36)

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 5 of 21

Pin Definitions

Pin Name I/O Description

A0, A1, A Input-

Synchronous

Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the

CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1:A0 are fed to the

2-bit counter.

BWA, BWB,

BWC, BWD

Input-

Synchronous

Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM.

Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write

is conducted (ALL bytes are written, regardless of the values on BWX and BWE).

BWE Input-

Synchronous

Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a byte write.

CLK Input-

Clock

Clock Input. Captures all synchronous inputs to the device. Also used to increment the burst counter

when ADV is asserted LOW during a burst operation.

CE1Input-

Synchronous

Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2

and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a

new external address is loaded.

CE2Input-

Synchronous

Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded.

CE3Input-

Synchronous

Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1

and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded.

OE Input-

Asynchronou

Output Enable, Asynchronous Input, Active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input data

pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV Input-

Synchronous

Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is

ignored when CE1 is deasserted HIGH.

ADSC Input-

Synchronous

Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1:A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ Input-

Asynchronou

ZZ “Sleep” Input, Active HIGH. When asserted HIGH, places the device in a non time-critical “sleep”

condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ

pin has an internal pull down.

DQs,

DQPs

I/O-

Synchronous

Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous clock rise of the read cycle. The direction of the pins is

controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX

are placed in a tri-state condition.

VDD Power Supply Power Supply Inputs to the Core of the Device.

VSS Ground Ground for the Core of the Device.

VSSQ[1] I/O Ground Ground for the I/O Circuitry.

VDDQ I/O Power

Supply

Power Supply for the I/O Circuitry.

Note

1. Applicable for TQFP package.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 6 of 21

Functional Overview

All synchronous inputs pass through input registers controlled by

the rising edge of the clock. All data outputs pass through output

registers controlled by the rising edge of the clock.

The CY7C1484BV25 supports secondary cache in systems

using either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486™ processors.

The linear burst sequence is suited for processors that use a

linear burst sequence. The burst order is user selectable and is

determined by sampling the MODE input. Accesses are initiated

with either the ADSP or ADSC. The ADV input controls address

advancement through the burst sequence. A 2-bit on-chip

wraparound burst counter captures the first address in a burst

sequence and automatically increments the address for the rest

of the burst access.

Byte write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BWX) inputs. GW overrides all

byte write inputs and writes data to all four bytes. All writes are

simplified with on-chip synchronous self timed write circuitry.

Synchronous Chip Selects CE1, CE2, CE3, and an asynchronous

Output Enable (OE) provide easy bank selection and output

tri-state control. ADSP is ignored if CE1 is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) chip selects are all asserted active, and (3) the write signals

(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is

HIGH. The address presented to the address inputs is stored into

the address advancement logic and the address register while

being presented to the memory core. The corresponding data is

allowed to propagate to the input of the output registers. At the

rising edge of the next clock the data is allowed to propagate

through the output register and onto the data bus within tco if OE

is active LOW. The only exception occurs when the SRAM is

emerging from a deselected state to a selected state; its outputs

are always tri-stated during the first cycle of the access. After the

first cycle of the access, the OE signal controls the outputs.

Consecutive single read cycles are supported.

The CY7C1484BV25 is a double cycle deselect part. After the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output tri-states immediately after the

next clock rise.

Single Write Accesses Initiated by ADSP

This access is initiated when both the following conditions are

satisfied at clock rise: (1) ADSP is asserted LOW and (2) chip

select is asserted active. The address presented is loaded into

the address register and the address advancement logic while

being delivered to the memory core. The write signals (GW,

BWE, and BWX) and ADV inputs are ignored during this first

cycle.

ADSP triggered write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQx inputs is written into the

corresponding address location in the memory core. If GW is

HIGH, then the BWE and BWX signals control the write

operation. The CY7C1484BV25 provides byte write capability

that is described in the Truth Table for Read/Write on page 9.

Asserting BWE with the selected Byte Write input selectively

writes to only the desired bytes. Bytes not selected during a byte

write operation remain unaltered. A synchronous self timed write

mechanism is provided to simplify the write operations.

Because the CY7C1484BV25 is a common I/O device, the

Output Enable (OE) must be deasserted HIGH before presenting

data to the DQ inputs. Doing so tri-states the output drivers. As

a safety precaution, DQ are automatically tri-stated whenever a

write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC write accesses are initiated when the following conditions

are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted

HIGH, (3) chip select is asserted active, and (4) the appropriate

combination of the write inputs (GW, BWE, and BWX) are

asserted active to conduct a write to the desired byte(s). ADSC

triggered write accesses require a single clock cycle to complete.

The address presented is loaded into the address register and

the address advancement logic while being delivered to the

memory core. The ADV input is ignored during this cycle. If a

global write is conducted, the data presented to the DQX is

written into the corresponding address location in the memory

core. If a byte write is conducted, only the selected bytes are

written. Bytes not selected during a byte write operation remain

unaltered. A synchronous self timed write mechanism is

provided to simplify the write operations.

Because the CY7C1484BV25 is a common I/O device, the

Output Enable (OE) must be deasserted HIGH before presenting

data to the DQX inputs. Doing so tri-states the output drivers. As

a safety precaution, DQX are automatically tri-stated whenever

a write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1484BV25 provides a 2-bit wraparound counter, fed

by A[1:0], that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed

MODE Input-

Static

Selects Burst Order. When tied to GND, selects linear burst sequence. When tied to VDD or left floating,

selects interleaved burst sequence. This is a strap pin and must remain static during device operation.

Mode Pin has an internal pull up.

NC – No Connects. Not internally connected to the die

NC(144M,

288M,

576M, 1G)

–These Pins are Not Connected. They are used for expansion to the 144M, 288M, 576M, and 1G

densities.

Pin Definitions (continued)

Pin Name I/O Description

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 7 of 21

specifically to support Intel Pentium applications. The linear

burst sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input. Both read and write burst operations

are supported.

Asserting ADV LOW at clock rise automatically increments the

burst counter to the next address in the burst sequence. Both

read and write burst operations are supported.

Sleep Mode

The ZZ input pin is asynchronous. Asserting ZZ places the

SRAM in a power conservation “sleep” mode. Two clock cycles

are required to enter into or exit from this “sleep” mode. While in

this mode, data integrity is guaranteed. Accesses pending when

entering the “sleep” mode are not considered valid nor is the

completion of the operation guaranteed. The device must be

deselected before entering the “sleep” mode. CEs, ADSP, and

ADSC must remain inactive for the duration of tZZREC after the

ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD– 0.2 V – 120 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2 V – 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2 V 2tCYC –ns

tZZI ZZ Active to sleep current This parameter is sampled – 2tCYC ns

tRZZI ZZ Inactive to exit sleep current This parameter is sampled 0 – ns

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 8 of 21

Truth Table

The truth table for CY7C1484BV25 follows. [2, 3, 4, 5, 6]

Operation Address Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselect Cycle, Power Down None H X X L X L X X X L–H Tri-State

Deselect Cycle, Power Down None L L X L L X X X X L–H Tri-State

Deselect Cycle, Power Down None L X H L L X X X X L–H Tri-State

Deselect Cycle, Power Down None L L X L H L X X X L–H Tri-State

Deselect Cycle, Power Down None L X H L H L X X X L–H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

Read Cycle, Begin Burst External L H L L L X X X L L–H Q

Read Cycle, Begin Burst External L H L L L X X X H L–H Tri-State

Write Cycle, Begin Burst External L H L L H L X L X L–H D

Read Cycle, Begin Burst External L H L L H L X H L L–H Q

Read Cycle, Begin Burst External L H L L H L X H H L–H Tri-State

Read Cycle, Continue Burst Next X X X L H H L H L L–H Q

Read Cycle, Continue Burst Next X X X L H H L H H L–H Tri-State

Read Cycle, Continue Burst Next H X X L X H L H L L–H Q

Read Cycle, Continue Burst Next H X X L X H L H H L–H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L–H D

Write Cycle, Continue Burst Next H X X L X H L L X L–H D

Read Cycle, Suspend Burst Current X X X L H H H H L L–H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L–H Tri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L–H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L–H Tri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L–H D

Write Cycle, Suspend Burst Current H X X L X H H L X L–H D

Notes

2. X = Don't Care, H = Logic HIGH, L = Logic LOW.

3. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H.

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the

ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't care for the

remainder of the write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive

or when the device is deselected, and all data bits behave as output when OE is active (LOW).

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 9 of 21

Truth Table for Read/Write

The read/write truth table for CY7C1484BV25 follows. [7, 8]

Function GW BWE BWDBWCBWBBWA

Read H H X X X X

Read HLHHHH

Write Byte A – (DQA and DQPA)HLHHHL

Write Byte B – (DQB and DQPB)HLHHLH

Write Bytes B, A H L H H L L

Write Byte C – (DQC and DQPC)HLHLHH

Write Bytes C, A H L H L H L

Write Bytes C, B H L H L L H

Write Bytes C, B, A H L H L L L

Write Byte D – (DQD and DQPD)HLLHHH

Write Bytes D, A H L L H H L

Write Bytes D, B H L L H L H

Write Bytes D, B, A H L L H L L

Write Bytes D, C H L L L H H

Write Bytes D, C, A H L L L H L

Write Bytes D, C, B H L L L L H

Write All Bytes H L L L L L

Write All Bytes L X X X X X

Notes

7. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

8. Table includes only a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write is based on which byte write is active.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 10 of 21

Maximum Ratings

Exceeding the maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ............................... –65 C to +150 C

Ambient Temperature with

Power Applied ......................................... –55 C to +125 C

Supply Voltage on VDD Relative to GND .....–0.5 V to +3.6 V

Supply Voltage on VDDQ Relative to GND .... –0.5 V to +VDD

DC Voltage Applied to Outputs

in Tri-State ........................................–0.5 V to VDDQ + 0.5 V

DC Input Voltage ................................ –0.5 V to VDD + 0.5 V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage

(MIL-STD-883, Method 3015) ................................. >2001 V

Latch Up Current ................................................... >200 mA

Operating Range

Range Ambient

Temperature VDD VDDQ

Commercial 0 °C to +70 °C 2.5 V– 5% /

+ 5%

2.5 V– 5% to

VDD

Industrial –40 °C to +85 °C

Electrical Characteristics

Over the Operating Range

Parameter [9, 10] Description Test Conditions Min Max Unit

VDD Power Supply Voltage 2.375 2.625 V

VDDQ I/O Supply Voltage For 2.5 V I/O 2.375 VDD V

VOH Output HIGH Voltage For 2.5 V I/O, IOH = –1.0 mA 2.0 – V

VOL Output LOW Voltage For 2.5 V I/O, IOL = 1.0 mA – 0.4 V

VIH Input HIGH Voltage [9] For 2.5 V I/O 1.7 VDD + 0.3 V V

VIL Input LOW Voltage [9] For 2.5 V I/O –0.3 0.7 V

IXInput Leakage Current except ZZ

and MODE

GND  VI  VDDQ –5 5 A

Input Current of MODE Input = VSS –30 – A

Input = VDD –5A

Input Current of ZZ Input = VSS –5 – A

Input = VDD –30A

IOZ Output Leakage Current GND  VI  VDDQ, Output Disabled –5 5 A

IDD [11] VDD Operating Supply Current VDD = Max., IOUT = 0 mA,

f = fMAX = 1/tCYC

4.0 ns cycle,

250 MHz

–450mA

ISB1 Automatic CE Power Down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN  VIH or VIN  VIL,

f = fMAX = 1/tCYC

4.0 ns cycle,

250 MHz

–200mA

ISB2 Automatic CE Power Down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN  0.3 V or VIN > VDDQ – 0.3 V,

f = 0

4.0 ns cycle,

250 MHz

–120mA

ISB3 Automatic CE Power Down

Current—CMOS Inputs

VDD = Max, Device Deselected,

VIN  0.3 V or VIN > VDDQ – 0.3 V,

f = fMAX = 1/tCYC

4.0 ns cycle,

250 MHz

–200mA

ISB4 Automatic CE Power Down

Current—TTL Inputs

VDD = Max, Device Deselected,

VIN  VIH or VIN  VIL, f = 0

4.0 ns cycle,

250 MHz

–135mA

Notes

9. Overshoot: VIH(AC) < VDD + 1.5 V (pulse width less than tCYC/2). Undershoot: VIL(AC) > –2 V (pulse width less than tCYC/2).

10. Power up: assumes a linear ramp from 0 V to VDD(minimum) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

11. The operation current is calculated with 50% read cycle and 50% write cycle.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 11 of 21

Capacitance

Parameter [12] Description Test Conditions 100-pin TQFP

Package Unit

CADDRESS Address Input Capacitance TA = 25 C, f = 1 MHz, VDD = 2.5 V, VDDQ = 2.5 V 6 pF

CDATA Data Input Capacitance 5pF

CCTRL Control Input Capacitance 8pF

CCLK Clock Input Capacitance 6pF

CIO Input/Output Capacitance 5pF

Thermal Resistance

Parameter [12] Description Test Conditions 100-pin TQFP

Package Unit

JA Thermal resistance

(junction to ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA/JESD51.

24.63 C/W

JC Thermal resistance

(junction to case)

2.28 C/W

AC Test Loads and Waveforms

Figure 2. AC Test Loads and Waveforms

OUTPUT

R = 1667

R = 1583

5pF

INCLUDING

JIG AND

SCOPE

(a) (b)

OUTPUT

RL= 50

Z0= 50

= 1.25V

2.5V ALL INPUT PULSES

VDDQ

GND

90%

10%

90%

10%

1 ns 1 ns

(c)

2.5 V I/O Test Load

Note

12. Tested initially and after any design or process change that may affect these parameters.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 12 of 21

Switching Characteristics

Over the Operating Range

Parameter [13, 14] Description 250 MHz Unit

Min Max

tPOWER VDD(typical) to the First Access [15] 1–ms

Clock

tCYC Clock Cycle Time 4.0 – ns

tCH Clock HIGH 2.0 – ns

tCL Clock LOW 2.0 – ns

Output Times

tCO Data Output Valid After CLK Rise – 3.0 ns

tDOH Data Output Hold After CLK Rise 1.3 – ns

tCLZ Clock to Low Z [16, 17, 18] 1.3 – ns

tCHZ Clock to High Z [16, 17, 18] –3.0ns

tOEV OE LOW to Output Valid – 3.0 ns

tOELZ OE LOW to Output Low Z [16, 17, 18] 0–ns

tOEHZ OE HIGH to Output High Z [16, 17, 18] –3.0ns

Setup Times

tAS Address Setup Before CLK Rise 1.4 – ns

tADS ADSC, ADSP Setup Before CLK Rise 1.4 – ns

tADVS ADV Setup Before CLK Rise 1.4 – ns

tWES GW, BWE, BWX Setup Before CLK Rise 1.4 – ns

tDS Data Input Setup Before CLK Rise 1.4 – ns

tCES Chip Enable Setup Before CLK Rise 1.4 – ns

Hold Times

tAH Address Hold After CLK Rise 0.4 – ns

tADH ADSP, ADSC Hold After CLK Rise 0.4 – ns

tADVH ADV Hold After CLK Rise 0.4 – ns

tWEH GW, BWE, BWX Hold After CLK Rise 0.4 – ns

tDH Data Input Hold After CLK Rise 0.4 – ns

tCEH Chip Enable Hold After CLK Rise 0.4 – ns

Notes

13. Timing reference level is 1.25 V when VDDQ = 2.5 V.

14. Test conditions shown in (a) of Figure 2 on page 11 unless otherwise noted.

15. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially before a read or write operation can be initiated.

16. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 2 on page 11. Transition is measured ±200 mV from steady-state voltage.

17. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data

bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve

High Z before Low Z under the same system conditions.

18. This parameter is sampled and not 100% tested.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 13 of 21

Switching Waveforms

Figure 3. Read Cycle Timing [19]

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

W, BWE,BW

Data Out (DQ) High-Z

tDOH

tCO

ADV

tOEHZ

tCO

Single READ BURST READ

tOEV

tOELZ tCHZ

Burst wraps around

to its initial state

tADVH

tADVS

tWEH

tWES

tADH

tADS

Q(A2)

Q(A2 + 1)

Q(A2 + 2)

Q(A1) Q(A2)

Q(A2 + 1)

Q(A3)

Q(A2 + 3)

A2 A3

Deselect

cycle

Burst continued with

new base address

ADV suspends burst

DON’T CARE UNDEFINED

CLZ

Note

19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 14 of 21

Figure 4. Write Cycle Timing [20, 21]

Switching Waveforms (continued)

tCYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

BWE,

ADV

BURST READ BURST WRITE

D(A2)

D(A2 + 1)

D(A3)

D(A3 + 1)

D(A3 + 2)

D(A2 + 3)

A2 A3

Extended BURST WRITE

D(A2 + 2)

Single WRITE

tADH

tADS

tADH

tADS

OEHZ

tADVH

tADVS

tWEH

tWES

tDS

tWEH

tWES

Byte write signals are ignored for rst cycle when

ADSP initiates burst

ADSC extends burst

ADV suspends burst

DON’T CARE UNDEFINED

D(A1)

High-Z

Data in (D)

ata Out (Q)

Notes

20. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.

21. Full width write is initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 15 of 21

Figure 5. Read/Write Cycle Timing [22, 23, 24]

Switching Waveforms (continued)

CYC

tCL

CLK

ADSP

tADH

tADS

ADDRESS

tCH

ADSC

tAH

tAS

tCEH

tCES

ata Out (Q) High-Z

ADV

Single WRITE

D(A3)

A4 A5 A6

D(A5) D(A6)

Data In (D)

BURST READ

Back-to-Back READs

High-Z

Q(A2)Q(A1) Q(A4)

Q(A4+1) Q(A4+2)

tWEH

tWES

Q(A4+3)

tOEHZ

tDH

tDS

tOELZ

tCLZ

tCO

Back-to-Back

WRITEs

BWE, BW

DON’T CARE UNDEFINED

Notes

22. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.

23. The data bus (Q) remains in High Z following a write cycle unless a new read access is initiated by ADSP or ADSC.

24. GW is HIGH.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 16 of 21

Figure 6. ZZ Mode Timing [25, 26]

Switching Waveforms (continued)

tZZ

SUPPLY

CLK

tZZREC

LL INPUTS

(except ZZ)

DON’T CARE

IDDZZ

tZZI

tRZZI

Outputs (Q)

High-Z

DESELECT or READ Only

Notes

25. Device must be deselected when entering ZZ mode. See Truth Table on page 8 for all possible signal conditions to deselect the device.

26. DQs are in High Z when exiting ZZ sleep mode.

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 17 of 21

Ordering Code Definitions

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit

www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

Package

Diagram Part and Package Type Operating

Range

250 CY7C1484BV25-250AXI 51-85050 100-pin TQFP (14 × 20 × 1.4 mm) Pb-free Industrial

Temperature Grade:

I = Industrial

Pb-free

Package Type: A = 100-pin TQFP

Frequency Range: 250 MHz

V25 = 2.5 V

Die Revision

Part Identifier: 1484 = DCD, 2 Mb × 36 (72 Mb)

Technology Code: C = CMOS

Marketing Code: 7 = SRAM

Company ID: CY = Cypress

CCY 1484 V25 -250 X

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 18 of 21

Package Diagrams

Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm) A100RA Package Outline, 51-85050

51-85050 *E

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 19 of 21

Acronyms Document Conventions

Units of Measure

Acronym Description

CE Chip Enable

CMOS Complementary Metal Oxide Semiconductor

EIA Electronic Industries Alliance

I/O Input/Output

JEDEC Joint Electron Devices Engineering Council

OE Output Enable

SRAM Static Random Access Memory

TQFP Thin Quad Flat Pack

TTL Transistor-Transistor Logic

Symbol Unit of Measure

°C degree Celsius

MHz megahertz

µA microampere

mA milliampere

mm millimeter

ms millisecond

mV millivolt

ns nanosecond

ohm

% percent

pF picofarad

Vvolt

Wwatt

CY7C1484BV25

Document Number: 001-75258 Rev. *D Page 20 of 21

Document History Page

Document Title: CY7C1484BV25, 72-Mbit (2 M × 36) Pipelined DCD Sync SRAM

Document Number: 001-75258

Rev. ECN No. Issue Date Orig. of

Change Description of Change

** 3489504 01/10/2012 GOPA New data sheet.

*A 3756097 09/27/2012 PRIT Changed status from Preliminary to Final.

*B 3861547 01/08/2013 PRIT No technical updates.

Completing Sunset Review.

*C 4573182 11/18/2014 PRIT Updated Functional Description:

Added “For a complete list of related documentation, click here.” at the end.

Updated Package Diagrams:

spec 51-85050 – Changed revision from *D to *E.

*D 5071123 01/04/2016 PRIT Updated to new template.

Completing Sunset Review.

Document Number: 001-75258 Rev. *D Revised January 4, 2016 Page 21 of 21

All products and company names mentioned in this document may be the trademarks of their respective holders.

CY7C1484BV25

any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for

medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as

critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems

application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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