M27C1001-12C6TR - STMicroelectronics

1/17June 2002

M27C1001

1 Mbit (128Kb x8) UV EPROM and OTP EPROM

■5V ± 10% SUPPLY VOLTAG E in READ

OPERATION

■ACCESS TIME: 35ns

■LOW POWER CONSUM PTION:

– Active Current 30mA at 5Mhz

– Standby Current 100µ A

■PROGRAMMING VOLTAGE: 12.75V ± 0.25V

■PRO GRAMMING TI ME: 1 00µs/wor d

■ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

– Devi ce Code: 05h

DESCRIPTION

The M 27C1001 is a 1 Mbit E P ROM of fered i n t he

two ranges UV (ultra violet erase) and OTP (one

time programmable). It is ideally suited for micro-

processor systems requiring large programs and

is organized as 131,072 words of 8 bits.

The FDIP32W (window ceramic frit-seal package)

and the LCCC32W (leadless chip carrier package)

have a transparent lids which allow the user to ex-

pose the chip to ultr aviolet light to erase the bit pat -

tern. A new pattern can then be written to the

device by following the programming procedure.

For applications where the content is programmed

only one time and erasure is not required, the

M27C1001 is offered in PDIP32, PLCC32 and

TSOP32 (8 x 20 mm) packages .

Figure 1. Logic Diagram

AI00710B

A0-A16

Q0-Q7

VPP

VCC

M27C1001

VSS

32 32

FDIP32W (F) PDIP32 (B)

PLCC32 (C) TSOP32 (N)

8 x 20 mm

LCCC32W (L)

M27C1001

2/17

Figure 2B. LCC Connections

AI00712

A10

A16

A11

A13

A12

VPP

VCC

M27C1001

A15

A14

VSS

Figure 2A. DIP Connections

A13

A10

A14

A11

Q5Q1

Q2 Q3VSS Q4

PA16

A12

VPP VCC

A15

AI00711

M27C1001

Figure 2C. TSOP Connections

A4 A3

A13

A10

A14

A11 G

A16

A12

VPP

VCC

A15

AI01151B

M27C1001

(Normal)

16 17

VSS

Table 1. Signal Names

A0-A16 Address Inputs

Q0-Q7 Data Outputs

EChip Enable

GOutput Enable

PProgram

VPP Program Supp ly

VCC Supply Voltage

VSS Ground

NC Not Connected Internally

3/17

M27C1001

Table 2. Absolute Maximum Ratings (1)

Note: 1. Exc ept for th e ratin g "Oper ating T em perature Range", stres ses above those listed in t he Tab l e " Absolute Maximum Ratings" may

cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions

above thos e indicated in t he Op erating sect i ons of this specification is not i m plied. Ex posure to A bsolute Ma ximum Rating condi-

tions for extended pe riods may aff ect device reliabilit y. Refer also to the STMic roelectronics SURE Pr ogra m and other relevant qual-

i ty do cu m ent s .

2. Minimum DC voltage on Inpu t or Output is –0.5V with po ssible under sh oot to –2.0V for a period less th an 20ns. Maximum DC

voltage on O ut put is VCC +0.5V with po ssible o vershoot to VCC +2V for a period less tha n 20ns.

3. Depends on range.

Table 3. Operating Modes

No te: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Symbol Parameter Value Unit

TAAmbient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Mode E G P A9 VPP Q7-Q0

Read VIL VIL XX

CC or VSS Data Out

Output Disable VIL VIH XX

CC or VSS Hi-Z

Program VIL VIH VIL Pulse XVPP Data In

Verify VIL VIL VIH XVPP Data Out

Program Inhibit VIH XXX

PP Hi-Z

Standby VIH XXX

CC or VSS Hi-Z

Electronic Signature VIL VIL VIH VID VCC Codes

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 00100000 20h

Device Code VIH 00000101 05h

M27C1001

4/17

DEVICE OPERATION

The operat ing modes of the M 27C1001 are listed

in the Operating Modes table. A single power sup-

ply is required in the read mode. All i nput s are TTL

levels ex cept for VPP and 12V on A9 for Electronic

Signature.

Read Mode

The M 27C1001 has tw o c ont rol functions, both of

which must be logically active in order to obtain

data at t he output s. Chip Enable (E ) is t he power

control and should be used for device selection.

Output Enable (G) is the output control and should

be used to gate data to the output pins, ind epen-

dent of device selection. Assuming that the ad-

dresses are stable, the address access time

(tAVQV) is equal to the delay from E to output

(tELQV). Data is available at the output after a delay

of tGLQV from the falling ed ge of G, assuming that

E has been low and the addresses have been s ta-

ble for at least tAVQV-tGLQV.

Standby Mo de

The M27C1001 has a standby mode which reduc-

es the supply current from 30mA to 100µA. The

M27C1001 is placed in the standby mode by ap-

plying a CMOS high signal to the E input. When in

the standby mode, the outputs are in a high imped-

ance state, independen t of the G input.

Table 5. AC M easu rem en t Conditions

High Speed Standard

Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform

AI01822

High Speed

1.5V

2.4V

Standard

0.4V

2.0V

0.8V

Figure 4. AC Testing Load Circuit

AI01823B

1.3V

OUT

CL = 30pF for High Speed

CL = 100pF for Standard

CL includes JIG capacitance

3.3kΩ

1N914

DEVICE

UNDER

TEST

Table 6. Capacitance (1) (TA = 2 5 °C, f = 1 M Hz)

Not e: 1. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

CIN Input Capacitance VIN = 0V 6pF

OUT Output Capacitance VOUT = 0V 12 pF

5/17

M27C1001

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70° C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Note: 1. VCC must b e applied simul t aneou sl y with or before VPP a nd remov ed simul taneously or after V PP.

2. Max imum DC voltage on Output i s V CC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70° C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Note: 1. VCC must b e applied simul t aneou sl y with or before VPP a nd remov ed simul taneously or after V PP.

2. Sampled only, not 100% tested.

3. Speed obtained with High Speed AC measurement conditi ons.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILO O utput Leak age Curren t 0V ≤ VOUT ≤ VCC ±10 µA

ICC Su pply Curre nt E = VIL, G = VIL,

IOUT = 0mA, f = 5MHz 30 mA

ICC1 Supply Current (Standby) TTL E = VIH 1mA

CC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA

IPP Program Current VPP = VCC 10 µA

VIL Input Low Voltage –0.3 0.8 V

VIH (2) Input High Voltage 2 VCC + 1 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA 2.4 V

Output High Voltage CMOS IOH = –100µA VCC – 0.7V V

Symbol Alt Parameter Test Condition

M27C1001 Unit

-35 (3) -45 -60 -70

Min Max Min Max Min Max Min Max

tAVQV tACC Address Valid to

Output Valid E = VIL, G = VIL 35 45 60 70 ns

tELQV tCE Chip Enable Low to

Output Valid G = VIL 35 45 60 70 ns

tGLQV tOE Output Enable Low

to Output Valid E = VIL 25 25 30 35 ns

tEHQZ (2) tDF Chip Enable High to

Output Hi-Z G = VIL 025025030030ns

GHQZ (2) tDF Output Enable High

to Output Hi-Z E = VIL 025025030030ns

AXQX tOH Address Transition

to Output Transition E = VIL, G = VIL 0000ns

Two Li ne Ou tp ut C on t rol

Because EPROMs are usually used in larger

memory ar rays, this product features a 2 line con-

trol function which accom mod ates the use of m ul-

tiple memory connection. The two line control

function allows:

a. the lowest possible memory power dissipation,

b. c om ple te assurance tha t output bus contention

will not occur.

For the most efficient use of these two control

lines, E should be decoded and used as the prima-

ry device selecting function, while G should be

made a common connection to all devices in the

array and connected to the READ line from the

system control bus. This ensures that all deselect -

ed memory devices are in their low power standby

mode and that the output pins are only active

when data is required from a particular memory

device.

M27C1001

6/17

Figure 5. Read Mode AC Waveforms

AI00713B

tAXQX

tEHQZ

A0-A16

Q0-Q7

tAVQV

tGHQZ

tGLQV

tELQV

VALID

Hi-Z

VALID

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70° C, –40 to 85°C or –40 to 125°C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)

Note: 1. VCC must b e applied simul t aneou sl y with or before VPP a nd remov ed simul taneously or after V PP.

2. Sampled only, not 100% tested.

Symbol Alt Parameter Test Condition

M27C1001

Unit-80 -90 -10 -12/-15/

-20/-25

Min Max Min Max Min Max Min Max

tAVQV tACC Address Valid to

Output Valid E = VIL, G = VIL 80 90 100 120 ns

tELQV tCE Chip Enable Low to

Output Valid G = VIL 80 90 100 120 ns

tGLQV tOE Output Enable Low

to Output Valid E = VIL 40 45 50 60 ns

tEHQZ (2) tDF Chip Enable High to

Output Hi-Z G = VIL 030030030040ns

GHQZ (2) tDF Output Enable High

to Output Hi-Z E = VIL 030030030040ns

AXQX tOH Address Transition

to Output Transition E = VIL, G = VIL 0000ns

System Cons iderations

The power switching characteristics of Advanced

CMOS EPROMs require careful decoupl in g of the

devices. The supply current, ICC, has three seg-

ments that are of interest to the s ystem designer:

the standby curren t le vel, the active current level,

and transient current peaks that are produced by

the falling and rising edges of E. The magnitude of

the transient current peaks is dependent on the

capacitive and inductive loading of the device at

the output. The associated transient voltage peaks

can be suppre ss ed by co m plying with th e two line

output cont rol and by proper ly selected decoupling

capacitors. It is recommended that a 0.1µF ceram-

ic capacitor be used on every device between VCC

and VSS. Thi s sho uld be a h igh frequenc y c apaci-

tor of low inherent inductance and should be

placed as close to the device as possible. In addi-

tion, a 4.7 µF bulk electrolytic capacitor should be

used be tween V CC and V SS for ev ery eight devic-

es. The bulk c apaci tor sho uld b e locat ed near the

power supply connection point. The purpose of the

bulk capacitor is to overcome the voltage drop

caused by the inductive effects of PCB traces.

7/17

M27C1001

Table 9. Programm ing Mode DC Characteri stics (1)

(TA = 25 °C ; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)

Note: 1. VCC must b e applied simul t aneou sl y with or before VPP a nd remov ed simul taneously or after V PP.

Table 10. Progr amming Mode AC Characteristics (1)

(TA = 25 °C ; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)

Note: 1. VCC must b e applied simul t aneou sl y with or before VPP a nd remov ed simul taneously or after V PP.

2. Sampled only, not 100% tested.

Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current VIL ≤ VIN ≤ VIH ±10 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA 2.4 V

VID A9 Voltage 11.5 12.5 V

Symbol Alt Parameter Test Condition Min Max Unit

tAVPL tAS Address Valid to Program Low 2 µs

tQVPL tDS Input Valid to Program Low 2 µs

tVPHPL tVPS VPP High to Program Low 2µs

VCHPL tVCS VCC High to Pro gram Low 2µs

ELPL tCES Chip Enable Low to Program Low 2 µs

tPLPH tPW Program Pulse Width 95 105 µs

tPHQX tDH Program High to Input Transition 2 µs

tQXGL tOES Input Transition to Output Enable Low 2 µs

tGLQV tOE Output Enable Low to Output Valid 100 ns

tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns

tGHAX tAH Output Enable High to Address

Transition 0ns

Programming

When delivered (and after each erasure for UV

EPROM), all bits of the M27C1001 are in the '1'

state. Data is introduced by selectively program-

ming '0's into the desired bit locations. Although

only '0's will be programmed, both '1's and '0's can

be present in the data word. The only way to

change a '0' to a '1' is by die exposition to ultravio-

let light (UV EPROM). The M27C1001 is in the

programming mode wh en V PP input is at 12.75V,

E is at VIL and P is pulsed to VIL. The data to be

programmed is applied to 8 bits in parallel to the

data output pins. The levels required for the ad-

dress and data inputs are TTL. VCC is specified to

be 6.25V ± 0.25V.

M27C1001

8/17

PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the

whole array to be programmed, with a guaranteed

margin, in a typical time of 13 s econds. Program-

ming with PRESTO II involves in applying a se-

quence of 100µs program pulses to each byte until

a correct verify occurs (see Figure 7). During pro-

gramming and verify operation, a MARGIN MODE

circuit is automatically activated in order to guar-

antee that each cell is programmed with enough

margin. No overprogram pulse is applied since the

verify in MARGIN MODE provides necessary mar-

gin to each programmed c ell.

Program Inhibit

Programming of multiple M27C1001s in parallel

with different data is also easily accomplished. Ex-

cept for E, all like inputs including G of the paral lel

M27C1001 may be common. A TTL low level

pulse applied to a M27C1001's P input, with E low

and VPP at 12.75V, will prog ram that M27C1001.

A high level E input inhibits t he ot her M27C1001s

from being programm ed.

Program Verify

A verify (read) should be performed on the pro-

grammed bit s t o determine that they were correct-

ly programmed. The verify is accomplished with E

and G at VIL, P at VIH, VPP at 12.75V and V CC at

6.25V.

Figure 6. Program mi ng and Verify Modes AC Wavefor m s

tAVPL

VALID

AI00714

A0-A16

Q0-Q7

VPP

VCC

DATA IN DATA OUT

tQVPL

tVPHPL

tVCHPL

tPHQX

tPLPH

tGLQV

tQXGL

tELPL

tGHQZ

tGHAX

PROGRAM VERIFY

Figure 7. Programming Flowchart

AI00715C

n = 0

Last

Addr

VERIFY

P = 100µs Pulse

++n

= 25 ++ Addr

VCC = 6.25V, VPP = 12.75V

FAIL

CHECK ALL BYTES

1st: VCC = 6V

2nd: VCC = 4.2V

YES

9/17

M27C1001

Electronic Sign ature

The Electronic Signature (ES) mode allows the

reading out of a binary code from an EPROM that

will identify its manufacturer and type. This mode

is intended for use b y pro gramming equi pment to

automatically match the device to be programmed

with its corresponding programming algorithm.

The ES mod e i s functional in the 25°C ± 5°C am-

bient temperature range that is required when pro-

gramming the M27C1001. To activate the ES

mode, the programming equipment must force

11.5V to 12.5V on address line A9 of the

M27C1001, with VPP = VCC = 5V. Two identifier

bytes may then be sequenced from the device out-

puts by toggling address line A0 from VIL to VIH. All

other address lines must be held at VIL during

Electronic Signa ture mode.

Byte 0 (A0 = VIL) represents the manufacturer

code and byte 1 (A0 = VIH) the device identifier

code. For the STMicroelectronics M27C1001,

these two identifier bytes are given in Table 4 and

can be read-out on outputs Q7 to Q0.

ERASURE OPERATION (ap plies to UV EPROM)

The erasure characteristics of the M27C1001 is

such that erasure begins when the cells are ex-

posed to light with wavelengths shorter than ap-

proximately 4000 Å. It should be noted that

sunlight and some type of fluoresce nt lamps have

wavelengths in the 3000-400 0 Å range . Research

shows that constant exposure to room level fluo-

rescent lighting could erase a typical M27C1001 in

about 3 years, while it would take approximately 1

week to cause erasure when exposed to direct

sunlight. If the M27C1001 is to be exposed to

these types of light ing conditions for extended pe-

riods of time, it is suggested that opaque labels be

put over the M27C1001 window to prevent unin-

tentional eras ure. The recommended erasur e pro-

cedure for the M27C1001 is exposure to short

wave ultraviolet light which has a wavelength of

2537 Å. The integrated dose (i.e. UV intensity x

exposure time) for erasure should be a m inimum

of 15 W-sec/cm2. T he erasure t ime with th is dos-

age is approximately 15 to 20 minutes using an ul-

traviolet lamp with 12000 µW/cm2 power rating.

The M27C1001 should be placed within 2.5 cm (1

inch) of the lamp t ubes during the e rasure. Some

lamps have a f ilter on their tubes which should be

removed before erasure.

M27C1001

10/17

Table 11. Ordering Information Scheme

No te : 1. High S peed , s ee AC Charact eri stics section for fur ther informat i on.

For a list of availabl e options (S peed, P ack age, et c...) or for further information on any aspect of this de-

vice, pleas e contact the STMicroelectronics Sales Office near est to you.

Example: M27C1001 -35 X C 1 TR

Device Type

M27

Supply Voltage

C = 5V

Device Function

1001 = 1 Mbit (128Kb x8)

Speed

-35 (1) = 35 ns

-45 = 45 ns

-60 = 60 ns

-70 = 70 ns

-80 = 80 ns

-90 = 90 ns

-10 = 100 ns

-12 = 120 ns

-15 = 150 ns

-20 = 200 ns

-25 = 250 ns

VCC Tolerance

blank = ± 10%

X = ± 5%

Package

F = FDIP32W

B = PDIP32

L = LCCC32W

C = PLCC32

N = TSOP32: 8 x 20 mm

Tem pera ture Rang e

1 = 0 to 70 °C

3 = –40 to 125 °C

6 = –40 to 85 °C

Options

X = Additional Burn-in

TR = Tape & Reel Packing

11/17

M27C1001

Table 12. Revision History

Date Revision Details

September 1998 First Issue

24-Jan-2000 35ns speed class addes (Table 8A, 11)

20-Sep-2000 AN620 Reference removed

04-Jun-2002 PLCC32 Package mechanical data and drawing clarified (Table 16 and Figure 11)

TSOP32 Package mechanical data clarified (Table 17)

M27C1001

12/17

Table 13. FDI P32 W - 32 pin Ceramic Frit-seal DIP with window, Package Me chanic al Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 5.72 0.225

A1 0.51 1.40 0.020 0.055

A2 3.91 4.57 0.154 0.180

A3 3.89 4.50 0.153 0.177

B 0.41 0.56 0.016 0.022

B1 1.45 – – 0.057 – –

C 0.23 0.30 0.009 0.012

D 41.73 42.04 1.643 1.655

D2 38.10 – – 1.500 – –

E 15.24 – – 0.600 – –

E1 13.06 13.36 0.514 0.526

e 2.54 – – 0.100 – –

eA 14.99 – – 0.590 – –

eB 16.18 18.03 0.637 0.710

L 3.18 0.125

S 1.52 2.49 0.060 0.098

∅7.11 – – 0.280 – –

α4° 11° 4° 11°

N32 32

Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP with window, Pac kage Outline

Drawing is not to scale.

FDIPW-a

B1 B e

E1 E

∅

13/17

M27C1001

Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Packag e Mechan ica l Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A – 5.08 – 0.200

A1 0.38 – 0.015 –

A2 3.56 4.06 0.140 0.160

B 0.38 0.51 0.015 0.020

B1 1.52 – – 0.060 – –

C 0.20 0.30 0.008 0.012

D 41.78 42.04 1.645 1.655

D2 38.10 – – 1.500 – –

E 15.24 – – 0.600 – –

E1 13.59 13.84 0.535 0.545

e1 2.54 – – 0.100 – –

eA 15.24 – – 0.600 – –

eB 15.24 17.78 0.600 0.700

L 3.18 3.43 0.125 0.135

S 1.78 2.03 0.070 0.080

α0° 10° 0° 10°

N32 32

Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Ou tline

Drawing is not to scale.

PDIP

B1 B e1

E1 E

M27C1001

14/17

Table 15. LCCC32W - 32 l ead Leadl ess Ceramic Chip Carrier, Package Mechanical Data

Symbol millimeters inches

Typ Min Max Typ Min Max

A 2.28 0.090

B 0.51 0.71 0.020 0.028

D 11.23 11.63 0.442 0.458

E 13.72 14.22 0.540 0.560

e 1.27 – – 0.050 – –

e1 0.39 – 0.015 –

e2 7.62 – – 0.300 – –

e3 10.16 – – 0.400 – –

h 1.02 – – 0.040 – –

j 0.51 – – 0.020 – –

L 1.14 1.40 0.045 0.055

L1 1.96 2.36 0.077 0.093

K 10.50 10.80 0.413 0.425

K1 8.03 8.23 0.316 0.324

N32 32

Figure 10. LCC C32W - 32 lead Leadless Ceram ic Chip Carr ier, Pa ckage Outline

Drawing is not to scale.

LCCCW-a

NL1

h x 45o

j x 45o

15/17

M27C1001

Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mec han ical Data

millimeters inches

Symbol Typ Min Max Typ Min Max

A 3.18 3.56 0.125 0.140

A1 1.53 2.41 0.060 0.095

A2 0.38 – 0.015 –

B 0.33 0.53 0.013 0.021

B1 0.66 0.81 0.026 0.032

CP 0.10 0.004

D 12.32 12.57 0.485 0.495

D1 11.35 11.51 0.447 0.453

D2 4.78 5.66 0.188 0.223

D3 7.62 – – 0.300 – –

E 14.86 15.11 0.585 0.595

E1 13.89 14.05 0.547 0.553

E2 6.05 6.93 0.238 0.273

E3 10.16 – – 0.400 – –

e 1.27 – – 0.050 – –

F 0.00 0.13 0.000 0.005

N32 32

R 0.89 – – 0.035 – –

Figure 11. PLCC32 - 32 lead Plastic Lead ed Chip Carrier, Pac kage Outline

Drawing is not to scale.

PLCC-A

E3 E1 E

1 N

0.51 (.020)

1.14 (.045)

D2 D2

M27C1001

16/17

Figure 12. TSO P32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline

Drawing is not to scale.

TSOP-a

1 N

N/2

DIE

LA1 α

Table 17. TSOP32 - 32 lead Plastic Thin Small Ou tline, 8 x 20 mm, Package Me chan ical Data

millimeters inches

Symbol Typ Min Max Typ Min Max

A 1.200 0.0472

A1 0.050 0.150 0.0020 0.0059

A2 0.950 1.050 0.0374 0.0413

B 0.170 0.250 0.0067 0.0098

C 0.100 0.210 0.0039 0.0083

CP 0.100 0.0039

D 19.800 20.200 0.7795 0.7953

D1 18.300 18.500 0.7205 0.7283

e 0.500 – – 0.0197 – –

E 7.900 8.100 0.3110 0.3189

L 0.500 0.700 0.0197 0.0276

α0° 5° 0° 5°

N32 32

17/17

M27C1001

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STMic roelect ron i cs GROUP OF COMPANIES

Aus tralia - Brazil - Cana da - Chi na - Finl and - France - German y - Hong Kong - India - Is rael - Ital y - Japan - Malaysia - M al ta -

Morocc o - Singa pore - Spain - Sweden - Switzerland - Uni t ed King dom - Unit ed States