Features
•High Performance, Low Power Atmel® AVR® 8-Bit Microcontroller
•Advanced RISC Architecture
– 135 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16MHz
– On-Chip 2-cycle Multiplier
•High Endurance Non-volatile Memory Segments
– 64K/128K/256KBytes of In-System Self-Programmable Flash
– 4Kbytes EEPROM
– 8Kbytes Internal SRAM
– Write/Erase Cycles:10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85C/ 100 years at 25C
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Endurance: Up to 64Kbytes Optional External Memory Space
•Atmel® QTouch® library support
– Capacitive touch buttons, sliders and wheels
– QTouch and QMatrix® acquisition
– Up to 64 sense channels
•JTAG (IEEE std. 1149.1 compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
•Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– Four 16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode
– Real Time Counter with Separate Oscillator
– Four 8-bit PWM Channels
– Six/Twelve PWM Channels with Programmable Resolution from 2 to 16 Bits
(ATmega1281/2561, ATmega640/1280/2560)
– Output Compare Modulator
– 8/16-channel, 10-bit ADC (ATmega1281/2561, ATmega640/1280/2560)
– Two/Four Programmable Serial USART (ATmega1281/2561, ATmega640/1280/2560)
– Master/Slave SPI Serial Interface
– Byte Oriented 2-wire Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
•Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby,
and Extended Standby
•I/O and Packages
– 54/86 Programmable I/O Lines (ATmega1281/2561, ATmega640/1280/2560)
– 64-pad QFN/MLF, 64-lead TQFP (ATmega1281/2561)
– 100-lead TQFP, 100-ball CBGA (ATmega640/1280/2560)
– RoHS/Fully Green
•Temperature Range:
–-40C to 85C Industrial
•Ultra-Low Power Consumption
– Active Mode: 1MHz, 1.8V: 500µA
– Power-down Mode: 0.1µA at 1.8V
•Speed Grade:
– ATmega640V/ATmega1280V/ATmega1281V:
• 0 - 4MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
– ATmega2560V/ATmega2561V:
• 0 - 2MHz @ 1.8V - 5.5V, 0 - 8MHz @ 2.7V - 5.5V
– ATmega640/ATmega1280/ATmega1281:
• 0 - 8MHz @ 2.7V - 5.5V, 0 - 16MHz @ 4.5V - 5.5V
– ATmega2560/ATmega2561:
• 0 - 16MHz @ 4.5V - 5.5V
8-bit Atmel
Microcontroller
with
64K/128K/256K
Bytes In-System
Programmable
Flash
ATmega640/V
ATmega1280/V
ATmega1281/V
ATmega2560/V
ATmega2561/V
Summary
2549OS–AVR–05/12
2
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
1. Pin Configurations
Figure 1-1. TQFP-pinout ATmega640/1280/2560
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
100 99 9897 96 95 94 93 92 91 90 8988 8786858483828180 79 7877 76
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 2829 3127 3630 32 35 3733 34 3839 40 41 42 43 44 45 46 47 4849 50
PK0 (ADC8/PCINT16)
PK1 (ADC9/PCINT17)
PK2 (ADC10/PCINT18)
PK3 (ADC11/PCINT19)
PK4 (ADC12/PCINT20)
PK5 (ADC13/PCINT21)
PK6 (ADC14/PCINT22)
PK7 (ADC15/PCINT23)
(OC2B) PH6
(TOSC2) PG3
(TOSC1) PG4
RESET
(T4) PH7
(ICP4) PL0
VCC
GND
XTAL2
XTAL1
PL6
PL7
GND
VCC
(OC0B) PG5
VCC
GND
(RXD2) PH0
(TXD2) PH1
(XCK2) PH2
(OC4A) PH3
(OC4B) PH4
(OC4C) PH5
(RXD0/PCINT8) PE0
(TXD0) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(CLKO/ICP3/INT7) PE7
(SS/PCINT0) PB0
(SCK/PCINT1) PB1
(MOSI/PCINT2) PB2
(MISO/PCINT3) PB3
(OC2A/PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
(OC0A/OC1C/PCINT7) PB7
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
(T1) PD6
(T0) PD7
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(ICP5) PL1
(T5) PL2
(OC5A) PL3
(OC5B) PL4
PJ6 (PCINT15)
PJ5 (PCINT14)
PJ4 (PCINT13)
PJ3 (PCINT12)
PJ2 (XCK3/PCINT11)
PJ1 (TXD3/PCINT10)
PJ0 (RXD3/PCINT9)
PJ7
(OC5C) PL5
INDEX CORNER
3
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
Figure 1-2. CBGA-pinout ATmega640/1280/2560
Note: The functions for each pin is the same as for the 100 pin packages shown in Figure 1-1 on page 2.
A
B
C
D
E
F
G
H
J
K
12345678910
A
B
C
D
E
F
G
H
J
K
10987654321
Top view Bottom view
Table 1-1. CBGA-pinout ATmega640/1280/2560
1 2 3 4 5 678 910
AGND AREF PF0 PF2 PF5 PK0 PK3 PK6 GNDVCC
BAVCC PG5 PF1 PF3 PF6 PK1 PK4 PK7 PA0 PA2
CPE2 PE0 PE1 PF4 PF7 PK2 PK5 PJ7 PA1 PA3
DPE3 PE4 PE5 PE6 PH2 PA4 PA5 PA6 PA7 PG2
EPE7 PH0 PH1 PH3 PH5 PJ6 PJ5 PJ4 PJ3 PJ2
FVCC PH4 PH6 PB0 PL4 PD1 PJ1 PJ0 PC7 GND
GGND PB1 PB2 PB5 PL2 PD0 PD5 PC5 PC6 VCC
HPB3 PB4 RESET PL1 PL3 PL7 PD4 PC4 PC3 PC2
JPH7 PG3 PB6 PL0 XTAL2 PL6 PD3 PC1 PC0 PG1
KPB7 PG4 VCC GND XTAL1 PL5 PD2 PD6 PD7 PG0
4
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
Figure 1-3. Pinout ATmega1281/2561
Note: The large center pad underneath the QFN/MLF package is made of metal and internally con-
nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
(RXD0/PCINT8/PDI) PE0
(TXD0/PDO) PE1
(XCK0/AIN0) PE2
(OC3A/AIN1) PE3
(OC3B/INT4) PE4
(OC3C/INT5) PE5
(T3/INT6) PE6
(ICP3/CLKO/INT7) PE7
(SS/PCINT0) PB0
(OC0B) PG5
(SCK/ PCINT1) PB1
(MOSI/ PCINT2) PB2
(MISO/ PCINT3) PB3
(OC2A/ PCINT4) PB4
(OC1A/PCINT5) PB5
(OC1B/PCINT6) PB6
(OC0A/OC1C/PCINT7) PB7
(TOSC2) PG3
(TOSC1) PG4
RESET
VCC
GND
XTAL2
XTAL1
(SCL/INT0) PD0
(SDA/INT1) PD1
(RXD1/INT2) PD2
(TXD1/INT3) PD3
(ICP1) PD4
(XCK1) PD5
PA3 (AD3)
PA4 (AD4)
PA5 (AD5)
PA6 (AD6)
PA7 (AD7)
PG2 (ALE)
PC7 (A15)
PC6 (A14)
PC5 (A13)
PC4 (A12)
PC3 (A11)
PC2 (A10)
PC1 (A9)
PC0 (A8)
PG1 (RD)
PG0 (WR)
AVCC
GND
AREF
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
PF5 (ADC5/TMS)
PF6 (ADC6/TDO)
PF7 (ADC7/TDI)
GND
VCC
PA0 (AD0)
PA1 (AD1)
PA2 (AD2)
(T1) PD6
(T0) PD7
INDEX CORNER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
5
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
2. Overview
The ATmega640/1280/1281/2560/2561 is a low-power CMOS 8-bit microcontroller based on the
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
ATmega640/1280/1281/2560/2561 achieves throughputs approaching 1 MIPS per MHz allowing
the system designer to optimize power consumption versus processing speed.
2.1 Block Diagram
Figure 2-1. Block Diagram
CPU
GND
VCC
RESET
Po w e r
Supervision
POR / BOD &
RESET
Wat ch dog
Oscillator
Wat ch dog
Ti m er
Oscillator
Ci rcu i t s /
Cl o c k
Gen e r at i o n
XTAL1
XTAL2
PC7..0 PORT C (8)
PA7..0 PORT A (8)
PORT D (8)
PD7..0
PORT B (8)
PB7..0
PORT E ( 8)
PE7..0
PORT F (8)
PF7..0
PORT J (8)
PJ7..0
PG5..0 PORT G (6)
PORT H (8)
PH7..0
PORT K (8)
PK7..0
PORT L (8 )
PL7..0
XRAM
TWISPI
EEPROM
JTAG
8 bit T/ C 0 8 bit T/ C 2
16 bit T/ C 1
16 bit T/ C 3
SRAMFLASH
16 bit T/ C 4
16 bit T/ C 5
USART 2
USART 1
USART 0
Internal
Bandgap reference
Analog
Co m p a rat o r
A/D
Co n v er t er
USART 3
NOTE:
Shaded part s only available
in the 100-pin version.
Complete functionality for
t he ADC, T/ C4, an d T/ C5 o n l y
available in the 100-pin version.
6
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
The Atmel® AVR® core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The ATmega640/1280/1281/2560/2561 provides the following features: 64K/128K/256K bytes of
In-System Programmable Flash with Read-While-Write capabilities, 4Kbytes EEPROM, 8
Kbytes SRAM, 54/86 general purpose I/O lines, 32 general purpose working registers, Real
Time Counter (RTC), six flexible Timer/Counters with compare modes and PWM, 4 USARTs, a
byte oriented 2-wire Serial Interface, a 16-channel, 10-bit ADC with optional differential input
stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI
serial port, IEEE® std. 1149.1 compliant JTAG test interface, also used for accessing the On-
chip Debug system and programming and six software selectable power saving modes. The Idle
mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system
to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-
save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all
I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC
conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the
device is sleeping. This allows very fast start-up combined with low power consumption. In
Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels-
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition
offersrobust sensing and includes fully debounced reporting of touch keys and includes Adjacent
KeySuppression® (AKS™) technology for unambiguous detection of key events. The easy-to-use
QTouch Suite toolchain allows you to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-
chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel ATmega640/1280/1281/2560/2561 is a powerful microcontroller that provides a highly
flexible and cost effective solution to many embedded control applications.
The ATmega640/1280/1281/2560/2561 AVR is supported with a full suite of program and sys-
tem development tools including: C compilers, macro assemblers, program
debugger/simulators, in-circuit emulators, and evaluation kits.
7
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
2.2 Comparison Between ATmega1281/2561 and ATmega640/1280/2560
Each device in the ATmega640/1280/1281/2560/2561 family differs only in memory size and
number of pins. Table 2-1 summarizes the different configurations for the six devices.
2.3 Pin Descriptions
2.3.1 VCC
Digital supply voltage.
2.3.2 GND
Ground.
2.3.3 Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 78.
2.3.4 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 79.
2.3.5 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
Table 2-1. Configuration Summary
Device Flash EEPROM RAM
General
Purpose I/O pins
16 bits resolution
PWM channels
Serial
USARTs
ADC
Channels
ATmega640 64KB 4KB 8KB 86 12 4 16
ATmega1280 128KB 4KB 8KB 86 12 4 16
ATmega1281 128KB 4KB 8KB 54 6 2 8
ATmega2560 256KB 4KB 8KB 86 12 4 16
ATmega2561 256KB 4KB 8KB 54 6 2 8
8
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega640/1280/1281/2560/2561 as
listed on page 82.
2.3.6 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 83.
2.3.7 Port E (PE7..PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 86.
2.3.8 Port F (PF7..PF0)
Port F serves as analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym-
metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface.
2.3.9 Port G (PG5..PG0)
Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output
buffers have symmetrical drive characteristics with both high sink and source capability. As
inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are
activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock
is not running.
Port G also serves the functions of various special features of the
ATmega640/1280/1281/2560/2561 as listed on page 90.
2.3.10 Port H (PH7..PH0)
Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
9
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port H also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 92.
2.3.11 Port J (PJ7..PJ0)
Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capa-
bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port J also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 94.
2.3.12 Port K (PK7..PK0)
Port K serves as analog inputs to the A/D Converter.
Port K is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port K output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port K pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port K pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port K also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 96.
2.3.13 Port L (PL7..PL0)
Port L is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port L output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port L pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port L pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port L also serves the functions of various special features of the ATmega640/1280/2560 as
listed on page 98.
2.3.14 RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in “System and Reset
Characteristics” on page 372. Shorter pulses are not guaranteed to generate a reset.
2.3.15 XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.3.16 XTAL2
Output from the inverting Oscillator amplifier.
10
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
2.3.17 AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con-
nected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC
through a low-pass filter.
2.3.18 AREF
This is the analog reference pin for the A/D Converter.
11
2549OS–AVR–05/12
ATmega640/1280/1281/2560/2561
3. Resources
A comprehensive set of development tools and application notes, and datasheets are available
for download on http://www.atmel.com/avr.
4. About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
These code examples assume that the part specific header file is included before compilation.
For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI"
instructions must be replaced with instructions that allow access to extended I/O. Typically
"LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".
5. Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 ppm over 20 years at 85°C or 100 years at 25°C.
6. Capacitive touch sensing
The Atmel®QTouch® Library provides a simple to use solution to realize touch sensitive inter-
faces on most Atmel AVR® microcontrollers. The QTouch Library includes support for the
QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan-
nels and sensors, and then calling the touch sensing API’s to retrieve the channel information
and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.
12
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
7. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0x1FF) Reserved - - - - - - - -
... Reserved - - - - - - - -
(0x13F) Reserved
(0x13E) Reserved
(0x13D) Reserved
(0x13C) Reserved
(0x13B) Reserved
(0x13A) Reserved
(0x139) Reserved
(0x138) Reserved
(0x137) Reserved
(0x136) UDR3 USART3 I/O Data Register 222
(0x135) UBRR3H - - - - USART3 Baud Rate Register High Byte 227
(0x134) UBRR3L USART3 Baud Rate Register Low Byte 227
(0x133) Reserved - - - - - - - -
(0x132) UCSR3C UMSEL31 UMSEL30 UPM31 UPM30 USBS3 UCSZ31 UCSZ30 UCPOL3 239
(0x131) UCSR3B RXCIE3 TXCIE3 UDRIE3 RXEN3TXEN3 UCSZ32 RXB83 TXB83 238
(0x130) UCSR3A RXC3 TXC3 UDRE3 FE3 DOR3 UPE3 U2X3 MPCM3 238
(0x12F) Reserved - - - - - - - -
(0x12E) Reserved - - - - - - - -
(0x12D) OCR5CH Timer/Counter5 - Output Compare Register C High Byte 165
(0x12C) OCR5CL Timer/Counter5 - Output Compare Register C Low Byte 165
(0x12B) OCR5BH Timer/Counter5 - Output Compare Register B High Byte 165
(0x12A) OCR5BL Timer/Counter5 - Output Compare Register B Low Byte 165
(0x129) OCR5AH Timer/Counter5 - Output Compare Register A High Byte 164
(0x128) OCR5AL Timer/Counter5 - Output Compare Register A Low Byte 164
(0x127) ICR5H Timer/Counter5 - Input Capture Register High Byte 165
(0x126) ICR5L Timer/Counter5 - Input Capture Register Low Byte 165
(0x125) TCNT5H Timer/Counter5 - Counter Register High Byte 163
(0x124) TCNT5L Timer/Counter5 - Counter Register Low Byte 163
(0x123) Reserved - - - - - - - -
(0x122) TCCR5C FOC5A FOC5B FOC5C - - - - - 162
(0x121) TCCR5B ICNC5 ICES5 -WGM53 WGM52 CS52 CS51 CS50 160
(0x120) TCCR5A COM5A1 COM5A0 COM5B1 COM5B0 COM5C1 COM5C0 WGM51 WGM50 158
(0x11F) Reserved - - - - - - - -
(0x11E) Reserved - - - - - - - -
(0x11D) Reserved - - - - - - - -
(0x11C) Reserved - - - - - - - -
(0x11B) Reserved - - - - - - - -
(0x11A) Reserved - - - - - - - -
(0x119) Reserved - - - - - - - -
(0x118) Reserved - - - - - - - -
(0x117) Reserved - - - - - - - -
(0x116) Reserved - - - - - - - -
(0x115) Reserved - - - - - - - -
(0x114) Reserved - - - - - - - -
(0x113) Reserved - - - - - - - -
(0x112) Reserved - - - - - - - -
(0x111) Reserved - - - - - - - -
(0x110) Reserved - - - - - - - -
(0x10F) Reserved - - - - - - - -
(0x10E) Reserved - - - - - - - -
(0x10D) Reserved - - - - - - - -
(0x10C) Reserved - - - - - - - -
(0x10B) PORTL PORTL7 PORTL6 PORTL5 PORTL4 PORTL3 PORTL2 PORTL1 PORTL0 104
(0x10A) DDRL DDL7 DDL6 DDL5 DDL4 DDL3 DDL2 DDL1 DDL0 104
(0x109) PINLPINL7 PINL6 PINL5 PINL4 PINL3 PINL2 PINL1 PINL0 104
(0x108) PORTK PORTK7 PORTK6 PORTK5 PORTK4 PORTK3 PORTK2 PORTK1 PORTK0 103
(0x107) DDRK DDK7 DDK6 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 103
(0x106) PINKPINK7 PINK6 PINK5 PINK4 PINK3 PINK2 PINK1 PINK0 103
(0x105) PORTJ PORTJ7 PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 103
(0x104) DDRJ DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 103
(0x103) PINJPINJ7 PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 103
(0x102) PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 102
(0x101) DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 103
13
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
(0x100) PINHPINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 103
(0xFF) Reserved - - - - - - - -
(0xFE) Reserved - - - - - - - -
(0xFD) Reserved - - - - - - - -
(0xFC) Reserved - - - - - - - -
(0xFB) Reserved - - - - - - - -
(0xFA) Reserved - - - - - - - -
(0xF9) Reserved - - - - - - - -
(0xF8) Reserved - - - - - - - -
(0xF7) Reserved - - - - - - - -
(0xF6) Reserved - - - - - - - -
(0xF5) Reserved - - - - - - - -
(0xF4) Reserved - - - - - - - -
(0xF3) Reserved - - - - - - - -
(0xF2) Reserved - - - - - - - -
(0xF1) Reserved - - - - - - - -
(0xF0) Reserved - - - - - - - -
(0xEF) Reserved - - - - - - - -
(0xEE) Reserved - - - - - - - -
(0xED) Reserved - - - - - - - -
(0xEC) Reserved - - - - - - - -
(0xEB) Reserved - - - - - - -
(0xEA) Reserved - - - - - - - -
(0xE9) Reserved - - - - - - - -
(0xE8) Reserved - - - - - - - -
(0xE7) Reserved - - - - - - -
(0xE6) Reserved - - - - - - - -
(0xE5) Reserved - - - - - - - -
(0xE4) Reserved - - - - - - - -
(0xE3) Reserved - - - - - - -
(0xE2) Reserved - - - - - - - -
(0xE1) Reserved - - - - - - -
(0xE0) Reserved - - - - - - -
(0xDF) Reserved - - - - - - - -
(0xDE) Reserved - - - - - - - -
(0xDD) Reserved - - - - - - -
(0xDC) Reserved - - - - - - - -
(0xDB) Reserved - - - - - - - -
(0xDA) Reserved - - - - - - - -
(0xD9) Reserved - - - - - - -
(0xD8) Reserved - - - - - - - -
(0xD7) Reserved - - - - - - - -
(0xD6) UDR2 USART2 I/O Data Register 222
(0xD5) UBRR2H - - - - USART2 Baud Rate Register High Byte 227
(0xD4) UBRR2L USART2 Baud Rate Register Low Byte 227
(0xD3) Reserved - - - - - - - -
(0xD2) UCSR2C UMSEL21 UMSEL20 UPM21 UPM20 USBS2 UCSZ21 UCSZ20 UCPOL2 239
(0xD1) UCSR2B RXCIE2 TXCIE2 UDRIE2 RXEN2TXEN2 UCSZ22 RXB82 TXB82 238
(0xD0) UCSR2A RXC2 TXC2 UDRE2 FE2 DOR2 UPE2 U2X2 MPCM2 238
(0xCF) Reserved - - - - - - - -
(0xCE) UDR1 USART1 I/O Data Register 222
(0xCD) UBRR1H - - - - USART1 Baud Rate Register High Byte 227
(0xCC) UBRR1L USART1 Baud Rate Register Low Byte 227
(0xCB) Reserved - - - - - - - -
(0xCA) UCSR1C UMSEL11 UMSEL10 UPM11 UPM10 USBS1 UCSZ11 UCSZ10 UCPOL1 239
(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1TXEN1 UCSZ12 RXB81 TXB81 238
(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 238
(0xC7) Reserved - - - - - - - -
(0xC6) UDR0 USART0 I/O Data Register 222
(0xC5) UBRR0H - - - - USART0 Baud Rate Register High Byte 227
(0xC4) UBRR0L USART0 Baud Rate Register Low Byte 227
(0xC3) Reserved - - - - - - - -
(0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 239
(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0TXEN0 UCSZ02 RXB80 TXB80 238
(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 238
(0xBF) Reserved - - - - - - - -
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
14
2549O–AVR–05/12
ATmega640/1280/1281/2560/2561
(0xBE) Reserved - - - - - - - -
(0xBD) TWAMR TWAM6 TWAM5 TWAM4 TWAM3 TWAM2 TWAM1 TWAM0 -269
(0xBC) TWCR TWINTTWEA TWSTA TWSTO TWWCTWEN-TWIE 266
(0xBB) TWDR 2-wire Serial Interface Data Register 268
(0xBA) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 269
(0xB9) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 -TWPS1 TWPS0 268
(0xB8) TWBR 2-wire Serial Interface Bit Rate Register 266
(0xB7) Reserved - - - - - - - -
(0xB6) ASSR -EXCLKAS2TCN2UB OCR2AUB OCR2BUB TCR2AUB TCR2BUB 184
(0xB5) Reserved - - - - - - - -
(0xB4) OCR2B Timer/Counter2 Output Compare Register B 191
(0xB3) OCR2A Timer/Counter2 Output Compare Register A 191
(0xB2) TCNT2 Timer/Counter2 (8 Bit) 191
(0xB1) TCCR2B FOC2A FOC2B - - WGM22 CS22 CS21 CS20 190
(0xB0) TCCR2A COM2A1 COM2A0 COM2B1 COM2B0 - - WGM21 WGM20 191
(0xAF) Reserved - - - - - - - -
(0xAE) Reserved - - - - - - - -
(0xAD) OCR4CH Timer/Counter4 - Output Compare Register C High Byte 164
(0xAC) OCR4CL Timer/Counter4 - Output Compare Register C Low Byte 164
(0xAB) OCR4BH Timer/Counter4 - Output Compare Register B High Byte 164
(0xAA) OCR4BL Timer/Counter4 - Output Compare Register B Low Byte 164
(0xA9) OCR4AH Timer/Counter4 - Output Compare Register A High Byte 164
(0xA8) OCR4AL Timer/Counter4 - Output Compare Register A Low Byte 164
(0xA7) ICR4H Timer/Counter4 - Input Capture Register High Byte 165
(0xA6) ICR4L Timer/Counter4 - Input Capture Register Low Byte 165
(0xA5) TCNT4H Timer/Counter4 - Counter Register High Byte 163
(0xA4) TCNT4L Timer/Counter4 - Counter Register Low Byte 163
(0xA3) Reserved - - - - - - - -
(0xA2) TCCR4C FOC4A FOC4B FOC4C - - - - - 162
(0xA1) TCCR4B ICNC4 ICES4 -WGM43 WGM42 CS42 CS41 CS40 160
(0xA0) TCCR4A COM4A1 COM4A0 COM4B1 COM4B0 COM4C1 COM4C0 WGM41 WGM40 158
(0x9F) Reserved - - - - - - - -
(0x9E) Reserved - - - - - - - -
(0x9D) OCR3CH Timer/Counter3 - Output Compare Register C High Byte 164
(0x9C) OCR3CL Timer/Counter3 - Output Compare Register C Low Byte 164
(0x9B) OCR3BH Timer/Counter3 - Output Compare Register B High Byte 164
(0x9A) OCR3BL Timer/Counter3 - Output Compare Register B Low Byte 164
(0x99) OCR3AH Timer/Counter3 - Output Compare Register A High Byte 163
(0x98) OCR3AL Timer/Counter3 - Output Compare Register A Low Byte 163
(0x97) ICR3H Timer/Counter3 - Input Capture Register High Byte 165
(0x96) ICR3L Timer/Counter3 - Input Capture Register Low Byte 165
(0x95) TCNT3H Timer/Counter3 - Counter Register High Byte 162
(0x94) TCNT3L Timer/Counter3 - Counter Register Low Byte 162
(0x93) Reserved - - - - - - - -
(0x92) TCCR3C FOC3A FOC3B FOC3C - - - - - 162
(0x91) TCCR3B ICNC3 ICES3 -WGM33 WGM32 CS32 CS31 CS30 160
(0x90) TCCR3A COM3A1 COM3A0 COM3B1 COM3B0 COM3C1 COM3C0 WGM31 WGM30 158
(0x8F) Reserved - - - - - - - -
(0x8E) Reserved - - - - - - - -
(0x8D) OCR1CH Timer/Counter1 - Output Compare Register C High Byte 163
(0x8C) OCR1CL Timer/Counter1 - Output Compare Register C Low Byte 163
(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 163
(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 163
(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 163
(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 163
(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 165
(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 165
(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 162
(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 162
(0x83) Reserved - - - - - - - -
(0x82) TCCR1C FOC1A FOC1B FOC1C - - - - - 161
(0x81) TCCR1B ICNC1 ICES1 -WGM13 WGM12 CS12 CS11 CS10 160
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 COM1C1 COM1C0 WGM11 WGM10 158
(0x7F) DIDR1 - - - - - -AIN1D AIN0D 274
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 295
(0x7D) DIDR2 ADC15D ADC14D ADC13D ADC12D ADC11D ADC10D ADC9D ADC8D 295
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page