INTEGRATED CIRCUITS PZ5128 128 macrocell CPLD Product specification Supersedes data of 1997 Apr 28 IC27 Data Handbook 1997 Aug 12 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 FEATURES Table 1. PZ5128 Features * Industry's first TotalCMOS PLD - both CMOS design and PZ5128 process technologies * Fast Zero Power (FZP) design technique provides ultra-low power and very high speed * IEEE 1149.1-compliant, JTAG Testing Capability Usable gates 4000 Maximum inputs 100 Maximum I/Os 96 - 4 pin JTAG interface (TCK, TMS, TDI, TDO) Number of macrocells 128 - IEEE 1149.1 TAP Controller Propagation delay (ns) - JTAG commands include: Bypass, Sample/Preload, Extest, Usercode, Idcode, HighZ Packages * 5 Volt, In-System Programmable (ISP) using the JTAG interface 7.5 84-pin PLCC, 100-pin PQFP, 100-pin TQFP 128-pin LQFP, 160-pin PQFP - On-chip supervoltage generation DESCRIPTION - ISP commands include: Enable, Erase, Program, Verify The PZ5128 CPLD (Complex Programmable Logic Device) is the third in a family of Fast Zero Power (FZP) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 128 macrocell CPLD. With the FZP design technique, the PZ5128 offers true pin-to-pin speeds of 7.5ns, while simultaneously delivering power that is less than 100A at standby without the need for `turbo bits' or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD - 70% lower at 50MHz. These devices are the first TotalCMOS PLDs, as they use both a CMOS process technology and the patented full CMOS FZP design technique. For 3V applications, Philips also offers the high speed PZ3128 CPLD that offers these features in a full 3V implementation. - Supported by multiple ISP programming platforms * High speed pin-to-pin delays of 7.5ns * Ultra-low static power of less than 100A * Dynamic power that is 70% lower at 50MHz than competing devices * 100% routable with 100% utilization while all pins and all macrocells are fixed * Deterministic timing model that is extremely simple to use * 4 clocks with programmable polarity at every macrocell * Support for complex asynchronous clocking * Innovative XPLA architecture combines high speed with extreme flexibility * 1000 erase/program cycles guaranteed * 20 years data retention guaranteed * Logic expandable to 37 product terms * PCI compliant * Advanced 0.5 E2CMOS process * Security bit prevents unauthorized access * Design entry and verification using industry standard and Philips The Philips FZP CPLDs introduce the new patent-pending XPLA (eXtended Programmable Logic Array) architecture. The XPLA architecture combines the best features of both PLA and PAL type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA structure in each logic block provides a fast 10ns PAL path with 5 dedicated product terms per output. This PAL path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2ns, regardless of the number of PLA product terms used, which results in worst case tPD's of only 9.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. CAE tools * Reprogrammable using industry standard device programmers * Innovative Control Term structure provides either sum terms or product terms in each logic block for: - Programmable 3-State buffer - Asynchronous macrocell register preset/reset * Programmable global 3-State pin facilitates `bed of nails' testing without using logic resources * Available in PLCC, TQFP, and PQFP packages * Available in both Commercial and Industrial grades The PZ5128 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either MINC or Philips Semiconductors-developed tools. The PZ5128 CPLD is electrically reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. The PZ5128 also includes an industry-standard, IEEE 1149.1, JTAG interface through which in-system programming (ISP) and reprogramming of the device is supported. PAL is a registered trademark of Advanced Micro Devices, Inc. 1997 Aug 12 2 853-2023 18271 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 ORDERING INFORMATION ORDER CODE DESCRIPTION DESCRIPTION DRAWING NUMBER PZ5128-S7A84 84-pin PLCC, 7.5ns tPD Commercial temp range, 5 volt power supply, 5% SOT189-3 PZ5128-S10A84 84-pin PLCC, 10ns tPD Commercial temp range, 5 volt power supply, 5% SOT189-3 PZ5128-S12A84 84-pin PLCC, 12ns tPD Commercial temp range, 5 volt power supply, 5% SOT189-3 PZ528IS10A84 84-pin PLCC, 10ns tPD Industrial temp range, 5 volt power supply, 10% SOT189-3 PZ5128IS15A84 84-pin PLCC, 15ns tPD Industrial temp range, 5 volt power supply, 10% SOT189-3 PZ5128-S7BB1 100-pin PQFP, 7.5ns tPD Commercial temp range, 5 volt power supply, 5% SOT382-1 PZ5128-S10BB1 100-pin PQFP, 10ns tPD Commercial temp range, 5 volt power supply, 5% SOT382-1 PZ5128-S12BB1 100-pin PQFP, 12ns tPD Commercial temp range, 5 volt power supply, 5% SOT382-1 PZ5128IS10BB1 100-pin PQFP, 10ns tPD Industrial temprange, 5 volt power supply, 10% SOT382-1 PZ5128IS15BB1 100-pin PQFP, 15ns tPD Industrial temp range, 5 volt power supply, 10% SOT382-1 PZ5128-S7BBP 100-pin TQFP, 7.5ns tPD Commercial temp range, 5 volt power supply, 5% SOT386-1 PZ5128-S10BP 100-pin TQFP, 10ns tPD Commercial temp range, 5 volt power supply, 5% SOT386-1 PZ5128-S12BP 100-pin TQFP, 12ns tPD Commercial temp range, 5 volt power supply, 5% SOT386-1 PZ5128IS10BP 100-pin TQFP, 10ns tPD Industrial temp range, 5 volt power supply, 10% SOT386-1 PZ5128IS15BP 100-pin TQFP, 15ns tPD Industrial temp range, 5 volt power supply, 10% SOT386-1 PZ5128-S7BE 128-LQFP, 7.5ns tPD Commercial temp range, 5 volt power supply, 5% SOT425-1 PZ5128-S10BE 128-pin LQFP, 10ns tPD Commercial temp range, 5 volt power supply, 5% SOT425-1 PZ5128-S12BE 128-pin LQFP, 12ns tPD Commercial temp range, 5 volt power supply, 5% SOT425-1 PZ5128IS10BE 128-pin LQFP, 10ns tPD Industrial temp range, 5 volt power supply, 10% SOT425-1 PZ5128IS15BE 128-pin LQFP, 15ns tPD Industrial temp range, 5 volt power supply, 10% SOT425-1 PZ5128-S7BB2 160-pin PQFP, 7.5ns tPD Commercial temp range, 5 volt power supply, 5% SOT322-2 PZ5128-S10BB2 160-pin PQFP, 10ns tPD Commercial temp range, 5 volt power supply, 5% SOT322-2 PZ5128-S12BB2 160-pin PQFP, 12ns tPD Commercial temp range, 5 volt power supply, 5% SOT322-2 PZ5128IS10BB2 160-pin PQFP, 7.5ns tPD Industrial temp range, 5 volt poweer supply, 10% SOT322-2 PZ5128IS15BB2 160-pin PQFP, 15ns tPD Industrial temp range, 5 volt power supply, 10% SOT322-2 1997 Aug 12 3 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 From this point of view, this architecture looks like many other CPLD architectures. What makes the CoolRunner family unique is what is inside each logic block and the design technique used to implement these logic blocks. The contents of the logic block will be described next. XPLA ARCHITECTURE Figure 1 shows a high level block diagram of a 128 macrocell device implementing the XPLA architecture. The XPLA architecture consists of logic blocks that are interconnected by a Zero-power Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each logic block is essentially a 36V16 device with 36 inputs from the ZIA and 16 macrocells. Each logic block also provides 32 ZIA feedback paths from the macrocells and I/O pins. MC0 MC1 I/O MC0 LOGIC BLOCK 36 36 16 16 16 16 36 36 16 16 16 16 LOGIC BLOCK MC15 I/O MC0 LOGIC BLOCK LOGIC BLOCK MC15 I/O ZIA LOGIC BLOCK 36 16 16 16 16 36 36 16 16 16 16 LOGIC BLOCK MC1 I/O MC15 MC0 I/O I/O MC0 36 MC15 MC1 MC1 MC15 MC0 MC1 I/O MC15 MC0 MC1 MC1 MC0 LOGIC BLOCK LOGIC BLOCK MC15 MC1 I/O MC15 SP00464 Figure 1. Philips XPLA CPLD Architecture 1997 Aug 12 4 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 Each macrocell has 5 dedicated product terms from the PAL array. The pin-to-pin tPD of the PZ5128 device through the PAL array is 7.5ns. If a macrocell needs more than 5 product terms, it simply gets the additional product terms from the PLA array. The PLA array consists of 32 product terms, which are available for use by all 16 macrocells. The additional propagation delay incurred by a macrocell using 1 or all 32 PLA product terms is just 2ns. So the total pin-to-pin tPD for the PZ5128 using 6 to 37 product terms is 9.5ns (7.5ns for the PAL + 2ns for the PLA). Logic Block Architecture Figure 2 illustrates the logic block architecture. Each logic block contains control terms, a PAL array, a PLA array, and 16 macrocells. the 6 control terms can individually be configured as either SUM or PRODUCT terms, and are used to control the preset/reset and output enables of the 16 macrocells' flip-flops. The PAL array consists of a programmable AND array with a fixed OR array, while the PLA array consists of a programmable AND array with a programmable OR array. The PAL array provides a high speed path through the array, while the PLA array provides increased product term density. 36 ZIA INPUTS 6 CONTROL TO 16 MACROCELLS 5 PAL ARRAY PLA ARRAY (32) SP00435 Figure 2. Philips Logic Block Architecture 1997 Aug 12 5 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 to control the Output Enable of the macrocell's output buffers. The reason there are as many control terms dedicated for the Output Enable of the macrocell is to insure that all CoolRunner devices are PCI compliant. The macrocell's output buffers can also be always enabled or disabled. All CoolRunner devices also provide a Global Tri-State (GTS) pin, which, when pulled Low, will 3-State all the outputs of the device. This pin is provided to support "In-Circuit Testing" or "Bed-of-Nails Testing". Macrocell Architecture Figure 3 shows the architecture of the macrocell used in the CoolRunner family. The macrocell consists of a flip-flop that can be configured as either a D or T type. A D-type flip-flop is generally more useful for implementing state machines and data buffering. A T-type flip-flop is generally more useful in implementing counters. All CoolRunner family members provide both synchronous and asynchronous clocking and provide the ability to clock off either the falling or rising edges of these clocks. These devices are designed such that the skew between the rising and falling edges of a clock are minimized for clocking integrity. There are 4 clocks available on the PZ5128 device. Clock 0 (CLK0) is designated as the "synchronous" clock and must be driven by an external source. Clock 1 (CLK1), Clock 2 (CLK2), and Clock 3 (CLK3) can either be used as a synchronous clock (driven by an external source) or as an asynchronous clock (driven by a macrocell equation). There are two feedback paths to the ZIA: one from the macrocell, and one from the I/O pin. The ZIA feedback path before the output buffer is the macrocell feedback path, while the ZIA feedback path after the output buffer is the I/O pin ZIA path. When the macrocell is used as an output, the output buffer is enabled, and the macrocell feedback path can be used to feedback the logic implemented in the macrocell. When the I/O pin is used as an input, the output buffer will be 3-Stated and the input signal will be fed into the ZIA via the I/O feedback path, and the logic implemented in the buried macrocell can be fed back to the ZIA via the macrocell feedback path. It should be noted that unused inputs or I/Os should be properly terminated. Two of the control terms (CT0 and CT1) are used to control the Preset/Reset of the macrocell's flip-flop. The Preset/Reset feature for each macrocell can also be disabled. Note that the Power-on Reset leaves all macrocells in the "zero" state when power is properly applied. The other 4 control terms (CT2-CT5) can be used TO ZIA D/T Q INIT (P or R) GTS CLK0 CLK0 GND CT0 CLK1 CLK1 CT1 CLK2 CLK2 GND CLK3 CLK3 CT2 CT3 CT4 CT5 VCC GND SP00457 Figure 3. PZ5128 Macrocell Architecture 1997 Aug 12 6 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 Simple Timing Model TotalCMOS Design Technique for Fast Zero Power Figure 4 shows the CoolRunner Timing Model. The CoolRunner timing model looks very much like a 22V10 timing model in that there are three main timing parameters, including tPD, tSU, and tCO. In other competing architectures, the user may be able to fit the design into the CPLD, but is not sure whether system timing requirements can be met until after the design has been fit into the device. This is because the timing models of competing architectures are very complex and include such things as timing dependencies on the number of parallel expanders borrowed, sharable expanders, varying number of X and Y routing channels used, etc. In the XPLA architecture, the user knows up front whether the design will meet system timing requirements. This is due to the simplicity of the timing model. tPD_PAL = COMBINATORIAL PAL ONLY tPD_PLA = COMBINATORIAL PAL + PLA INPUT PIN INPUT PIN Philips is the first to offer a TotalCMOS CPLD, both in process technology and design technique. Philips employs a cascade of CMOS gates to implement its Sum of Products instead of the traditional sense amp approach. This CMOS gate implementation allows Philips to offer CPLDs which are both high performance and low power, breaking the paradigm that to have low power, you must have low performance. Refer to Figure 5 and Table 2 showing the IDD vs. Frequency of our PZ5128 TotalCMOS CPLD (data taken w/eight up/down, loadable 16 bit counters@5V, 25C. REGISTERED tSU_PAL = PAL ONLY tSU_PLA = PAL + PLA D Q OUTPUT PIN REGISTERED tCO OUTPUT PIN CLOCK SP00441 Figure 4. CoolRunner Timing Model 120 100 80 IDD (mA) 60 40 20 0 0 20 40 60 80 100 120 FREQUENCY (MHz) SP00465 Figure 5. IDD vs. Frequency @ VDD = 5.0V, 25C Table 2. IDD vs. Frequency VDD = 5.00V FREQUENCY (MHz) 0 1 20 40 60 80 100 120 Typical IDD (mA) 0.5 1 20 40 60 80 99 118 1997 Aug 12 7 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 specification: TCK, TMS, TDI, and TDO. The fifth signal defined by the JTAG specification is TRST* (Test Reset). TRST* is considered an optional signal, since it is not actually required to perform BST or ISP. The Philips PZ5128 saves an I/O pin for general purpose use by not implementing the optional TRST* signal in the JTAG interface. Instead, the Philips PZ5128 supports the test reset functionality through the use of its power up reset circuit, which is included in all Philips CPLDs. The pins associated with the power up reset circuit should connect to an external pull-up resistor to keep the JTAG signals from floating when they are not being used. JTAG Testing Capability JTAG is the commonly-used acronym for the Boundary Scan Test (BST) feature defined for integrated circuits by IEEE Standard 1149.1. This standard defines input/output pins, logic control functions, and commands which facilitate both board and device level testing without the use of specialized test equipment. BST provides the ability to test the external connections of a device, test the internal logic of the device, and capture data from the device during normal operation. BST provides a number of benefits in each of the following areas: * Testability In the Philips PZ5128, the four mandatory JTAG pins each require a unique, dedicated pin on the device. However, if JTAG and ISP are not desired in the end-application, these pins may instead be used as additional general I/O pins. The decision as to whether these pins are used for JTAG/ISP or as general I/O is made when the JEDEC file is generated. If the use of JTAG/ISP is selected, the dedicated pins are not available for general purpose use. However, unlike competing CPLD's, the Philips PZ5128 does allow the macrocell logic associated with these dedicated pins to be used as buried logic even when JTAG/ISP is selected. Table 4 defines the dedicated pins used by the four mandatory JTAG signals for each of the PZ5128 package types. - Allows testing of an unlimited number of interconnects on the printed circuit board - Testability is designed in at the component level - Enables desired signal levels to be set at specific pins (Preload) - Data from pin or core logic signals can be examined during normal operation * Reliability - Eliminates physical contacts common to existing test fixtures (e.g., "bed-of-nails") - Degradation of test equipment is no longer a concern The JTAG specifications defines two sets of commands to support boundary-scan testing: high-level commands and low-level commands. High-level commands are executed via board test software on an a user test station such as automated test equipment, a PC, or an engineering workstation (EWS). Each high-level command comprises a sequence of low level commands. These low-level commands are executed within the component under test, and therefore must be implemented as part of the TAP Controller design. The set of low-level boundary-scan commands implemented in the Philips PZ5128 is defined in Table 5. By supporting this set of low-level commands, the PZ5128 allows execution of all high-level boundary-scan commands. - Facilitates the handling of smaller, surface-mount components - Allows for testing when components exist on both sides of the printed circuit board * Cost - Reduces/eliminates the need for expensive test equipment - Reduces test preparation time - Reduces spare board inventories The Philips PZ5128's JTAG interface includes a TAP Port and a TAP Controller, both of which are defined by the IEEE 1149.1 JTAG Specification. As implemented in the Philips PZ5128, the TAP Port includes four of the five pins (refer to Table 3) described in the JTAG Table 3. JTAG Pin Description PIN NAME DESCRIPTION TCK Test Clock Output Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins, respectively. TCK is also used to clock the TAP Controller state machine. TMS Test Mode Select Serial input pin selects the JTAG instruction mode. TMS should be driven high during user mode operation. TDI Test Data Input Serial input pin for instructions and test data. Data is shifted in on the rising edge of TCK. TDO Test Data Output Serial output pin for instructions and test data. Data is shifted out on the falling edge of TCK. The signal is tri-stated if data is not being shifted out of the device. Table 4. PZ5128 JTAG Pinout by Package Type (PIN NUMBER / MACROCELL #) DEVICE PZ5128 84-pin PLCC 100-pin PQFP 100-pin TQFP 128-pin LQFP 160-pin PQFP 1997 Aug 12 TCK TMS TDI TDO 62 / 96 (F15) 64 / 96 (F15) 62 / 96 (F15) 82 / 96 (F15) 99 / 96 (F15) 23 / 48 (C15) 17 / 48 (C15) 15 / 48 (C15) 21 / 48 (C15) 22 / 48 (C15) 14 / 32 (B15) 6 / 32 (B15) 4 / 32 (B15) 8 / 32 (B15) 9 / 32 (B15) 71 / 112 (G15) 75 / 112 (G15) 73 / 112 (G15) 95 / 112 (G15) 112/ 112 (G15) 8 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 Table 5. PZ5128 Low-Level JTAG Boundary-Scan Commands INSTRUCTION (Instruction Code) Register Used DESCRIPTION Sample/Preload (0010) Boundary-Scan Register The mandatory SAMPLE/PRELOAD instruction allows a snapshot of the normal operation of the component to be taken and examined. It also allows data values to be loaded onto the latched parallel outputs of the Boundary-Scan Shift-Register prior to selection of the other boundary-scan test instructions. Extest (0000) Boundary-Scan Register The mandatory EXTEST instruction allows testing of off-chip circuitry and board level interconnections. Data would typically be loaded onto the latched parallel outputs of Boundary-Scan Shift-Register using the Sample/Preload instruction prior to selection of the EXTEST instruction. Bypass (1111) Bypass Register Places the 1 bit bypass register between the TDI and TDO pins, which allows the BST data to pass synchronously through the selected device to adjacent devices during normal device operation. The Bypass instruction can be entered by holding TDI at a constant high value and completing an Instruction-Scan cycle. Idcode (0001) Boundary-Scan Register Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind interrogation of the components assembled onto a printed circuit board. Thus, in circumstances where the component population may vary, it is possible to determine what components exist in a product. HighZ (0101) Bypass Register The HIGHZ instruction places the component in a state in which all of its system logic outputs are placed in an inactive drive state (e.g., high impedance). In this state, an in-circuit test system may drive signals onto the connections normally driven by a component output without incurring the risk of damage to the component. The HighZ instruction also forces the Bypass Register between TDI and TDO. * Field Support 5-Volt, In-System Programming (ISP) ISP is the ability to reconfigure the logic and functionality of a device, printed circuit board, or complete electronic system before, during, and after its manufacture and shipment to the end customer. ISP provides substantial benefits in each of the following areas: - Easy remote upgrades and repair - Support for field configuration, re-configuration, and customization * Design The Philips PZ5128 allows for 5-Volt, in-system programming/reprogramming of its EEPROM cells via its JTAG interface. An on-chip charge pump eliminates the need for externally-provided supervoltages, so that the PZ5128 may be easily programmed on the circuit board using only the 5-volt supply required by the device for normal operation. A set of low-level ISP basic commands implemented in the PZ5128 enable this feature. The ISP commands implemented in the Philips PZ5128 are specified in Table 6. Please note that an ENABLE command must precede all ISP commands unless an ENABLE command has already been given for a preceding ISP command and the device has not gone through a Test-Logic/Rest TAP Controller State. - Faster time-to-market - Debug partitioning and simplified prototyping - Printed circuit board reconfiguration during debug - Better device and board level testing * Manufacturing - Multi-Functional hardware - Reconfiguarability for Test - Eliminates handling of "fine lead-pitch" components for programming - Reduced Inventory and manufacturing costs - Improved quality and reliability Table 6. Low Level ISP Commands INSTRUCTION (Register Used) INSTRUCTION CODE Enable (ISP Shift Register) 1001 Enables the Erase, Program, and Verify commands. Using the ENABLE instruction before the Erase, Program, and Verify instructions allows the user to specify the outputs the device using the JTAG Boundary-Scan SAMPLE/PRELOAD command. Erase (ISP Shift Register) 1010 Erases the entire EEPROM array. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. Program (ISP Shift Register) 1011 Programs the data in the ISP Shift Register into the addressed EEPROM row. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. Verify (ISP Shift Register) 1100 Transfers the data from the addressed row to the ISP Shift Register. The data can then be shifted out and compared with the JEDEC file. The outputs during this operation can be defined by user by using the JTAG SAMPLE/PRELOAD command. 1997 Aug 12 DESCRIPTION 9 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 * Automated Test Equipment * Third party Programmers * High-End JTAG and ISP Tools JTAG and ISP Interfacing A number of industry-established methods exist for JTAG/ISP interfacing with CPLD's and other integrated circuits. The Philips PZ5128 supports the following methods: * PC Parallel Port * Workstation or PC Serial Port * Embedded Processor A Boundary-Scan Description Language (BSDL) description of the PZ5128 is also available from Philips for use in test program development. For more details on JTAG and ISP for the PZ5128, refer to the related application note: JTAG and ISP in Philips CPLDs. Table 7. Programming Specifications SYMBOL PARAMETER MIN. MAX. UNIT DC Parameters VCCP VCC supply program/verify ICCP ICC limit program/verify 4.5 5.5 V 200 mA VIH Input voltage (High) VIL Input voltage (Low) 0.8 V VSOL Output voltage (Low) 0.5 V VSOH Output voltage (High) 2.4 V TDO_IOL Output current (Low) 12 mA TDO_IOH Output current (High) -12 mA 2.0 V AC Parameters fMAX CLK maximum frequency 10 MHz PWE Pulse width erase 100 ms PWP Pulse width program 10 ms PWV Pulse width verify 10 s INIT Initialization time 100 s TMS_SU TMS setup time before TCK 10 ns TDI_SU TDI setup time before TCK 10 ns TMS_H TMS hold time after TCK 20 ns TDI_H TDI hold time after TCK 20 ns TDO_CO TDO valid after TCK 30 ns MAX. UNIT ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER MIN. VDD Supply voltage -0.5 7.0 V VI Input voltage -1.2 VDD+0.5 V VOUT Output voltage -0.5 VDD+0.5 V IIN Input current -30 30 mA IOUT Output current -100 100 mA TJ Maximum junction temperature -40 150 C Tstr Storage temperature -65 150 C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied. OPERATING RANGE 1997 Aug 12 PRODUCT GRADE TEMPERATURE Commercial 0 to +70C 5.0 5% V Industrial -40 to +85C 5.0 10% V 10 VOLTAGE Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES Commercial: 0C Tamb +70C; 4.75V VDD 5.25V PARAMETER SYMBOL TEST CONDITIONS MIN. VIL Input voltage low VDD = 4.75V VIH Input voltage high VDD = 5.25V VI Input clamp voltage VOL Output voltage low VDD = 4.75V, IOL = 12mA VOH Output voltage high VDD = 4.75V, IOH = -12mA 2.4 II Input leakage current VIN = 0 to VDD -10 IOZ 3-Stated output leakage current VIN = 0 to VDD -10 IDDQ Standby current IDDD1 current2 V -1.2 V 0.5 V 10 A 10 A V 100 A VDD = 5.25V, Tamb = 0C @ 1MHz 5 mA VDD = 5.25V, Tamb = 0C @ 50MHz 75 mA -200 mA 8 pF 12 pF 10 pF Short circuit output CIN Input pin capacitance2 Tamb = 25C, f = 1MHz CCLK Clock input capacitance2 Tamb = 25C, f = 1MHz I/O pin V VDD = 5.25V, Tamb = 0C IOS CI/O UNIT 0.8 2.0 VDD = 4.75V, IIN = -18mA Dynamic current MAX. 1 pin at a time for no longer than 1 second capacitance2 -50 5 Tamb = 25C, f = 1MHz NOTES: 1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. 2. Typical values, not tested. AC ELECTRICAL CHARACTERISTICS1 FOR COMMERCIAL GRADE DEVICES Commercial: 0C Tamb +70C; 4.75V VDD 5.25V -7 -10 -12 MIN/ MAX. MIN. MAX. MIN. MAX. UNI T Propagation delay time, input (or feedback node) to output through PAL 2 7.5 2 10 2 12 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 9.5 3 12 3 14.5 ns tCO Clock to out delay time 2 6 2 7 2 8 ns tSU_PAL Setup time (from input or feedback node) through PAL 4.5 7 8 tSU_PLA Setup time (from input or feedback node) through PAL + PLA 6.5 9 10.5 tH Hold time tCH Clock High time 3 tCL Clock Low time 3 tR Input Rise time 20 20 20 tF Input Fall time 20 20 20 fMAX1 Maximum FF toggle rate2 fMAX2 Maximum internal frequency2 fMAX3 Maximum external frequency2 tBUF Output buffer delay time tPDF_PA Input (or feedback node) to internal feedback node delay time through PAL 2 6 2 8.5 A Input (or feedback node) to internal feedback node delay time through PAL+PLA 3 8 3 10.5 tCF Clock to internal feedback node delay time 4.5 tINIT Delay from valid VDD to valid reset tER Input to output disable3 tEA SYMBOL PARAMETER tPD_PAL 0 1/(tCH + tCL) 0 4 ns ns 0 4 4 ns ns 4 ns ns ns 167 125 125 MHz 1/(tSUPAL + tCF) 111 80 69 MHz 1/(tSUPAL + tCO) 95 71 63 ns 2 10.5 ns 3 13 ns 5.5 6.5 ns 50 50 50 s 9 12 15 ns Input to output valid 9 12 15 ns tRP Input to register preset 11 12.5 15 ns tRR Input to register reset 11 12.5 15 ns tPDF_PL NOTES: 1997 Aug 12 11 1.5 MHz 1.5 L 1.5 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: SYMBOL VIL VIH VI VOL VOH II IOZ IDDQ -40C Tamb +85C; 4.5V VDD 5.5V PARAMETER Input voltage low Input voltage high Input clamp voltage Output voltage low Output voltage high Input leakage current 3-Stated output leakage current Standby current IDDD1 Dynamic current IOS CIN CCLK CI/O Short circuit output current2 Input pin capacitance2 Clock input capacitance2 I/O pin capacitance2 TEST CONDITIONS VDD = 4.5V VDD = 5.5V VDD = 4.5V, IIN = -18mA VDD = 4.5V, IOL = 12mA VDD = 4.5V, IOH = -12mA VIN = 0 to VDD VIN = 0 to VDD VDD = 5.5V, Tamb = -40C VDD = 5.5V, Tamb = -40C @ 1MHz VDD = 5.5V, Tamb = -40C @ 50MHz 1 pin at a time for no longer than 1 second Tamb = 25C, f = 1MHz Tamb = 25C, f = 1MHz Tamb = 25C, f = 1MHz MIN. MAX. 0.8 UNIT V V V V V A A A mA mA mA pF pF pF 2.0 -1.2 0.5 2.4 -10 -10 -50 5 10 10 125 6 90 -230 8 12 10 NOTES: 1. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs disabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. 2. Typical values, not tested. AC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: -40C Tamb +85C; 4.5V VDD 5.5V I10 SYMBOL PARAMETER tPD_PAL tPD_PLA tCO tSU_PAL tSU_PLA tH tCH tCL tR tF fMAX1 fMAX2 fMAX3 tBUF tPDF_PAL tPDF_PLA tCF tINIT tER tEA tRP tRR Propagation delay time, input (or feedback node) to output through PAL Propagation delay time, input (or feedback node) to output through PAL & PLA Clock to out delay time Setup time (from input or feedback node) through PAL Setup time (from input or feedback node) through PAL + PLA Hold time Clock High time Clock Low time Input Rise time Input Fall time Maximum FF toggle rate2 1/(tCH + tCL) Maximum internal frequency2 1/(tSUPAL + tCF) Maximum external frequency2 1/(tSUPAL + tCO) Output buffer delay time Input (or feedback node) to internal feedback node delay time through PAL Input (or feedback node) to internal feedback node delay time through PAL+PLA Clock to internal feedback node delay time Delay from valid VDD to valid reset Input to output disable3 Input to output valid Input to register preset Input to register reset NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 8 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. 1997 Aug 12 12 MIN. 2 3 2 8 10 I15 MAX. 10 12 7 MIN. 2 3 2 8 10.5 0 5 5 0 5 5 20 20 100 71 66 2 3 MAX. 15 17.5 8 20 20 100 69 63 1.5 8.5 10.5 6 50 15 15 15 15 2 3 1.5 13.5 16 6.5 50 15 15 17 17 UNIT ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns ns ns ns s ns ns ns ns Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 VDD = 5V, 25C 8.4 8.0 7.6 tPD_PAL (ns) 7.2 6.8 6.4 6.0 1 2 4 8 12 16 NUMBER OF OUTPUTS SWITCHING SP00472 Figure 6. tPD_PAL vs. Outputs Switching Table 8. tPD_PAL vs. Number of Outputs Switching VDD = 5.00V NUMBER OF OUTPUTS 1 2 4 8 12 16 Typical (ns) 6.6 6.8 7.0 7.2 7.4 7.6 1997 Aug 12 13 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 PIN DESCRIPTIONS 84-Pin Plastic Leaded Chip Carrier 11 1 100-Pin Plastic Quad Flat Package 100 75 12 80 1 74 QFP PLCC 32 54 33 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 * Function IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-A7 I/O-A5 I/O-A4 I/O-A2 VDD I/O-B15 (TDI) I/O-B12 I/O-B10 I/O-B8 I/O-B7 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS)* I/O-C13 I/O-C12 VDD I/O-C10 I/O-C7 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 81 30 53 Function I/O-C5 I/O-C4 I/O-C2 GND I/O-D15 I/O-D12 I/O-D10 I/O-D8 I/O-D7 VDD I/O-D4 I/O-D2 I/O-D0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E4 GND I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E15 VDD I/O-F2 I/O-F4 I/O-F5 51 31 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Function I/O-F7 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G4 VDD I/O-G7 I/O-G8 I/O-G10 I/O-G12 I/O-G15 (TDO) GND I/O-H2 I/O-H4 I/O-H5 I/O-H7 I/O-H10 VDD I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES. SP00467 * Function I/O-A5 I/O-A4 I/O-A2 I/O-A0 VDD I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS)* I/O-C13 I/O-C12 VDD I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-B9 I/O-C2 I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D10 I/O-D8 I/O-D7 Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 50 Function I/O-D5 VDD I/O-D4 I/O-D2 I/O-B0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E13 I/O-E15 VDD I/O-F0 I/O-F2 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G4 VDD Pin 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function I/O-G5 I/O-G7 I/O-G8 I/O-G10 I/O-G12 I/O-G13 I/O-G15 (TDO) GND I/O-H0 I/O-H2 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VDD I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-A8 I/O-A7 THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES. SP00468 1997 Aug 12 14 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 100-Pin Thin Quad Flat Package 100 128-Pin Low Profile Quad Flat Package 102 1 75 1 103 128 76 TQFP LQFP 25 51 65 38 26 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 * Function I/O-A2 I/O-A0 VDD I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B2 I/O-B0 I/O-C15 (TMS)* I/O-C13 I/O-C12 VDD I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C2 I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D10 I/O-D8 I/O-D7 I/O-D5 VDD Pin 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 50 Function I/O-D4 I/O-D2 I/O-D0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E12 I/O-E13 I/O-E15 VDD I/O-F0 I/O-F2 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G4 VDD I/O-G5 I/O-G7 Pin 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Function I/O-G8 I/O-G10 I/O-G12 I/O-G13 I/O-G15 (TDO) GND I/O-H0 I/O-H2 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VDD I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES. SP00485 * Function I/O-A3 I/O-A2 I/O-A0 NC NC NC VDD I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B11 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B3 I/O-B2 I/O-B0 I/O-C15 (TMS)* I/O-C13 I/O-C12 I/O-C11 VDD I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C3 I/O-C2 NC NC NC I/O-C0 GND I/O-D15 I/O-D13 I/O-D12 I/O-D11 I/O-D10 I/O-D8 39 64 Pin 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Function I/O-D7 I/O-D5 VDD I/O-D4 I/O-D3 I/O-D2 I/O-D0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E3 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E11 I/O-E12 I/O-E13 I/O-E15 VDD I/O-F0 NC NC NC I/O-F2 I/O-F3 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F11 I/O-F12 I/O-F13 I/O-F15(TCK) I/O-G0 I/O-G2 I/O-G3 I/O-G4 Pin 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Function VDD I/O-G5 I/O-G7 I/O-G8 I/O-G10 I/O-G11 I/O-G12 I/O-G13 I/O-G15 (TDO) GND NC NC NC I/O-H0 I/O-H2 I/O-H3 I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VDD I/O-H11 I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 I/O-A11 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4 THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES. SP00469A 1997 Aug 12 15 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 160-Pin Plastic Quad Flat Package Package Thermal Characteristics Philips Semiconductors uses the Temperature Sensitive Parameter (TSP) method to test thermal resistance. This method meets Mil-Std-883C Method 1012.1 and is described in Philips 1995 IC Package Databook. Thermal resistance varies slightly as a function of input power. As input power increases, thermal resistance changes approximately 5% for a 100% change in power. 121 160 120 1 PQFP 40 41 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 * Function NC NC NC NC NC NC NC VDD I/O-B15 (TDI) I/O-B13 I/O-B12 I/O-B11 I/O-B10 I/O-B8 I/O-B7 I/O-B5 GND I/O-B4 I/O-B3 I/O-B2 I/O-B0 I/O-C15 (TMS) I/O-C13 I/O-C12 I/O-C11 VDD I/O-C10 I/O-C8 I/O-C7 I/O-C5 I/O-C4 I/O-C3 I/O-C2 NC NC NC NC NC NC NC I/O-C0 GND I/O-D15 NC NC NC NC I/O-D13 I/O-D12 I/O-D11 I/O-D10 I/O-D8 I/O-D7 Figure 7 is a derating curve for the change in JA with airflow based on wind tunnel measurements. It should be noted that the wind flow dynamics are more complex and turbulent in actual applications than in a wind tunnel. Also, the test boards used in the wind tunnel contribute significantly to forced convection heat transfer, and may not be similar to the actual circuit board, especially in size. 81 Pin 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 80 Function I/O-D5 VDD I/O-D4 I/O-D3 I/O-D2 I/O-D0/CLK2 GND VDD I/O-E0/CLK1 I/O-E2 I/O-E3 I/O-E4 GND I/O-E5 I/O-E7 I/O-E8 I/O-E10 I/O-E11 I/O-E12 I/O-E13 NC NC NC NC I/O-E15 VDD I/O-F0 NC NC NC NC NC NC NC I/O-F2 I/O-F3 I/O-F4 I/O-F5 I/O-F7 I/O-F8 I/O-F10 GND I/O-F11 I/O-F12 I/O-F13 I/O-F15 (TCK) I/O-G0 I/O-G2 I/O-G3 I/O-G4 VDD I/O-G5 I/O-G7 Pin 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Function I/O-G8 I/O-G10 I/O-G11 I/O-G12 I/O-G13 I/O-G15 (TDO) GND NC NC NC NC NC NC NC I/O-H0 I/O-H2 I/O-H3 NC NC NC NC I/O-H4 I/O-H5 I/O-H7 I/O-H8 I/O-H10 VDD I/O-H11 I/O-H12 I/O-H13 I/O-H15 GND IN0/CLK0 IN2-gtsn IN1 IN3 VDD I/O-A15/CLK3 I/O-A13 I/O-A12 I/O-A11 GND I/O-A10 I/O-A8 I/O-A7 I/O-A5 I/O-A4 NC NC NC NC I/O-A3 I/O-A2 I/O-A0 84-pin PLCC 32.8 C/W 100-pin PQFP 41.2 C/W 100-pin TQFP 47.4 C/W 128-pin LQFP 45.0 C/W 160-pin PQFP 31.4 C/W PERCENTAGE REDUCTION IN JA (%) 0 10 20 30 40 PLCC/ QFP 50 0 1 2 3 4 5 AIR FLOW (m/s) SP00419A Figure 7. Average Effect of Airflow on JA THE TEST MODE SELECT (TMS) FUNCTION IS INACTIVE ON NON-ISR ARCHITECTURES. SP00470A 1997 Aug 12 JA Package 16 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 PLCC84: plastic leaded chip carrier; 84 leads; pedestal 1997 Aug 12 17 SOT189-3 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 QFP100: plastic quad flat package; 100 leads (lead length 1.6 mm); body 14 x 20 x 2.8 mm 1997 Aug 12 18 SOT382-1 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 TQFP100: plastic thin quad flat package; 100 leads; body 14 x 14 x 1.0 mm 1997 Aug 12 19 SOT386-1 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 LQFP128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm 1997 Aug 12 20 SOT425-1 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 QFP160: plastic quad flat package; 160 leads (lead length 1.6 mm); body 28 x 28 x 3.4 mm; high stand-off height 1997 Aug 12 21 SOT322-2 Philips Semiconductors Product specification 128 macrocell CPLD PZ5128 DEFINITIONS Data Sheet Identification Product Status Definition Objective Specification Formative or in Design This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. Preliminary Specification Preproduction Product This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. Product Specification Full Production This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product. Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Copyright Philips Electronics North America Corporation 1997 All rights reserved. Printed in U.S.A. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 12NC-9397 750 02644 1997 Aug 12 22