DATA SH EET
Product specification
Supersedes data of 1998 Sep 08 2003 Apr 14
INTEGRATED CIRCUITS
PCF8578
LCD row/column driver for
dot matrix graphic displays
2003 Apr 14 2
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
CONTENTS
1 FEATURES
2 APPLICATIONS
3 GENERAL DESCRIPTION
4 ORDERING INFORMATION
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Mixed mode
7.2 Row mode
7.3 Multiplexed LCD bias generation
7.4 Power-on reset
7.5 Internal clock
7.6 External clock
7.7 Timing generator
7.8 Row/column drivers
7.9 Display mode controller
7.10 Display RAM
7.11 Data pointer
7.12 Subaddress counter
7.13 I2C-bus controller
7.14 Input filters
7.15 RAM access
7.16 Display control
7.17 TEST pin
8I
2
C-BUS PROTOCOL
8.1 Command decoder
9 CHARACTERISTICS OF THE I2C-BUS
9.1 Bit transfer
9.2 Start and stop conditions
9.3 System configuration
9.4 Acknowledge
10 LIMITING VALUES
11 HANDLING
12 DC CHARACTERISTICS
13 AC CHARACTERISTICS
14 APPLICATION INFORMATION
15 CHIP DIMENSIONS AND BONDING PAD
LOCATIONS
16 CHIP-ON-GLASS INFORMATION
17 PACKAGE OUTLINES
18 SOLDERING
18.1 Introduction to soldering surface mount
packages
18.2 Reflow soldering
18.3 Wave soldering
18.4 Manual soldering
18.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
19 DATA SHEET STATUS
20 DEFINITIONS
21 DISCLAIMERS
22 PURCHASE OF PHILIPS I2C COMPONENTS
2003 Apr 14 3
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
1 FEATURES
Single chip LCD controller/driver
Stand-alone or may be used with up to 32 PCF8579s
(40960 dots possible)
40 driver outputs, configurable as 328,2416,1624 or
832 rows/columns
Selectable multiplex rates; 1 : 8, 1 : 16, 1 : 24 or 1 : 32
Externally selectable bias configuration, 5 or 6 levels
1280-bit RAM for display data storage and scratch pad
Display memory bank switching
Auto-incremented data loading across hardware
subaddress boundaries (with PCF8579)
Provides display synchronization for PCF8579
On-chip oscillator, requires only 1 external resistor
Power-on reset blanks display
Logic voltage supply range 2.5 to 6 V
Maximum LCD supply voltage 9 V
Low power consumption
I2C-bus interface
TTL/CMOS compatible
Compatible with most microcontrollers
Optimized pinning for single plane wiring in multiple
device applications (with PCF8579)
Space saving 56-lead plastic mini-pack and 64 pin quad
flat pack
Compatible with chip-on-glass technology.
2 APPLICATIONS
Automotive information systems
Telecommunication systems
Point-of-sale terminals
Computer terminals
Instrumentation.
3 GENERAL DESCRIPTION
The PCF8578 is a low power CMOS LCD row/column
driver, designed to drive dot matrix graphic displays at
multiplex rates of 1 : 8, 1 : 16, 1 : 24 or 1 : 32. The device
has 40 outputs, of which 24 are programmable,
configurable as 328,2416,1624 or 832 rows/columns.
The PCF8578 can function as a stand-alone LCD
controller/driver for use in small systems, or for larger
systems can be used in conjunction with up to
32 PCF8579s for which it has been optimized. Together
these two devices form a general purpose LCD dot matrix
driver chip set, capable of driving displays of up to
40960 dots. The PCF8578 is compatible with most
microcontrollers and communicates via a two-line
bidirectionalbus(I2C-bus).Communicationoverheadsare
minimized by a display RAM with auto-incremented
addressing and display bank switching.
4 ORDERING INFORMATION
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
PCF8578T VSO56 plastic very small outline package; 56 leads SOT190-1
PCF8578U/2 chip with bumps in tray
PCF8578H LQFP64 plastic low profile quad flat package; 64 leads; body 10 ×10 ×1.4 mm SOT314-2
2003 Apr 14 4
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
5 BLOCK DIAGRAM
Fig.1 Block diagram.
(1) Operates at LCD voltage levels, all other blocks operate at logic levels.
The pin numbers given in parenthesis refer to the LQFP64 package.
VSS
C39 - C32
R31/C31 - R8/C8
R7 - R0
17 - 56
(29 to 35, 37, 38 to 46
48 to 62, 63, 64, 1 to 6)
MSA842
VDD
PCF8578
VLCD
V2
V3
V4
V5
9 (20)
10 (21)
11 (22)
12 (23)
13 (24)
14 (25)
6 (12)
OUTPUT
CONTROLLER
ROW/COLUMN
DRIVERS
(1)
DISPLAY
MODE
CONTROLLER
Y DECODER
AND SENSING
AMPLIFIERS 32 x 40-BIT
DISPLAY RAM
X DECODER
DISPLAY
DECODER
RAM DATA POINTER
SUBADDRESS
COUNTER TIMING
GENERATOR
I C-BUS
CONTROLLER
2
INPUT
FILTERS COMMAND
DECODER
POWER-ON
RESET
OSCILLATOR
TEST
2 (8)
1 (7)
SCL
SDA
n.c. n.c. SA0
15, 16 (14, 15, 17 to 19
26 to 28 36, 47) 7 (13)
(16) 8
(11) 5
(10) 4
(9) 3
ROSC
OSC
CLK
SYNC
YX
2003 Apr 14 5
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
6 PINNING
SYMBOL PIN DESCRIPTION
VSO56 LQFP64
SDA 1 7 I2C-bus serial data input/output
SCL 2 8 I2C-bus serial clock input
SYNC 3 9 cascade synchronization output
CLK 4 10 external clock input/output
VSS 5 11 ground (logic)
TEST 6 12 test pin (connect to VSS)
SA0 7 13 I2C-bus slave address input (bit 0)
OSC 8 16 oscillator input
VDD 9 20 positive supply voltage
V2 to V510 to 13 21 to 24 LCD bias voltage inputs
VLCD 14 25 LCD supply voltage
n.c. 15, 16 14, 15, 17 to 19,
26 to 28, 36, 47 not connected
C39 to C32 17 to 24 29 to 35, 37 LCD column driver outputs
R31/C31 to R8/C8 25 to 48 38 to 46, 48 to 62 LCD row/column driver outputs
R7 to R0 49 to 56 63, 64, 1 to 6 LCD row driver outputs
2003 Apr 14 6
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.2 Pin configuration (VSO56).
1
2
3
4
5
6
7
8
9
10
11
12
13 44
43
42
41
40
39
38
37
36
35
34
33
32
31
14
15
16
17
18
19
20
22
23
24
25
26
21
46
45
47
48
49
50
51
52
53
54
55
56
27
28
30
29
MSA839
R27/C27
R26/C26
R25/C25
R24/C24
R23/C23
R22/C22
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
R16/C16
R15/C15
R14/C14
R13/C13
R12/C12
R11/C11
R10/C10
R9/C9
R8/C8
R7
R6
R5
R4
R3
R2
R1
R0
R28/C28
R29/C29
R30/C30
R31/C31
C32
C33
C34
C35
C36
C37
C38
C39
n.c.
n.c.
VLCD
V2
V3
V4
V5
VDD
OSC
SA0
TEST
CLK
SYNC
SCL
SDA
VSS
PCF8578T
2003 Apr 14 7
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.3 Pin configuration (LQFP64).
handbook, full pagewidth
PCF8578H
MBH588
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
SCL
CLK
TEST
SA0
n.c.
n.c.
OSC
VSS
SYNC
SDA
R0
R1
R2
R3
R4
R5
R6
R7
R21/C21
R20/C20
R19/C19
R18/C18
R17/C17
R16/C16
R15/C15
R14/C14
R13/C13
R12/C12
R11/C11
R10/C10
R9/C9
R8/C8
R31/C31
C35
C34
C33
n.c.
C32
C39
n.c.
n.c.
n.c.
n.c.
n.c.
n.c.
VLCD
VDD
V5
V4
V3
V2
C38
C37
C36
R30/C30
R29/C29
R28/C28
R27/C27
R26/C26
R24/C24
R25/C25
R23/C23
n.c.
R22/C22
2003 Apr 14 8
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
7 FUNCTIONAL DESCRIPTION
ThePCF8578row/columndriverisdesignedforusein one
of three ways:
Stand-alone row/column driver for small displays
(mixed mode)
Row/column driver with cascaded PCF8579s
(mixed mode)
Row driver with cascaded PCF8579s (mixed mode).
7.1 Mixed mode
In mixed mode, the device functions as both a row and
column driver. It can be used in small stand-alone
applications,or for largerdisplays withup to15 PCF8579s
(31 PCF8579s when two slave addresses are used).
See Table 1 for common display configurations.
7.2 Row mode
In row mode, the device functions as a row driver with up
to 32 row outputs and provides the clock and
synchronization signals for the PCF8579. Up to 16
PCF8579s can normally be cascaded (32 when two slave
addresses are used).
Timing signals are derived from the on-chip oscillator,
whose frequency is determined by the value of the resistor
connected between OSC and VSS.
Commands sent on the I2C-bus from the host
microcontroller set the mode (row or mixed), configuration
(multiplex rate and number of rows and columns) and
control the operation of the device. The device may have
one of two slave addresses. The only difference between
these slave addresses is the least significant bit, which is
set by the logic level applied to SA0. The PCF8578 and
PCF8579also have subaddresses. Thesubaddress ofthe
PCF8578 is only defined in mixed mode and is fixed at 0.
The RAM may only be accessed in mixed mode and data
is loaded as described for the PCF8579.
Bias levels may be generated by an external potential
divider with appropriate decoupling capacitors. For large
displays, bias sources with high drive capability should be
used. A typical mixed mode system operating with up to
15 PCF8579s is shown in Fig.5 (a stand-alone system
would be identical but without the PCF8579s).
Table 1 Possible displays configurations
Notes
1. Using 15 PCF8579s.
2. Using 16 PCF8579s.
APPLICATION MULTIPLEX
RATE MIXED MODE ROW MODE TYPICAL APPLICATIONS
ROWS COLUMNS ROWS COLUMNS
Stand alone 1 : 8 8 32 −−small digital or
alphanumerical displays
1:16 16 24 −−
1:24 24 16 −−
1:32 32 8 −−
With PCF8579 1 : 8 8(1) 632(1) 8×4(2) 640(2) alphanumeric displays and
dot matrix graphic displays
1:16 16
(1) 624(1) 16 ×2(2) 640(2)
1:24 24
(1) 616(1) 24(2) 640(2)
1:32 32
(1) 608(1) 24(2) 640(2)
2003 Apr 14 9
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
7.3 Multiplexed LCD bias generation
The bias levels required to produce maximum contrast
depend on the multiplex rate and the LCD threshold
voltage (Vth). Vth is typically defined as the RMS voltage at
which the LCD exhibits 10% contrast. Table 2 shows the
optimum voltage bias levels for the PCF8578 as functions
of Vop (Vop =V
DD VLCD), together with the discrimination
ratios (D) for the different multiplex rates. A practical value
for Vop is obtained by equating Voff(rms) with Vth. Figure 4
showsthe first 4 rowsof Table 2as graphs. Table 3shows
the relative values of the resistors required in the
configuration of Fig.5 to produce the standard multiplex
rates.
Table 2 Optimum LCD voltages
Table 3 Multiplex rates and resistor values for Fig.5
7.4 Power-on reset
At power-on the PCF8578 resets to a defined starting
condition as follows:
1. Display blank
2. 1 : 32 multiplex rate, row mode
3. Start bank, 0 selected
4. Data pointer is set to X, Y address 0, 0
5. Character mode
6. Subaddress counter is set to 0
7. I2C-bus interface is initialized.
Data transfers on the I2C-bus should be avoided for 1 ms
following power-on, to allow completion of the reset action.
PARAMETER MULTIPLEX RATE
1:8 1:16 1:24 1:32
0.739 0.800 0.830 0.850
0.522 0.600 0.661 0.700
0.478 0.400 0.339 0.300
0.261 0.200 0.170 0.150
0.297 0.245 0.214 0.193
0.430 0.316 0.263 0.230
1.447 1.291 1.230 1.196
3.370 4.080 4.680 5.190
RESISTORS MULTIPLEX RATE (n)
n = 8 n = 16, 24, 32
R1 R R
R2 R
R3
V2
Vop
---------
V3
Vop
---------
V4
Vop
---------
V5
Vop
---------
Voff rms()
V
op
----------------------
Von rms()
V
op
---------------------
DVon rms()
V
off rms()
----------------------
=
Vop
Vth
---------
n2()R
3n()Rn3()R
Fig.4 Vbias/Vop as a function of the multiplex rate.
1:8 1:16 1:32
1.0
0
0.8
MSA838
1:24
0.6
0.4
0.2
multiplex rate
Vbias
Vop
V5
V4
V3
V2
Vbias =V
2
, V3, V4, V5. See Table 2.
2003 Apr 14 10
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
ROSC OSC
VSS
SDA
SA0 CLK SYNC V3
V4
VDD
VLCD
A0
A1
A2
A3
VSS PCF8579
40
columns
SCL
VSS
SCLSDA
SA0
CLK SYNC
V3
V4
VDD
VLCD
PCF8578
VLCD
VDD
V2
V5
VSS VDD
/
VSS
LCD DISPLAY
VDD
R1
C
R2
C
R3
C
R2
C
R1
C
VSS VDD
/
VLCD subaddress 1
VSS VDD
/
40 n
columns
n
rows
HOST
MICROCONTROLLER
SCL
SDA
MSA843
Fig.5 Typical mixed mode configuration.
2003 Apr 14 11
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.6 LCD row/column waveforms.
MSA841
VDD
V2
V
V
V
V
3
4
5
LCD
Tframe
COLUMN
SYNC
VDD
V2
V
V
V
V
3
4
5
LCD
ROW 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SYNC
VDD
V2
V
V
V
V
3
4
5
LCD
COLUMN
VDD
V2
V
V
V
V
3
4
5
LCD
ROW 0
23222120191817161514131211109876543210
SYNC
VDD
V2
V
V
V
V
3
4
5
LCD
COLUMN
VDD
V2
V
V
V
V
3
4
5
LCD
ROW 0
15
SYNC
14131211109876543210
VDD
V2
V
V
V
V
3
4
5
LCD
COLUMN
VDD
V2
V
V
V
V
3
4
5
LCD
ROW 0
01234567
ON
OFF
1:8
1:16
1:24
1:32
column
display
2003 Apr 14 12
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.7 LCD drive mode waveforms for 1 : 8 multiplex rate.
MSA840
VDD
V2
V
V
V
V
3
4
5
LCD
Tframe
ROW 1
R1 (t)
VDD
V2
V
V
V
V
3
4
5
LCD
ROW 2
R2 (t)
VDD
V2
V
V
V
V
3
4
5
LCD
COL 1
C1 (t)
VDD
V2
V
V
V
V
3
4
5
LCD
COL 2
C2 (t)
dot matrix
1:8 multiplex rate
0.261 Vop
0.261 Vop
0 V
Vop
Vop
Vstate 1(t)
Vstate 2(t) 0.261 Vop
0.261 Vop
0 V
Vop
Vop
0.478 Vop
0.478 Vop
state 1 (OFF)
state 2 (ON)
Vstate 1 (t) =C1(t) R1(t):
V
on(rms)
V
op
=1
88 1
8 1
()
8=
0.430
Vstate 2 (t) = C2(t) R2(t):
V
off(rms)
V
op
=8 1
8 1
()
8=
0.297
2
2()
general relationship (n = multiplex rate)
V
on(rms)
V
op
=1
nn
1
n
1
()
n
V
off(rms)
V
op
=
n
1
n
1
()
n
2
2
()
2003 Apr 14 13
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.8 LCD drive mode waveforms for 1 : 16 multiplex rate.
MSA836
VDD
V2
V
V
V
V
3
4
5
LCD
Tframe
ROW 1
R1 (t)
VDD
V2
V
V
V
V
3
4
5
LCD
ROW 2
R2 (t)
VDD
V2
V
V
V
V
3
4
5
LCD
COL 1
C1 (t)
VDD
V2
V
V
V
V
3
4
5
LCD
COL 2
C2 (t)
dot matrix
1:16 multiplex rate
state 1 (OFF)
state 2 (ON)
0.2 Vop
0.2 Vop
0 V
Vop
Vop
Vstate 1(t)
0.2 Vop
0.2 Vop
0 V
Vop
Vop
Vstate 2(t)
0.6 Vop
0.6 Vop
Vstate 1 (t) =C1(t) R1(t):
V
on(rms)
V
op
=1
16 16 1
16 1
()
16 =0.316
Vstate 2 (t) = C2(t) R2(t):
V
off(rms)
V
op
=16 1
16 1
()
16 =0.254
2
2()
general relationship (n = multiplex rate)
V
on(rms)
V
op
=1
nn
1
n
1
()
n
V
off(rms)
V
op
=
n
1
n
1
()
n
2
2
()
2003 Apr 14 14
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
7.5 Internal clock
The clock signal for the system may be generated by the
internal oscillator and prescaler. The frequency is
determined by the value of the resistor ROSC, see Fig.9.
For normal use a value of 330 k is recommended.
The clock signal, for cascaded PCF8579s, is output at
CLK and has a frequency 16 (multiplex rate 1 : 8, 1 : 16
and 1 : 32) or 18 (multiplex rate 1 : 24) of the oscillator
frequency.
Fig.9 Oscillator frequency as a function of
external oscillator resistor, ROSC.
To avoid capacitive coupling, which could adversely affect oscillator
stability, ROSC should be placed as closely as possible to the OSC
pin. If this proves to be a problem, a filtering capacitor may be
connected in parallel to ROSC.
10
MSA837
102103104
1
103
10
102
fOSC
(kHz)
R(k)
OSC
7.6 External clock
If an external clock is used, OSC must be connected to
VDD and the external clock signal to CLK. Table 4
summarizes the nominal CLK and SYNC frequencies.
7.7 Timing generator
The timing generator of the PCF8578 organizes the
internal data flow of the device and generates the LCD
frame synchronization pulse SYNC, whose period is an
integer multiple of the clock period. In cascaded
applications, this signal maintains the correct timing
relationship between the PCF8578 and PCF8579s in the
system.
7.8 Row/column drivers
Outputs R0 to R7 and C32 to C39 are fixed as row and
column drivers respectively. The remaining 24 outputs
R8/C8 to R31/C31 are programmable and may be
configured (in blocks of 8) to be either row or column
drivers. The row select signal is produced sequentially at
each output from R0 up to the number defined by the
multiplex rate (see Table 1). In mixed mode the remaining
outputs are configured as columns. In row mode all
programmableoutputs (R8/C8 to R31/C31) aredefinedas
row drivers and the outputs C32 to C39 should be left
open-circuit.
Using a 1 : 16 multiplex rate, two sets of row outputs are
driven, thus facilitating split-screen configurations, i.e. a
row select pulse appears simultaneously at R0 and
R16/C16,R1and R17/C17 etc. Similarly, usinga multiplex
rate of 1 : 8, four sets of row outputs are driven
simultaneously. Driver outputs must be connected directly
to the LCD. Unused outputs should be left open-circuit.
In 1 : 8 R0 to R7 are rows; in 1 : 16 R0 to R15/C15 are
rows; in 1 : 24 R0 to R23/C23 are rows; in 1 : 32
R0 to R31/C31 are rows.
Table 4 Signal frequencies required for nominal 64 Hz frame frequency; note 1.
Notes
1. A clock signal must always be present, otherwise the LCD may be frozen in a DC state.
2. ROSC = 330 k.
OSCILLATOR
FREQUENCY
fOSC(2) (Hz)
FRAME FREQUENCY
fSYNC (Hz) MULTIPLEX RATE (n) DIVISION
RATIO CLOCK FREQUENCY
fCLK (Hz)
12288 64 1 : 8, 1 : 16, 1 : 32 6 2048
12288 64 1 : 24 8 1536
2003 Apr 14 15
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
7.9 Display mode controller
The configuration of the outputs (row or column) and the
selection of the appropriate driver waveforms are
controlled by the display mode controller.
7.10 Display RAM
The PCF8578 contains a 32 ×40-bit static RAM which
stores the display data. The RAM is divided into 4 banks
of 40 bytes (4 ×8×40 bits). During RAM access, data is
transferred to/from the RAM via the I2C-bus. The first
eight columns of data (0 to 7) cannot be displayed but
are available for general data storage and provide
compatibility with the PCF8579. There is a direct
correspondence between X-address and column output
number.
7.11 Data pointer
The addressing mechanism for the display RAM is
realized using the data pointer. This allows an individual
databyte or aseriesofdatabytesto be written into,orread
from, the display RAM, controlled by commands sent on
the I2C-bus.
7.12 Subaddress counter
The storage and retrieval of display data is dependent on
the content of the subaddress counter. Storage takes
place only when the contents of the subaddress counter
agree with the hardware subaddress. The hardware
subaddress of the PCF8578, valid in mixed mode only, is
fixed at 0000.
7.13 I2C-bus controller
The I2C-bus controller detects the I2C-bus protocol, slave
address, commands and display data bytes. It performs
the conversion of the data input (serial-to-parallel) and the
data output (parallel-to-serial). The PCF8578 acts as an
I2C-bus slave transmitter/receiver in mixed mode, and as
a slave receiver in row mode. A slave device cannot
control bus communication.
7.14 Input filters
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.15 RAM access
RAM operations are only possible when the PCF8578 is
in mixed mode.
In this event its hardware subaddress is internally fixed at
0000 and the hardware subaddresses of any PCF8579
used in conjunction with the PCF8578 must start at 0001.
There are three RAM ACCESS modes:
Character
Half-graphic
Full-graphic.
These modes are specified by bits G1 to G0 of the RAM
ACCESS command. The RAM ACCESS command
controls the order in which data is written to or read from
the RAM (see Fig.10).
To store RAM data, the user specifies the location into
which the first byte will be loaded (see Fig.11):
Device subaddress (specified by the DEVICE SELECT
command)
RAM X-address (specified by the LOAD X-ADDRESS
command)
RAM bank (specified by bits Y1 and Y0 of the RAM
ACCESS command).
Subsequent data bytes will be written or read according to
the chosen RAM ACCESS mode. Device subaddresses
are automatically incremented between devices until the
last device is reached. If the last device has
subaddress 15, further display data transfers will lead to a
wrap-around of the subaddress to 0.
7.16 Display control
The display is generated by continuously shifting rows of
RAM data to the dot matrix LCD via the column outputs.
The number of rows scanned depends on the multiplex
rate set by bits M1 and M0 of the SET MODE command.
The display status (all dots on/off and normal/inverse
video) is set by bits E1 and E0 of the SET MODE
command. For bank switching, the RAM bank
corresponding to the top of the display is set by bits
B1 and B0 of the SET START BANK command. This is
shown in Fig.12. This feature is useful when scrolling in
alphanumeric applications.
7.17 TEST pin
The TEST pin must be connected to VSS.
2003 Apr 14 16
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
MSA849
01234567891011
0246810121416182022
1357911131517192123
04 8 12 16 20 24 28 32 36 40 44
1 5 9 13 17 21 25 29 33 37 41 45
2 6 10 14 18 22 26 30 34 38 42 46
3 7 11 15 19 23 27 31 35 39 43 47
RAM data bytes are
written or read as
indicated above
full-graphic mode
LSB
MSB
bank 0
bank 1
bank 2
bank 3
PCF8578/PCF8579 system RAM
1 k 16
half-graphic mode
character mode
1 byte
4 bytes
RAM
2 bytes
4 bytes
40-bits
driver 1 driver 2 driver k
PCF8578/PCF8579 PCF8579
Fig.10 RAM ACCESS mode.
2003 Apr 14 17
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in
_white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in
white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ...
MSA835
S
A
0
S011110 0A
slave address
/RW
0
110110 A
DEVICE SELECT
10
000100 A
LOAD X-ADDRESS
11
111000 A
RAM ACCESS
0
last command
S
A
0
S011110 1A
slave address
/RW
DATA A
READ
WRITE DATA A DATA A
DEVICE SELECT:
subaddress 12
RAM ACCESS:
character mode
bank 1
LOAD X-ADDRESS: X-address = 8
RAM
bank 0
bank 1
bank 2
bank 3
Fig.11 Example of commands specifying initial data byte RAM locations.
2003 Apr 14 18
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.12 Relationship between display and SET START BANK; 1 : 32 multiplex rate and start bank = 2.
MSA851
bank 0
top of LCD
bank 1
bank 2
bank 3
LCD
RAM
2003 Apr 14 19
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
8I
2
C-BUS PROTOCOL
Two 7-bit slave addresses (0111100 and 0111101) are
reserved for both the PCF8578 and PCF8579. The least
significant bit of the slave address is set by connecting
inputSA0to either 0 (VSS)or1(VDD).Therefore,twotypes
of PCF8578 or PCF8579 can be distinguished on the
same I2C-bus which allows:
1. One PCF8578 to operate with up to 32 PCF8579s on
the same I2C-bus for very large applications
2. The use of two types of LCD multiplex schemes on the
same I2C-bus.
InmostapplicationsthePCF8578willhavethesameslave
address as the PCF8579.
The I2C-bus protocol is shown in Fig.13.
All communications are initiated with a start condition (S)
from the I2C-bus master, which is followed by the desired
slaveaddress and read/write bit.All devices withthis slave
address acknowledge in parallel. All other devices ignore
the bus transfer.
In WRITE mode (indicated by setting the read/write bit
LOW) one or more commands follow the slave address
acknowledgement. The commands are also
acknowledged by all addressed devices on the bus.
The last command must clear the continuation bit C.
After the last command a series of data bytes may follow.
The acknowledgement after each byte is made only by the
(A0, A1, A2 and A3) addressed PCF8579 or PCF8578
with its implicit subaddress 0. After the last data byte
has beenacknowledged,the I2C-bus master issuesa stop
condition (P).
In READ mode, indicated by setting the read/write bit
HIGH, data bytes may be read from the RAM following the
slave address acknowledgement. After this
acknowledgement the master transmitter becomes a
master receiver and the PCF8578 becomes a slave
transmitter. The master receiver must acknowledge the
reception of each byte in turn. The master receiver must
signal an end of data to the slave transmitter, by not
generating an acknowledge on the last byte clocked out of
the slave. The slave transmitter then leaves the data line
HIGH, enabling the master to generate a stop condition
(P).
Display bytes are written into, or read from, the RAM at the
address specified by the data pointer and subaddress
counter.Boththedata pointer and subaddress counterare
automaticallyincremented,enablingastream of data to be
transferred either to, or from, the intended devices.
In multiple device applications, the hardware subaddress
pins of the PCF8579s (A0 to A3) are connected to VSS or
VDD to represent the desired hardware subaddress code.
If two or more devices share the same slave address, then
each device must be allocated a unique hardware
subaddress.
2003 Apr 14 20
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Fig.13 (a) Master transmits to slave receiver (WRITE mode); (b) Master reads after sending command string
(WRITE commands; READ data); (c) Master reads slave immediately after sending slave address (READ
mode).
MSA830
S
A
0
S011110 0AC COMMAND AP
ADISPLAY DATA
slave address /RW
acknowledge by
all addressed
PCF8578s / PCF8579s
acknowledge
by A0, A1, A2 and A3
selected PCF8578s /
PCF8579s only
n 0 byte(s)n 0 byte(s)1 byte
update data pointers
and if necessary,
subaddress counter
(a)
MSA832
S
A
0
S011110 0AC COMMAND A
slave address
/RW
acknowledge by
all addressed
PCF8578s / PCF8579s
n 1 byte
(b)
ADATA
S
A
0
S011110 1A
slave address
/RW
P
1DATA
n bytes last byte
update data pointers
and if necessary
subaddress counter
acknowledge
from master no acknowledge
from master
at this moment master
transmitter becomes a
master receiver and
PCF8578/PCF8579 slave
receiver becomes a
slave transmitter
MSA831
S
A
0
S011110 1A DATA AP
1DATA
slave address
/RW
acknowledge by
all addressed
PCF8578s / PCF8579s
last byten bytes
update data pointers
and if necessary,
subaddress counter
(c)
acknowledge
from master no acknowledge
from master
2003 Apr 14 21
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
8.1 Command decoder
The command decoder identifies command bytes that
arrive on the I2C-bus. The most-significant bit of a
commandisthecontinuation bit C (see Fig.14). When this
bitisset, it indicates thatthe next byteto be transferred will
also be a command. If the bit is reset, it indicates the
conclusion of the command transfer. Further bytes will be
regarded as display data. Commands are transferred in
WRITE mode only.
The five commands available to the PCF8578 are defined
in Tables 5 and 6. Fig.14 General information of command byte.
MSA833
REST OF OPCODE
C
MSB LSB
C = 0; last command.
C = 1; commands continue.
Table 5 Summary of commands
Note
1. C = command continuation bit. D = may be a logic 1 or 0.
COMMAND OPCODE(1) DESCRIPTION
SET MODE C 1 0 D D D D D multiplex rate, display status, system type
SET START BANK C 1 1 1 1 1 D D defines bank at top of LCD
DEVICE SELECT C 1 1 0 D D D D defines device subaddress
RAM ACCESS C 1 1 1 D D D D graphic mode, bank select (D D D D 12 is not
allowed; see SET START BANK opcode)
LOAD X-ADDRESS C 0 D D D D D D 0 to 39
2003 Apr 14 22
Philips Semiconductors Product specification
LCD row/column driver for
dot matrix graphic displays PCF8578
Table 6 Definition of PCF8578/PCF8579 commands
COMMAND OPCODE OPTIONS DESCRIPTION
SET MODE C 1 0 T E1 E0 M1 M0 see Table 7 defines LCD drive mode
see Table 8 defines display status
see Table 9 defines system type
SET START BANK C 1 1 1 1 1 B1 B0 see Table 10 defines pointer to RAM bank
corresponding to the top of the LCD;
useful for scrolling, pseudo-motion and
background preparation of new display
DEVICE SELECT C 1 1 0 A3 A2 A1 A0 see Table 11 four bits of immediate data, bits
A0 to A3, are transferred to the
subaddress counter to define one of
sixteen hardware subaddresses
RAM ACCESS C 1 1 1 G1 G0 Y1 Y0 see Table 12 defines theauto-increment behaviour of
the address for RAM access
see Table 13 two bits of immediate data, bits Y0 to
Y1, are transferred to the X-address
pointer to define one of forty display
RAM columns
LOAD X-ADDRESS C 0 X5 X4 X3 X2 X1 X0 see Table 14 six bits of immediate data, bits
X0 to X5, are transferred to the
X-address pointer to define one of forty
display RAM columns