intel PRELIMINARY 2764 (8K x 8) UV ERASABLE PROM @ 200 ns (2764-2) Maximum Access a Pin Compatible to 2732A EPROM Time ... HMOS*-E Technology = Industry Standard Pinout... JEDEC = Compatible to High Speed 8mHz Approved 8086-2 MPU... Zero WAIT State @ Low Active Current...100mA Max. a Two Line Control The Intel 2764 is a 5V only, 65,536-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The standard 2764 access time is 250ns with speec selection available at 200ns. The access time is compatible to high performance microprocessors, such as Intels 8mHz 8086-2. In these systems, the 2764 allows the microprocessor to operate without the addition of WAIT states. An important 2764 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The OE control eliminates bus contention in multiple bus microprocessor systems. Intels Application Note AP-72 describes the microprocessor system implementation of the CE.and CE controls on Intels EPROMs. AP-72 is available from Intels Literature Department. The 2764 has a standby mode which reduces the power dissipation without increasing access time. The active current is 150mA while the standby current is only 50mA. The standby mode is achieved by applying a TTL-high signal to the CE input. The 2764 is fabricated with HMOS*-E technology, Intels high-speed N-channel MOS Silicon Gate Technology. 2764 BLOCK DIAGRAM 2732A PIN CONFIGURATION Veco DATs OUTPUTS PIN CONFIGURATION vee]: 7 1 vec GNOO e AvC]2 27) FGM Vep o ! tT] | I I | arta 26[-) N.clt | Ae(}4 25 [7] As OUTPUT ENABLE "| A aot */ CHIP ENABLE sys a AND OUTPUT BUFFERS Aa( ye 23 An &E *] PROG Loic a3(]7 227) OE | = y Y.GATING aetqe 21[7 Ato A-Ag | "L_DECODER +- aiChs 20 [7] cE ADDRESS < ag (10 191] 07 mers = ; 65.536-BIT oof" Wh 06 =S] CECODER CELL MATIX ore EJ os +4 02413 16 [-} O4 GND [7] 14 1$[_] 03 [1] For total compatibility and upgradability trom the 2732A and MODE SELECTION ROMs provide a trace to pin 26. PINS | CE| OE | PGM | V,, Veo Outputs 118, 1578) PIN NAMES OUTPUT ENABLE x can be either V or Via N.C. NO CONNECT *HMOS is a patented process of Intel Corporation. 2-172764 PRELIMINARY PROGRAMMING The programming specifications are described in the Data Catalog PROM/ROM Programming Instructions Section. ABSOLUTE MAXIMUM RATINGS* COMMENT. Stresses above those listed under Absolute Maximum Ratings may cause Temperature Under Bias ...............++ 10C to +80C permanent damage to the device. Thisis a stress rating only and functional REC: operation of the device at these or any other conditions above those Storage Temperature seers seer eee r eres 65C to +125C indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods Ail Input or Output Voltages with may affect device reliability. Respect to Ground Veep Supply Voltage with Respect to Ground During Programming D.C. and A.C. Operating Conditions During Read 2764 2764-2 2764-3 2764-4 Operating Temperature Range oc-70C oc-70C oc-70C 0C-70C Voco Power Supply? 5V+ 5% 5V + 5% 5V + 5% 5V +5% Vpp Voltage? Ver = Vec Vpe = Voc Ver = Veo Vor = Vec READ OPERATION D.C. AND OPERATING CHARACTERISTICS Limits Symbol Parameter Min Typ? | Max Unit Conditions ha Input Load Current 10 BA Vin = 5.25V loo Output Leakage Current 10 BA Vour = 5.25V | ppy? Vpp Current Read 15 mA Vep= 5.25V loot? Veo Current Standby 50 mA | CE=Va lees? Voc Current Active 70 =| 150 mA | CE=0E=\ Mi Input Low Voltage -A +.8 v Van Input High Voltage 2.0 Vect+1 Vv Vor Output Low Voltage 45 Vv lo. = 2.1 MA Vou Output High Voltage 2.4 Vv lon = 400 pA NOTES: 1. Vc. must be applied: simultaneously or before V,, and removed simultaneously or after Vop. 2. Vpp may be connected directly to V,, except during programming. The supply current would then be the sum of Icc and Iper- 3. Typical values are for T, = 25C and nominal supply voltages. 2-18 AFN-O167442764 PRELIMINARY A.C. CHARACTERISTICS 2764-2 Limits | 2764 Limits | 2764-3 Limits | 2764-4 Limits Test Symbol , Parameter Min | Max | Min | Max | Min | Max | Min | Max | Unit Conditions tacc Address to Output Delay 200 250 300 450 ns CE=OE=V), tog CE to Output Delay 200 250 300 450 ns OE=Vit toe Output Enable to Output 10 70 10 100 10 150 10 150 ns CE=Vi, Delay . tor Output Enable High to 0 60 0 90 0 130 0 130 ns CE=V yc Output Float ton Output Hold from Addresses, 0 0 0 0 ns CE=OE=Vi, CE or OE Whichever Occurred First CAPACITANCE "I 1, = 25C, f= 1MHz A.C. TEST CONDITIONS Symbol Parameter Typ. | Max. | Unit {| Conditions Output Load: 1 TTL gate and Ci = 100pF Cw Input Capacitance 4 6 pF Vin=OV tnput Rise and Fal! Times: < 20ns ~ Input Pulse Levels: 0.8V to 2.2V Cour__ [Output Capacitance 8 12 |_PF Vour=0V Timing Measurement Reference Level: Inputs 1V and 2V Outputs 0.8V and 2V A.C. WAVEFORMS ADDRESSES a snes a, tce 9 -_+| OE / Le D toH } peer oe HIGH Z / | 7 , , HIGH Z OUTPUT x \ . \ VALID OUTPUT ee NOTES: 1. Typical values are for T, = 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. _ 3. OE may be delayed up to tacc tee after the falling edge of CE without impact on tac. 4. tor is specified from OE or CE, whichever occurs first. 2-19 AFN-01647A2764 PRELIMINARY ERASURE CHARACTERISTICS The erasure characteristics of the 2764 are such that erasure begins to occur when exposed to light with wavelengths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 A range. Data show that constant exposure to room level fluorescent lighting could erase the typical 2764 in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the 2764 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels are available from Intel which should be placed over the 2764 window to prevent unintentional erasure. The recommended erasure procedure for the 2764 is expo- sure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity X exposure time) for erasure should be a minimum of 15 W-sec/cm?. The erasure time with this dosage is approxi- mately 15 to 20 minutes using an ultraviolet lamp with 12000 uW/cm? power rating. The 2764 should be placed within 1 inch of the lamp tubes during erasure. Some lamps have a filter on their tubes which should be removed before erasure. DEVICE OPERATION The five modes of operation of the 2764 are listed in Table 1.A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vp. TABLE 1. MODE SELECTION PINS | CE| OE|PGM| V..| Voc} Outputs MODE (20)} (22)) (27) | (1) | (28)|(11-13, 15-19) Read Me] Ved Ma | Veo} Vee | Dour Standby Vial x x | Mecl Veo | High Z Program Mi x Vic | Ver | Veco | Din Program Verify| Vic] Vic] Va | Vee | Veco | Dour Program Inhibit] Vi, x xX | Vep}| Veco} High Z x can be either V, or Via READ MODE The 2764 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (OE) is the output control and should be used to gate data to the output pins, indepen- dent of device selection. Assuming that addresses are stable, address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the outputs after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacctoe. Standby Mode The 2764 has a standby mode which reduces the active power current from 150mA to 50mA. The 2764 is placed in the standby mode by applying a TTL high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE input. Output OR-Tieing Because EPROMs are usually used in larger memory arrays, Intel has provided a 2 line control function that accommo- dates this use of multiple memory connection. The two line control function allows for: a) the lowest possible memory power dissipation, and b) compiete assurance that output bus contention will not occur. To most efficiently use these two control lines, it is recom- mended that CE (pin 20) be decoded and used as the primary device selecting function, while OE (pin 22) be made a com- mon connection to all devices in the array and connected to the READ line from the system control bus. This assures that all deselected memory devices are in their low power standby mode and that the output pins are only active when data is desired from a particular memory device. PROGRAMMING (See Programming instruction Section for Waveforms.) __ Programming is the same as Intels 2732A except that OE/Vpp is not multiplexed. They have separate pins. Like the 2732A, exceeding 21.5V will damage the 2764. Initially, and after each erasure, all bits of the 2764 are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Although only Os will be programmed, both 1s and '0s can be present in the data word. The only way to change a 0 to a'1 is by ultraviolet light erasure. The 2764 is in the programming mode when V>p inputis at 21V and CE and PGM are both at TTL low. The data to be pro- grammed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL. For programming, CE should be kept TTL low at all times while Vpp is kept at 21V. When the address and data are stable, a 50 msec, active low, TTL program pulse is applied to PGM input. A program pulse must be applied at each address location to be programmed. You can program any location at any timeeither individually, sequentially, or at random. The program pulse has a maximum width of 55 msec. Programming of multiple 2764s in parallel with the same data can be easily accomplished due to the simplicity of the pro- gramming requirements. Like inputs of the paralleled 2764s may be connected together when they are programmed with the same data. A low level TTL pulse applied to the PGM input programs the paralleled 2764s. 2-202764 PRELIMINARY Program Inhibit Program Verify Programming of multiple 2764s in parallel with different data A verify should be performed on the programmed bits to is also easily accomplished. A high level CE or PGM input determine that they were correctly programmed. The The verify is inhibits the other 2764s from being programmed. Except for accomplished with CE and OE at V.. However, PGM is at Vin. GE (or PGM), all like inputs (including OE) of the parallel 2764s may be common. A TTL low level pulse applied to a 2764 CE and PGM input with Vpp at 21V will program that 2764. 2-21