64-Position OTP Digital Potentiometer
AD5171
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2008 Analog Devices, Inc. All rights reserved.
FEATURES
64 position
One-time programmable (OTP) set-and-forget resistance
setting—low cost alternative over EEMEM
Unlimited adjustments prior to OTP activation
5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ end-to-end resistance
Low temperature coefficient: 5 ppm/°C in potentiometer mode
Low temperature coefficient: 35 ppm/°C in rheostat mode
Compact standard 8-lead SOT-23 package
Low power: IDD = 10 μA maximum
Fast settling time: tS = 5 μs typical in power-up
I2C-compatible digital interface
Computer software replaces microcontroller in factory
programming applications
Full read/write of wiper register
Extra I2C device address pin
Low operating voltage: 2.7 V to 5.5 V
OTP validation check function
Automotive temperature range: −40°C to +125°C
APPLICATIONS
System calibrations
Electronics level settings
Mechanical trimmers and potentiometer replacements
Automotive electronics adjustments
Gain control and offset adjustments
Transducer circuit adjustments
Programmable filters up to 1.5 MHz BW1
GENERAL DESCRIPTION
The AD5171 is a 64-position, one-time programmable (OTP)
digital potentiometer2 that uses fuse link technology to achieve
the memory retention of the resistance setting function. OTP is
a cost-effective alternative over the EEMEM approach for users
who do not need to reprogram new memory settings in the
digital potentiometer. This device performs the same electronic
adjustment function as most mechanical trimmers and variable
resistors. The AD5171 is programmed using a 2-wire, I2C®-
compatible digital control. It allows unlimited adjustments
before permanently setting the resistance value. During the
OTP activation, a permanent fuse blown command is sent after the
final value is determined, freezing the wiper position at a given
setting (analogous to placing epoxy on a mechanical trimmer).
FUNCTIONAL BLOCK DIAGRAM
GND
A
W
B
V
DD
AD0
SDA
SCL
AD5171
03437-001
WIPER
REGISTER
I
2
C INTERFACE
AND
CONTROL LOGIC
FUSE
LINK
Figure 1.
W1
VDD 2
GND 3
SCL 4
A8
B
7
AD0
6
SDA
5
AD5171
TOP VIEW
(Not to Scale)
03437-002
Figure 2. Pin Configuration
When this permanent setting is achieved, the value does not
change regardless of supply variations or environmental stresses
under normal operating conditions. To verify the success of
permanent programming, Analog Devices, Inc., patterned the
OTP validation such that the fuse status can be discerned from
two validation bits in read mode.
For applications that program the AD5171 in factories, Analog
Devices offers device programming software that operates
across Windows® 95 to XP platforms, including Windows NT.
This software application effectively replaces the need for external
I2C controllers or host processors and, therefore, significantly
reduces the development time of the users.
An AD5171 evaluation kit includes the software, connector, and
cable that can be converted for factory programming applications.
The AD5171 is available in a compact 8-lead SOT-23 package.
All parts are guaranteed to operate over the automotive temper-
ature range of −40°C to +125°C. Besides its unique OTP feature,
the AD5171 lends itself well to other general-purpose digital
potentiometer applications due to its temperature performance,
small form factor, and low cost.
1 Applies to 5 kΩ parts only.
2 The terms digital potentiometer and RDAC are used interchangeably.
AD5171
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics: 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ .. 3
Timing Characteristics: 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ ...... 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 12
One-Time Programming (OTP) .............................................. 12
Variable Resistance and Voltage for Rheostat Mode ............. 13
Variable Resistance and Voltage for Potentiometer Mode .... 13
Power Supply Considerations ................................................... 14
ESD Protection ........................................................................... 14
Terminal Voltage Operating Range .......................................... 15
Power-Up/Power-Down Sequences ......................................... 15
Controlling the AD5171 ................................................................ 16
Software Programming ............................................................. 16
Device Programming ................................................................. 16
I2C Controller Programming .................................................... 17
I2C-Compatible 2-Wire Serial Bus ........................................... 17
Controlling Two Devices on One Bus ..................................... 18
Applications Information .............................................................. 19
DAC .............................................................................................. 19
Gain Control Compensation .................................................... 19
Programmable Voltage Source with Boosted Output ........... 19
Level Shifting for Different Voltage Operation ...................... 19
Resistance Scaling ...................................................................... 19
Resolution Enhancement .......................................................... 20
RDAC Circuit Simulation Model ............................................. 20
Evaluation Board ............................................................................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
7/08—Rev. C to Rev. D
Changes to Power Supplies Parameter in Table 1.........................3
Updated Fuse Blow Condition to 400 ms Throughout ...............5
1/08—Rev. B to Rev. C
Updated Format .................................................................. Universal
Deleted Note 1; Renumbered Sequentially ................................... 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 6
Changes to Table 4 ............................................................................ 7
Changes to Figure 13 to Figure 16 .................................................. 9
Changes to Figure 17 and Figure 18 ............................................. 10
Inserted Figure 24 ........................................................................... 11
Changes to One-Time Programming (OTP) Section and Power
Supply Considerations Section ..................................................... 12
Deleted Figure 25 and Figure 26 ................................................... 13
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
1/05—Rev. A to Rev. B
Change to Features ............................................................................ 1
Changes to Electrical Characteristics ............................................. 3
Change to Table 3 .............................................................................. 6
Changes to Power Supply Considerations Section .................... 13
Changes to Level Shifting for Different Voltage Operation
Sect ion .............................................................................................. 19
Added Note to Ordering Guide .................................................... 22
11/04—Rev. 0 to Rev. A
Changes to Specifications ................................................................. 3
Changes to Table 3 ............................................................................. 7
Changes to One-Time Programming Section ............................ 11
Changes to Power Supply Consideration Section ...................... 11
Changes to Figure 26 and Figure 27............................................. 12
1/04—Revision 0: Initial Version
AD5171
Rev. D | Page 3 of 24
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 3 V to 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ1Max Unit
DC CHARACTERISTICS RHEOSTAT MODE
Resistor Differential Nonlinearity2R-DNL RWB, VA = no connect,
RAB = 10 kΩ, 50 kΩ, and 100 kΩ
−0.5 ±0.1 +0.5 LSB
R
WB, VA = no connect, RAB = 5 kΩ −1 ±0.25 +1 LSB
Resistor Integral Nonlinearity2
R-INL RWB, VA = no connect,
RAB = 10 kΩ, 50 kΩ, and 100 kΩ
−1.5 ±0.35 +1.5 LSB
R
WB, VA = no connect, RAB = 5 kΩ −1.5 ±0.5 +1.5 LSB
Nominal Resistor Tolerance3∆RAB/RAB −30 +30 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T 35 ppm/°C
Wiper Resistance RW V
DD = 5 V 60 115 Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER
MODE (SPECIFICATIONS APPLY TO ALL RDACs)
Resolution N 6 Bits
Differential Nonlinearity4DNL −0.5 ±0.1 +0.5 LSB
Integral Nonlinearity4 INL −1 ±0.2 +1 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T Code = 0x20 5 ppm/°C
Full-Scale Error VWFSE Code = 0x3F, RAB = 10 kΩ,
50 kΩ, and 100 kΩ
−1 −0.5 0 LSB
Full-Scale Error VWFSE Code = 0x3F, RAB = 5 kΩ −1.5 0 LSB
Zero-Scale Error VWZSE Code = 0x00, RAB =10 kΩ,
50 kΩ, and 100 kΩ
0 0.5 1 LSB
Code = 0x00, RAB = 5 kΩ 0 2 LSB
RESISTOR TERMINALS
Voltage Range5VA, VB, VW With respect to GND VDD V
Capacitance A, B6CA, CB f = 1 MHz, measured to GND,
code = 0x20
25 pF
Capacitance W6
CW f = 1 MHz, measured to GND,
code = 0x20
55 pF
Common-Mode Leakage ICM V
A = VB = VDD/2 1 nA
DIGITAL INPUTS
Input Logic High (SDA and SCL)7 VIH 0.7 VDD V
DD + 0.5 V
Input Logic Low (SDA and SCL)7 VIL −0.5 +0.3 VDD V
Input Logic High (AD0) VIH V
DD = 3 V 3.0 VDD V
Input Logic Low (AD0) VIL V
DD = 3 V 0 1.0 V
Input Current IIL V
IN = 0 V or 5 V ±1 μA
Input Capacitance8CIL 3 pF
DIGITAL OUTPUTS
Output Logic Low (SDA) VOL I
OL = 6 mA 0.4 V
Three-State Leakage Current (SDA) IOZ V
IN = 0 V or 5 V ±1 μA
Output Capacitance8
COZ 3 pF
POWER SUPPLIES
Power Supply Range VDD 2.7 5.5 V
OTP Power Supply7, 9
VDD_OTP TA = 25°C 4.75 5 5.25 V
Supply Current IDD V
IH = 5 V or VIL = 0 V 4 10 μA
OTP Supply Current7, 10, 11
IDD_OTP V
DD_OTP = 5 V, TA = 25°C 100 mA
Power Dissipation12 PDISS V
IH = 5 V or VIL = 0 V, VDD = 5 V 0.02 0.055 mW
Power Supply Sensitivity PSSR −0.025 +0.001 +0.025 %/%
AD5171
Rev. D | Page 4 of 24
Parameter Symbol Conditions Min Typ1Max Unit
DYNAMIC CHARACTERISTICS8, 13 , 14
–3 dB Bandwidth BW_5k RAB = 5 kΩ, code = 0x20 1500 kHz
BW_10k RAB = 10 kΩ, code = 0x20 600 kHz
BW_50k RAB = 50 kΩ, code = 0x20 110 kHz
BW_100k RAB = 100 kΩ, code = 0x20 60 kHz
Total Harmonic Distortion THD VA = 1 V rms, RAB = 10 kΩ,
VB = 0 V dc, f = 1 kHz
0.05 %
Adjustment Settling Time tS1 VA = 5 V ± 1 LSB error band,
VB = 0 V, measured at VW
5 μs
Power-Up Settling Time After Fuses Blown tS2 VA = 5 V ±1 LSB error band,
VB = 0 V, measured at VW
5 μs
Resistor Noise Voltage eN_WB RAB = 5 kΩ, f = 1 kHz,
code = 0x20
8 nV/√Hz
RAB = 10 kΩ, f = 1 kHz,
code = 0x20
12 nV/√Hz
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits
of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other.
6 Guaranteed by design; not subject to production test.
7 The minimum voltage requirement on the VIH is 0.7 V × VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up
to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pull-
up resistors.
8 Guaranteed by design; not subject to production test.
9 Different from operating power supply; power supply for OTP is used one time only.
10 Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only.
11 See Figure 24 for the energy plot during the OTP program.
12 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest
bandwidth. The highest R value results in the minimum overall power consumption.
14 All dynamic characteristics use VDD = 5 V.
AD5171
Rev. D | Page 5 of 24
TIMING CHARACTERISTICS: 5 kΩ, 10 kΩ, 50 kΩ, AND 100 kΩ
VDD = 3 V to 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +125°C, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ1Max Unit
INTERFACE TIMING CHARACTERISTICS (APPLY TO ALL PARTS2, 3)
SCL Clock Frequency fSCL 400 kHz
tBUF Bus Free Time Between Start and Stop t1 1.3 μs
tHD;STA Hold Time (Repeated Start) t2 After this period, the
first clock pulse is generated
0.6 μs
tLOW Low Period of SCL Clock t3 1.3 μs
tHIGH High Period of SCL Clock t4 0.6 50 μs
tSU;STA Setup Time for Start Condition t5 0.6 μs
tHD;DAT Data Hold Time t6 0.9 μs
tSU;DAT Data Setup Time t7 0.1 μs
tF Fall Time of Both SDA and SCL Signals t8 0.3 μs
tR Rise Time of Both SDA and SCL Signals t9 0.3 μs
tSU;STO Setup Time for Stop Condition t10 0.6 μs
OTP Program Time t11 400 ms
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design; not subject to production test.
3 All dynamic characteristics use VDD = 5 V.
SCL
S
DA
t
1
t
2
t
3
t
8
t
8
t
9
t
4
t
5
t
9
t
7
t
6
t
10
PPS
03437-024
Figure 3. Interface Timing Diagram
AD5171
Rev. D | Page 6 of 24
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
VA, VB, and VW to GND GND to VDD
Maximum Current
IWB, IWA Pulsed ±20 mA
IWB Continuous (RWB ≤ 1 kΩ, A Open)1
±5 mA
IWA Continuous (RWA ≤ 1 kΩ, B Open)1
±5 mA
Digital Inputs and Output Voltage to GND 0 V to VDD
Operating Temperature Range −40°C to +125°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
Thermal Resistance θJA2230°C/W
1 Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance; the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.
2 Package power dissipation = (TJ max – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5171
Rev. D | Page 7 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
W
1
V
DD 2
GND
3
SCL
4
A
8
B
7
AD0
6
SDA
5
AD5171
TOP VIEW
(Not to Scale)
03437-003
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 W Wiper Terminal W. GND ≤ VWVDD.
2 VDD Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be within
the 4.75 V and 5.25 V range and capable of driving 100 mA.
3 GND Common Ground.
4 SCL Serial Clock Input. Requires a pull-up resistor. If it is driven direct from a logic controller without the pull-up
resistor, ensure that the VIH minimum is 0.7 V × VDD.
5 SDA Serial Data Input/Output. Requires a pull-up resistor. If it is driven direct from a logic controller without a pull-up
resistor, ensure that the VIH minimum is 0.7 V × VDD.
6 AD0 I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed.
7 B Resistor Terminal B. GND ≤ VBVDD.
8 A Resistor Terminal A. GND ≤ VAVDD.
AD5171
Rev. D | Page 8 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
RHEOST
A
T MODE INL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-004
–40°C
+25°C
+125°C
V
DD
= 5V
Figure 5. R-INL vs. Code vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
RHEOST
A
T MODE DNL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-005
–40°C
+25°C
+125°C
V
DD
= 5V
Figure 6. R-DNL vs. Code vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
POTENTIOMETER MODE INL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-006
–40°C
+25°C +125°C
V
DD
= 5V
Figure 7. INL vs. Code vs. Temperature
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
0.08
0.10
POTENTIOMETER MODE DNL (LSB)
32248160 40485664
CODE (DECIMAL)
03437-007
–40°C +25°C
+125°C
V
DD
= 5V
Figure 8. DNL vs. Code vs. Temperature
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
FSE (LSB)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03437-008
V
DD
= 5V
V
DD
= 3V
Figure 9. Full-Scale Error (FSE) vs. Temperature
0
0.1
0.2
0.3
0.4
0.5
0.6
ZSE (LSB)
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03437-009
V
DD
= 5V
V
DD
= 3V
Figure 10. Zero-Scale Error (ZSE) vs. Temperature
AD5171
Rev. D | Page 9 of 24
IDD SUPPLY CURRENT (µA)
0.1
1
10
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
03437-010
VDD = 5V
VDD = 3V
Figure 11. IDD Supply Current vs. Temperature
–40
–20
20
100
140
180
60
0
80
120
160
40
RHEOST
A
T MODE TEMPCO (ppm/°C)
32248160 40485664
CODE (DECIMAL)
03437-011
Figure 12. Rheostat Mode Tempco (∆RAB/RAB)/∆T vs. Code
–5
0
5
10
15
20
25
POTENTIOMETER MODE TEMPCO (ppm/°C)
32248160 40485664
CODE (DECIMAL)
03437-012
Figure 13. Potentiometer Mode Tempco (∆VW /VW)/∆T vs. Code
100 1M1k 10k 100k 10M
FREQUENCY (Hz)
0
6
–6
–12
–18
–24
–30
–36
–54
–42
–48
GAIN (dB)
0x02
0x01
0x00
0x04
0x08
0x10
0x20
03437-013
Figure 14. Gain vs. Frequency vs. Code, RAB = 5 kΩ
100 1M1k 10k 100k
FREQUENCY (Hz)
0
6
–6
–12
–18
–24
–30
–36
–54
–42
–48
GAIN (dB)
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
03437-014
Figure 15. Gain vs. Frequency vs. Code, RAB = 10 kΩ
100 1M1k 10k 100k
FREQUENCY (Hz)
0
6
–6
–12
–18
–24
–30
–36
–54
–42
–48
GAIN (dB)
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
03437-015
Figure 16. Gain vs. Frequency vs. Code, RAB = 50 Ω
AD5171
Rev. D | Page 10 of 24
FREQUENCY (Hz)
100 1k
0
–6
6
–12
–18
–24
–30
–36
–54
–42
–48
GAIN (dB)
0x3F
0x20
0x10
0x08
0x04
0x02
0x01
0x00
1M10k 100k
03437-016
Figure 17. Gain vs. Frequency vs. Code, RAB = 100 kΩ
FREQUENCY (Hz)
80
40
100 1M1k 10k 100k
POWER SUPPLY REJECTION
R
A
TIO (dB)
60
20
0
T
A
= 25°C
CODE = 0x20
V
A
= 2.5V, V
B
= 0V
V
DD
= 5V DC ± 1.0V p-p AC
V
DD
= 3V DC ± 0.6V p-p AC
03437-017
Figure 18. Power Supply Rejection Ratio vs. Frequency
03437-018
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
fCLK
= 100kHz
10mV 500ns
V
W
= 10mV/DIV
SCL = 5V/DIV
5V
Figure 19. Digital Feedthrough vs. Time
03437-019
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
fCLK
= 400kHz
DATA 0x00 0x3F
5µs5V5V
V
W
= 5V/DIV
SCL = 5V/DIV
Figure 20. Settling Time
03437-020
V
DD
= 5.5V
V
A
= 5.5V
V
B
= GND
f
CLK
= 100kHz
DATA 0x20 0x1F
50mV 200ns5V
V
W
= 50mV/DIV
SCL = 5V/DIV
Figure 21. Midscale Glitch Energy
03437-021
5µs5V1V
OTP PROGRAMMED AT MS
V
DD
= 5.5V
V
A
= 5.5V
R
AB
= 10k
V
W
= 1V/DIV
V
DD
= 5V/DIV
Figure 22. Power-Up Settling Time After Fuses Blown
AD5171
Rev. D | Page 11 of 24
THEORETIC
A
L I
WB_MAX
(mA)
0.01
1
0.1
10
32248160 40485664
CODE (DECIMAL)
03437-0-022
V
A
= V
B
= OPEN
T
A
= 25°C
R
AB
= 100k
R
AB
= 50k
R
AB
= 10k
R
AB
= 5k
03437-023
CH1 20.0mAM 200ns A CH1 32.4mA
1
T 588.000ns
CH1 MAX
103mA
CH1 MIN
–1.98mA
Figure 24. OTP Program Energy Plot for Single Fuse
Figure 23. Theoretical IWB_MAX vs. Code
AD5171
Rev. D | Page 12 of 24
THEORY OF OPERATION
03437-025
SDA
SCL A
W
B
COMPARATOR
MUX DECODER
FUSES
EN
FUSE
REG.
DAC
REG.
I
2
C INTERFACE
ONE-TIME
PROGRAM/TEST
CONTROL BLOCK
Figure 25. Detailed Functional Block Diagram
The AD5171 allows unlimited 6-bit adjustments, except for the
one-time programmable, set-and-forget resistance setting. OTP
technology is a proven, cost-effective alternative over EEMEM
in one-time memory programming applications. The AD5171
employs fuse link technology to achieve the memory retention
of the resistance setting function. It has six data fuses that control
the address decoder for programming the RDAC, one user
mode test fuse for checking setup error, and one programming
lock fuse for disabling any further programming once the data
fuses are blown.
ONE-TIME PROGRAMMING (OTP)
Prior to OTP activation, the AD5171 presets to midscale during
initial power-on. After the wiper is set at the desired position,
the resistance can be permanently set by programming the T bit
high along with the proper coding (see Table 8 and Table 9) and
one-time VDD_OTP. The fuse link technology of the AD517x
family of digital potentiometers requires VDD_OTP between 4.75 V
and 5.25 V to blow the fuses to achieve a given nonvolatile
setting. On the other hand, VDD can be 2.7 V to 5.5 V during
operation. As a result, a system supply that is lower than 4.75 V
requires external supply for OTP. In addition, the user is only
allowed one attempt in blowing the fuses. If the user fails to
blow the fuses at the first attempt, the fuse structures may change
so that they may never be blown regardless of the energy applied
at subsequent events. For details, see the Power Supply
Considerations section.
The device control circuit has two validation bits, E1 and E0,
that can be read back to check the programming status (see
Table 5). Users should always read back the validation bits to
ensure that the fuses are properly blown. After the fuses are
blown, all fuse latches are enabled upon subsequent power-on;
therefore, the output corresponds to the stored setting.
Table 5. Validation Status
E1 E0 Status
0 0 Ready for programming.
0 1 Test fuse not blown successfully. For factory setup
checking purpose only. Users should not see these
combinations.
1 0 Fatal error. Some fuses are not blown. Do not retry.
Discard the unit.
1 1 Successful. No further programming is possible.
This section discusses the fuse operation in detail. When the
OTP T bit is set, the internal clock is enabled. The program then
attempts to blow a test fuse. The operation stops if the test fuse
is not properly blown. The validation bits, E1 and E0, show 01.
This status is intended for factory setup checking purposes
only; users should not see this status. If the test fuse is properly
blown, the data fuses can be programmed. The six data fuses
are programmed in six clock cycles. The output of the fuses is
compared with the code stored in the RDAC register. If they do
not match, E1 and E0 of 10 are issued as fatal errors and the
operation stops. Users should never try blowing the fuses more
than once because the fuse structure may have changed prohibiting
further programming. As a result, the unit must be discarded.
This error status can also occur if the OTP supply voltage goes
above or drops below the VDD_OTP requirement, the OTP supply
current is limited, or both the voltage and current ramp times
are slow. If the output and stored code match, the programming
lock fuse is blown so that no further programming is possible.
In the meantime, E1 and E0 issue 11, indicating the lock fuse is
properly blown. All the fuse latches are enabled at power-on;
therefore, from this point on, the output corresponds to the
stored setting. Figure 25 shows a detailed functional block
diagram.
AD5171
Rev. D | Page 13 of 24
VARIABLE RESISTANCE AND VOLTAGE FOR
RHEOSTAT MODE
If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with
Terminal W. This operation is called rheostat mode (see Figure 26).
A
W
B
A
W
B
A
W
B
0
3437-050
Figure 26. Rheostat Mode Configuration
The nominal resistance (RAB) of the RDAC has 64 contact points
accessed by the wiper terminal, plus Terminal B contact if RWB is
considered. The 6-bit data in the RDAC latch is decoded to
select one of the 64 settings. Assuming that a 10 kΩ part is used,
the first connection of the wiper starts at Terminal B for Data 0x00.
Such a connection yields a minimum of 60 Ω resistance between
Terminal W and Ter minal B due to th e 60 Ω wip er contac t
resistance. The second connection is the first tap point, which
corresponds to 219 Ω (RWB = 1 × RAB/63 + RW) for Data 0x01,
and so on. Each LSB data value increase moves the wiper up
the resistor ladder until the last tap point is reached at 10,060 Ω
(63 × RAB/63 + RW). Figure 27 shows a simplified diagram of the
equivalent RDAC circuit. The general equation determining RWB is
W
AB
WB RR
D
DR +×=
63
)( (1)
where:
D is the decimal equivalent of the 6-bit binary code.
RAB is the end-to-end resistance.
RW is the wiper resistance contributed by the on-resistance of
the internal switch.
Table 6. RWB vs. Codes: RAB = 10 kΩ; Terminal A Open
D (Dec) RWB (Ω) Output State
63 10060 Full-scale (RAB + RW)
32 5139 Midscale
1 219 1 LSB
0 60 Zero-scale (wiper contact resistance)
Because a finite wiper resistance of 60 Ω is present in the zero-
scale condition, care should be taken to limit the current flow
between Terminal W and Terminal B in t his st ate to a maximu m
pulse current 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper (Terminal W) and Terminal A also
produces a complementary resistance, RWA . When these terminals
are used, Terminal B can be opened or shorted to Terminal W.
Setting the resistance value for RWA starts at a maximum value
of resistance and decreases as the data loaded in the latch
increases in value. The general equation for this operation is
W
ABWA RR
D
DR +×
=
63
63
)( (2)
Table 7. RWA vs. Codes: RAB = 10 kΩ; Terminal B Open
D (Dec) RWA (Ω) Output State
63 60 Full-scale
32 4980 Midscale
1 9901
1 LSB
0 10060 Zero-scale
The typical distribution of the resistance tolerance from device
to device is process-lot dependent; it is possible to have ±30%
tolerance.
R
S
R
S
R
S
A
W
B
D5
D4
D3
D2
D1
D0
RDAC
LATCH
AND
DECODER
03437-026
Figure 27. AD5171 Equivalent RDAC Circuit
VARIABLE RESISTANCE AND VOLTAGE FOR
POTENTIOMETER MODE
If all three terminals are used, the operation is called the
potentiometer mode. The most common configuration is the
voltage divider operation (see Figure 28).
A
W
B
V
I
V
O
0
3437-051
Figure 28. Potentiometer Mode Configuration
AD5171
Rev. D | Page 14 of 24
Ignoring the effect of the wiper resistance, the transfer function
is simply
A
WV
D
DV
63
)( = (3)
A more accurate calculation, which includes the wiper
resistance effect, yields
A
AB
W
AB
WV
RR
RR
D
DV
2
63
)( +
+
= (4)
Unlike in rheostat mode where the absolute tolerance is high,
potentiometer mode yields an almost ratiometric function of
D/63 with a relatively small error contributed by the RW terms;
thus, the tolerance effect is almost cancelled. Although the thin
film step resistor (RS) and CMOS switches resistance (RW) have
very different temperature coefficients, the ratiometric adjustment
also reduces the overall temperature coefficient effect to 5 ppm/°C,
except at low value codes where RW dominates.
Potentiometer mode includes other operations such as op amp
input, feedback resistor networks, and voltage scaling applications.
Terminal A, Terminal W, and Terminal B can, in fact, be input
or output terminals provided that |VAB|, |VWA |, and |VWB| do not
exceed VDD to GND.
POWER SUPPLY CONSIDERATIONS
To minimize the package pin count, both the OTP and normal
operating voltage supplies share the same VDD terminal of the
AD5171. The AD5171 employs fuse link technology that requires
4.75 V to 5.25 V for blowing the internal fuses to achieve a
given setting, but normal VDD can be anywhere between 2.7 V
and 5.5 V after the fuse programming process. As a result, dual
voltage supplies and isolation are needed if system VDD is lower
than the required VDD_OTP. The fuse programming supply (either
an on-board regulator or rack-mount power supply) must be
rated at 4.75 V to 5.25 V and able to provide a 100 mA current
for 400 ms for successful one-time programming. Once fuse
programming is complete, the VDD_OTP supply must be removed
to allow normal operation at 2.7 V to 5.5 V; the device then
consumes current in the μA range.
03437-052
V
DD
2
.7
V
5V
P1
R1
10k
P2
APPLY FOR O
T
P ONLY
AD5171
C2
0.1µF
C1
10µF
P1 = P2 = FDV302P, NDS0610
Figure 29. 5 V OTP Supply Isolated from the 2.7 V Normal Operating Supply;
the VDD_OTP supply must be removed once OTP is complete.
When operating at 2.7 V, use of the bidirectional low threshold
P-Ch MOSFETs is recommended for the isolation of the supply.
As shown in Figure 29, this assumes that the 2.7 V system
voltage is applied first, and the P1 and P2 gates are pulled to
ground, thus turning on P1 and, subsequently, P2. As a result,
VDD of the AD5171 approaches 2.7 V. When the AD5171 setting
is found, the factory tester applies the VDD_OTP to both the VDD
and the MOSFETs gates, thus turning off P1 and P2. The OTP
command should be executed at this time to program the
AD5171 while the 2.7 V source is protected. Once the fuse
programming is complete, the tester withdraws the VDD_OTP and
the setting of the AD5171 is permanently fixed.
The AD5171 achieves the OTP function through blowing
internal fuses. Users should always apply the 4.75 V to
5.25 V one-time program voltage requirement at the first
fuse programming attempt. Failure to comply with this
requirement may lead to a change in the fuse structures,
rendering programming inoperable.
Care should be taken when SCL and SDA are driven from a low
voltage logic controller. Users must ensure that the logic high
level is between 0.7 V × VDD and VDD. Refer to the Level Shifting
for Different Voltage Operation section.
Poor PCB layout introduces parasitics that may affect the fuse
programming. Therefore, it is recommended that a 10 μF
tantalum capacitor be added in parallel with a 1 nF ceramic
capacitor as close as possible to the VDD pin. The type and value
chosen for both capacitors are important. This combination of
capacitor values provides both a fast response and larger supply
current handling with minimum supply droop during transients.
As a result, these capacitors increase the OTP programming
success by not inhibiting the proper energy needed to blow the
internal fuses. Additionally, C1 minimizes transient disturbance
and low frequency ripple, while C2 reduces high frequency
noise during normal operation.
ESD PROTECTION
Digital inputs SDA and SCL are protected with a series input
resistor and parallel Zener ESD structures (see Figure 30).
LOGIC
340
GND
03437-027
Figure 30. ESD Protection of Digital Pins
AD5171
Rev. D | Page 15 of 24
TERMINAL VOLTAGE OPERATING RANGE POWER-UP/POWER-DOWN SEQUENCES
There are also ESD protection diodes between VDD and the
RDAC terminals; therefore, the VDD of the AD5171 defines their
voltage boundary conditions (see Figure 31). Supply signals
present on Terminal A, Terminal B, and Terminal W that
exceed VDD are clamped by the internal forward-biased diodes
and should be avoided.
Similarly, because of the ESD protection diodes, it is important
to power VDD first before applying any voltages to Terminal A,
Terminal B, and Ter mina l W. Other wi se, t he di ode is for ward-
biased such that VDD is powered unintentionally and can affect
the remainder of the users’ circuits. The ideal power-up sequence is
the following order: GND, VDD, digital inputs, and VA/VB/VW.
The order of powering VA, VB, VW, and the digital inputs is not
important as long as they are powered after VDD. Similarly, VDD
should be powered down last.
GND
A
W
B
V
DD
03437-029
Figure 31. Maximum Terminal Voltages Set by VDD
AD5171
Rev. D | Page 16 of 24
CONTROLLING THE AD5171
There are two ways of controlling the AD5171. Users can either
program the devices with computer software or employ external
I2C controllers.
SOFTWARE PROGRAMMING
Due to the advantage of the one-time programmable feature,
users may consider programming the device in the factory
before shipping it to the end users. Analog Devices offers device
programming software that can be implemented in the factory
on PCs running Windows 95 to Windows XP platforms. As a
result, external controllers are not required, which significantly
reduces development time.
The program is an executable file that does not require the user
to know any programming languages or programming skills. It
is easy to set up and use. Figure 32 shows the software interface.
The software can be downloaded from the AD5171 product page.
03437-032
Figure 32. Software Interface
Write
The AD5171 starts at midscale after power-up prior to the OTP
programming. To increment or decrement the resistance, move
the scrollbar on the left. To write any specific values, use the bit
pattern control in the upper screen and click Run. The format
of writing data to the device is shown in Table 8. Once the
desired setting is found, click Program Permanent to blow the
internal fuse links for permanent setting. The user can also set
the programming bit pattern in the upper screen and click Run
to achieve the same result.
Read
To read the validation bits and data from the device, click Read.
The user may also set the bit pattern in the upper screen and
click Run. The format of reading data out from the device is
shown in Table 9.
DEVICE PROGRAMMING
To apply the device programming software in the factory, users
need to modify a parallel port cable and configure Pin 2, Pin 3,
Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND,
respectively, for the control signals (see Figure 33). In addition,
lay out the PCB of the AD5171 with SCL and SDA pads, as
shown in Figure 34, such that pogo pins can be inserted for the
factory programming.
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
SCL
R3
100
R2
100
R1
100
SDA
READ
WRITE
0
3437-033
Figure 33. Parallel Port Connection: Pin 2 = SDA_write, Pin 3 = SCL,
Pin 15 = SDA_read, and Pin 25 = DGND
W
V
DD
GND
SCL
A
B
AD0
SDA
04104-034
Figure 34. Recommended AD5171 PCB Layout
Table 8. SDA Write Mode Bit Format
S 0 1 0 1 1 0 AD0 0 A T X X X X X X X A X X D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 9. SDA Read Mode Bit Format
S 0 1 0 1 1 0 AD0 1 A E1 E0 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
AD5171
Rev. D | Page 17 of 24
Table 10. SDA Bits Definitions and Descriptions
Bit Description
S Start Condition.
P Stop Condition.
A Acknowledge.
AD0 I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed.
X Don’t Care.
T OTP Programming Bit. Logic 1 programs the wiper position permanently.
D5, D4, D3, D2, D1, D0 Data Bits.
E1, E0 OTP Validation Bits:
0, 0 = Ready to Program.
0, 1 = Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these
combinations.
1, 0 = Fatal Error. Do not retry. Discard the unit.
1, 1 = Programmed Successfully. No further adjustments are possible.
I2C CONTROLLER PROGRAMMING
Write Bit Patterns
SDA
SCL
0
1
10110AD0 R/W 0XXXXXXXXXD5
D4 D3 D2 D1 D0
91 91 9
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
S
TART BY
MASTER
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
03437-035
Figure 35. Writing to the RDAC Register
SDA
SCL
0
1
10110AD0 R/W 1XXXXXXXXX D5D4D3D2D1D0
91 91 9
STOP BY
MASTER
FRAME 1
DATA BYTE
FRAME 2
INSTRUCTION BYTE
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
ACK. BY
AD5171
ACK. BY
AD5171
ACK. BY
AD5171
03437-036
Figure 36. Activating One-Time Programming
Read Bit Pattern
SDA
SCL
0
1
10110AD0 E1 E0 D5 D4 D3 D2 D1 D0
91 9
R/W
STOP BY
MASTER
FRAME 2
RDAC REGISTER
FRAME 1
SLAVE ADDRESS BYTE
START BY
MASTER
NO ACK. BY
MASTER
ACK. BY
AD5171
03437-037
Figure 37. Reading Data from RDAC Register
I2C-COMPATIBLE 2-WIRE SERIAL BUS
For users who prefer to use external controllers, the AD5171
can be controlled via an I2C-compatible serial bus; the part is
connected to this bus as a slave device. The following section
describes how the 2-wire I2C serial bus protocol operates (see
Figure 35, Figure 36, and Figure 37).
The master initiates data transfer by establishing a start condition,
which is when SDA goes from high to low while SCL is high
(see Figure 35 and Figure 36). The following byte is the slave
address byte, which consists of the 6 MSBs as a slave address
defined as 010110. The next bit is AD0, which is an I2C device
address bit. Depending on the states of their AD0 bits, two
AD5171s can be addressed on the same bus (see Figure 38). The
last LSB is the R/W bit, which determines whether data is read
from, or written to, the slave device.
The slave address corresponding to the transmitted address bit
responds by pulling the SDA line low during the 9th clock pulse
(this is termed the acknowledge bit). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to, or read from, its serial register.
The write operation contains one instruction byte more than
the read operation. The instruction byte in the write mode
follows the slave address byte. The MSB of the instruction byte
labeled T is the one-time programming bit. After acknowledging
AD5171
Rev. D | Page 18 of 24
the instruction byte, the last byte in the write mode is the data
byte. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
The transitions on the SDA line must occur during the low
period of SCL and remain stable during the high period of SCL
(see Figure 35).
In read mode, the data byte follows immediately after the
acknowledgment of the slave address byte. Data is transmitted over
the serial bus in sequences of nine clock pulses (note the slight
difference from the write mode; there are eight data bits followed
by a no acknowledge bit). Similarly, the transitions on the SDA
line must occur during the low period of SCL and remain stable
during the high period of SCL (see Figure 37).
When all data bits are read or written, a stop condition is
established by the master. A stop condition is defined as a low-
to-high transition on the SDA line while SCL is high. In the
write mode, the master pulls the SDA line high during the 10th
clock pulse to establish a stop condition (see Figure 35 and
Figure 36). In the read mode, the master issues a no acknowledge
for the 9th clock pulse, that is, the SDA line remains high. The
master then brings the SDA line low before the 10th clock pulse,
which goes high to establish a stop condition (see Figure 37).
A repeated write function gives the user flexibility to update the
RDAC output a number of times, except after permanent
programming, addressing, and instructing the part only once.
During the write cycle, each data byte updates the RDAC output.
For example, after the RDAC has acknowledged its slave address
and instruction bytes, the RDAC output updates after these two
bytes. If another byte is written to the RDAC while it is still
addressed to a specific slave device with the same instruction,
this byte updates the output of the selected slave device. If
different instructions are needed, the write mode has to be
started with a new slave address, instruction, and data bytes.
Similarly, a repeated read function of the RDAC is also allowed.
CONTROLLING TWO DEVICES ON ONE BUS
Figure 38 shows two AD5171 devices on the same serial bus.
Each has a different slave address because the state of each AD0
pin is different, which allows each device to be independently
operated. The master device output bus line drivers are open-
drain pull-downs in a fully I2C-compatible interface.
MASTER
SDA SCL
AD0
AD5171
SDA SCL
AD0
AD5171
SDA
SCL
5
V
Rp Rp
5V
03437-038
Figure 38. Two AD5171 Devices on One Bus
AD5171
Rev. D | Page 19 of 24
APPLICATIONS INFORMATION
DAC
It is common to buffer the output of the digital potentiometer as
a DAC unless the load is much larger than RWB. The buffer can
impede conversion and deliver higher current, if needed.
GND
V
IN
V
OUT
1
5
V
2
3
V
O
AD8601
5V
A
W
B
U1
AD1582
A1
AD5171
U2
03437-039
Figure 39. Programmable Voltage Reference (DAC)
GAIN CONTROL COMPENSATION
The digital potentiometers are commonly used in gain
controls or sensor transimpedance amplifier signal conditioning
applications (see Figure 40). To avoid gain peaking, or in worst-
case oscillation due to step response, a compensation capacitor
is needed. In general, C2 in the range of a few picofarads to a
few tenths of a picofarad is adequate for the compensation.
U1
C2
4.7pF
A
B
W
R2 100k
V
O
V
I
R1
47k
0
3437-040
Figure 40. Typical Noninverting Gain Amplifier
PROGRAMMABLE VOLTAGE SOURCE WITH
BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 41).
+V
W
SIGNAL
C
C
R
BIAS
LD
V
IN
A
B
V
OUT
U1
A
D5171
U3 2N7002
AD8601
U2
–V
I
L
03437-041
Figure 41. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the VOUT
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the N‒Ch
FET N1. N1 power handling must be adequate to dissipate
(VI − VO) × IL power. This circuit can source a maximum of
100 mA with a 5 V supply. For precision applications, a voltage
reference, such as the ADR421, ADR03, or ADR370, can be
applied at Terminal A of the digital potentiometer.
LEVEL SHIFTING FOR DIFFERENT VOLTAGE
OPERATION
If the SCL and SDA signals come from a low voltage logic
controller and are below the minimum VIH level (0.7 V × VDD),
level shift the signals for read/write communications between
the AD5171 and the controller. Figure 42 shows one of the
implementations. For example, when SDA1 is at 2.5 V, M1 turns
off, and SDA2 becomes 5 V. When SDA1 is at 0 V, M1 turns on,
and SDA2 approaches 0 V. As a result, proper level shifting is
established. M1 and M2 should be low threshold N-Ch power
MOSFETs, such as FDV301N.
2.5V
CONTROLLER
2.7V–5.5V
AD5171
Rp Rp Rp Rp
V
DD1 = 2.5
V
V
DD2 = 5
V
G
G
SD
M1 SD
M2
SDA1
SCL1
SDA2
SCL2
03437-042
Figure 42. Level Shifting for Different Voltage Operation
RESISTANCE SCALING
The AD5171 offers 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ nominal
resistances. For users who need to optimize the resolution with
an arbitrary full range resistance, the following techniques can
be used. By paralleling a discrete resistor, a proportionately lower
voltage appears at Ter mina l A to Ter mi na l B, w hi ch i s ap pl icabl e
only to the voltage divider mode (see Figure 43).
This translates into a finer degree of precision because the step
size at Terminal W is smaller. The voltage can be found as
DD
AB
AB
WV
D
R2RR3
R2R
DV ××
+
=
64||
)||(
)( (5)
R1
R2
B
A
V
DD
R3
W
03437-043
Figure 43. Lowering the Nominal Resistance
AD5171
Rev. D | Page 20 of 24
For log taper adjustment, such as volume control, Figure 44
shows another way of resistance scaling. In this circuit, the
smaller the R2 with respect to RAB, the more it behaves like the
pseudo log taper characteristic. The wiper voltage is simply
I
WB
WA
WB
WV
2RRR
2RR
DV ×
+
=
||
)||(
)( (6)
V
I
R1
B
A
R2
VO
W
0
3437-044
Figure 44. Resistor Scaling with Log Adjustment Characteristics
RESOLUTION ENHANCEMENT
The resolution can be doubled in the potentiometer mode of
operation by using three digital potentiometers. Borrowed from
the Analog Devices patented RDAC segmentation technique,
users can configure three AD5171s to double the resolution (see
Figure 45). First, U3 must be parallel with a discrete resistor, RP,
which is chosen to be equal to a step resistance (RP = RAB/64).
Adjusting U1 and U2 together forms the coarse 6-bit adjustment,
and adjusting U3 alone forms the finer 6-bit adjustment. As a
result, the effective resolution becomes 12-bit.
U1
A1
B1
W1
U2
A2
B2
W3
W2
U3
A3
B3
R
P
COARSE
ADJUSTMENT
FINE
ADJUSTMENT
03437-045
Figure 45. Doubling the Resolution
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the digital potentiometers.
Configured as a potentiometer divider, the –3 dB bandwidth of
the AD5171 (5 kΩ resistor) measures 1.5 MHz at half scale.
Figure 14 to Figure 17 provide the large signal BODE plot
characteristics of the four available resistor versions: 5 kΩ,
10 kΩ, 50 kΩ, and 100 kΩ. A parasitic simulation model is
shown in Figure 46. Listing 1 provides a macro model net list
for the 10 kΩ device.
55pF
C
A
25pF
C
B
25pF
AB
RDAC
10k
W
C
W
03437-046
Figure 46. Circuit Simulation Model for RDAC = 10 kΩ
Listing 1. Macro Model Net List for RDAC
.PARAM D=64, RDAC=10E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/64)*RDAC+60}
CW W 0 55E-12
RWB W B {D/64*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT
AD5171
Rev. D | Page 21 of 24
EVALUATION BOARD
8
7
6
5
4
3
2
1
J1
W
VDD
GND
SCL
A
B
AD0
SDA
OUT1
OUT1
+IN1
V+
V–
–IN2
+IN2
OUT2
–IN1
JP8
JP7
JP4
JP6
C8
0.1µF C9
10µF
VEE
U3A
CP4
CP2
JP5
JP3
C6
0.1µF
C7
10µF
1
2
3
4
8
5
6
7
–IN1
CP3
CP1
VIN
1
AD5170 AD5171/AD5273
AGND
VREF
ADR03
2
3
5
4
C1
10µF
C2
0.1µF
R1
10k
R2
10k
SCL
SDA
C3
0.1µF
U1
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
U2
C4
0.1µF
U4
TEMP
GND
VIN
TRIM
VOUT C5
0.1µF
JP1
JP2
A
W
BCP6 CP7
U3B
VDD
VDD
W
VDD
GND
SCL
A
B
AD0
SDA
VDD
VDD
VCC
CP5
03437-047
Figure 47. Evaluation Board Schematic
The AD5171 evaluation board comes with a dual op amp
AD822 and a 2.5 V reference ADR03. Users can configure many
building block circuits with minimal components needed.
Figure 48 shows one of the examples. There is space available on
the board where users can build additional circuits for further
evaluations as shown in Figure 49.
A
B
WV
O
A
B
W
CP2
U2
JP1
JP2 JP4
JP3
JP7
4
U3A
1
OUT1
V+
V–
AD822
2
311
03437-048
V
REF
V
REF
V
DD
Figure 48. Programmable Voltage Reference
03437-049
Figure 49. Evaluation Board
AD5171
Rev. D | Page 22 of 24
OUTLINE DIMENSIONS
13
56
2
8
4
7
2.90 BSC
1.60 BSC
1.95
BSC
0.65 BSC
0.38
0.22
0.15 MAX
1.30
1.15
0.90
SEATING
PLANE
1.45 MAX 0.22
0.08 0.60
0.45
0.30
2.80 BSC
PIN 1
INDICATOR
COMPLIANT TO JEDEC STANDARDS MO-178-B A
Figure 50. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1RAB (kΩ) Temperature Range Package Description Package Option Ordering Quantity Branding
AD5171BRJ5-R2 5 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D12
AD5171BRJ5-RL7 5 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D12
AD5171BRJZ5-R225 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D12#
AD5171BRJZ5-R72
5 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D12#
AD5171BRJ10-R2 10 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D13
AD5171BRJ10-RL7 10 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D13
AD5171BRJZ10-R22
10 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D13#
AD5171BRJZ10-R72
10 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D13#
AD5171BRJ50-R2 50 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D14
AD5171BRJ50-RL7 50 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D14
AD5171BRJZ50-R22
50 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D14#
AD5171BRJZ50-R72
50 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D14#
AD5171BRJ100-R2 100 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D15
AD5171BRJ100-RL7 100 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D15
AD5171BRJZ100-R22
100 −40°C to +125°C 8-Lead SOT-23 RJ-8 250 D15#
AD5171BRJZ100-R72
100 −40°C to +125°C 8-Lead SOT-23 RJ-8 3000 D15#
AD5171EVAL310 Evaluation Board 1
1 Parts have a YWW or #YWW marking on the bottom of the package. Y shows the year that the part was made, for example, Y = 5 for 2005. WW shows the work week
that the part was made.
2 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
3 The evaluation board is shipped with three pieces of 10 kΩ parts. Users should order extra samples or different resistance options if needed.
AD5171
Rev. D | Page 23 of 24
NOTES
AD5171
Rev. D | Page 24 of 24
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2004–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03437-0-7/08(D)