64-Position OTP Digital Potentiometer AD5171 FUNCTIONAL BLOCK DIAGRAM 64 position One-time programmable (OTP) set-and-forget resistance setting--low cost alternative over EEMEM Unlimited adjustments prior to OTP activation 5 k, 10 k, 50 k, 100 k end-to-end resistance Low temperature coefficient: 5 ppm/C in potentiometer mode Low temperature coefficient: 35 ppm/C in rheostat mode Compact standard 8-lead SOT-23 package Low power: IDD = 10 A maximum Fast settling time: tS = 5 s typical in power-up I2C-compatible digital interface Computer software replaces microcontroller in factory programming applications Full read/write of wiper register Extra I2C device address pin Low operating voltage: 2.7 V to 5.5 V OTP validation check function Automotive temperature range: -40C to +125C SCL SDA A I2C INTERFACE AND CONTROL LOGIC W AD0 B WIPER REGISTER VDD GND FUSE LINK AD5171 03437-001 FEATURES Figure 1. 8 AD5171 A B TOP VIEW GND 3 (Not to Scale) 6 AD0 SCL 4 7 5 SDA 03437-002 W 1 VDD 2 Figure 2. Pin Configuration APPLICATIONS System calibrations Electronics level settings Mechanical trimmers and potentiometer replacements Automotive electronics adjustments Gain control and offset adjustments Transducer circuit adjustments Programmable filters up to 1.5 MHz BW 1 GENERAL DESCRIPTION The AD5171 is a 64-position, one-time programmable (OTP) digital potentiometer 2 that uses fuse link technology to achieve the memory retention of the resistance setting function. OTP is a cost-effective alternative over the EEMEM approach for users who do not need to reprogram new memory settings in the digital potentiometer. This device performs the same electronic adjustment function as most mechanical trimmers and variable resistors. The AD5171 is programmed using a 2-wire, I2C(R)compatible digital control. It allows unlimited adjustments before permanently setting the resistance value. During the OTP activation, a permanent fuse blown command is sent after the final value is determined, freezing the wiper position at a given setting (analogous to placing epoxy on a mechanical trimmer). When this permanent setting is achieved, the value does not change regardless of supply variations or environmental stresses under normal operating conditions. To verify the success of permanent programming, Analog Devices, Inc., patterned the OTP validation such that the fuse status can be discerned from two validation bits in read mode. For applications that program the AD5171 in factories, Analog Devices offers device programming software that operates across Windows(R) 95 to XP platforms, including Windows NT. This software application effectively replaces the need for external I2C controllers or host processors and, therefore, significantly reduces the development time of the users. An AD5171 evaluation kit includes the software, connector, and cable that can be converted for factory programming applications. The AD5171 is available in a compact 8-lead SOT-23 package. All parts are guaranteed to operate over the automotive temperature range of -40C to +125C. Besides its unique OTP feature, the AD5171 lends itself well to other general-purpose digital potentiometer applications due to its temperature performance, small form factor, and low cost. 1 2 Applies to 5 k parts only. The terms digital potentiometer and RDAC are used interchangeably. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2004-2008 Analog Devices, Inc. All rights reserved. AD5171 TABLE OF CONTENTS Features .............................................................................................. 1 Power-Up/Power-Down Sequences ......................................... 15 Applications ....................................................................................... 1 Controlling the AD5171 ................................................................ 16 General Description ......................................................................... 1 Software Programming ............................................................. 16 Functional Block Diagram .............................................................. 1 Device Programming ................................................................. 16 Revision History ............................................................................... 2 I2C Controller Programming .................................................... 17 Specifications..................................................................................... 3 I2C-Compatible 2-Wire Serial Bus ........................................... 17 Electrical Characteristics: 5 k, 10 k, 50 k, and 100 k .. 3 Controlling Two Devices on One Bus ..................................... 18 Timing Characteristics: 5 k, 10 k, 50 k, and 100 k ...... 5 Applications Information .............................................................. 19 Absolute Maximum Ratings............................................................ 6 DAC.............................................................................................. 19 ESD Caution .................................................................................. 6 Gain Control Compensation .................................................... 19 Pin Configuration and Function Descriptions ............................. 7 Programmable Voltage Source with Boosted Output ........... 19 Typical Performance Characteristics ............................................. 8 Level Shifting for Different Voltage Operation ...................... 19 Theory of Operation ...................................................................... 12 Resistance Scaling ...................................................................... 19 One-Time Programming (OTP) .............................................. 12 Resolution Enhancement .......................................................... 20 Variable Resistance and Voltage for Rheostat Mode ............. 13 RDAC Circuit Simulation Model ............................................. 20 Variable Resistance and Voltage for Potentiometer Mode .... 13 Evaluation Board ............................................................................ 21 Power Supply Considerations ................................................... 14 Outline Dimensions ....................................................................... 22 ESD Protection ........................................................................... 14 Ordering Guide .......................................................................... 22 Terminal Voltage Operating Range.......................................... 15 REVISION HISTORY 7/08--Rev. C to Rev. D Changes to Power Supplies Parameter in Table 1.........................3 Updated Fuse Blow Condition to 400 ms Throughout ...............5 1/08--Rev. B to Rev. C Updated Format .................................................................. Universal Deleted Note 1; Renumbered Sequentially ................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 5 Changes to Table 3 ............................................................................ 6 Changes to Table 4 ............................................................................ 7 Changes to Figure 13 to Figure 16 .................................................. 9 Changes to Figure 17 and Figure 18 ............................................. 10 Inserted Figure 24 ........................................................................... 11 Changes to One-Time Programming (OTP) Section and Power Supply Considerations Section ..................................................... 12 Deleted Figure 25 and Figure 26 ................................................... 13 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 1/05--Rev. A to Rev. B Change to Features ............................................................................1 Changes to Electrical Characteristics .............................................3 Change to Table 3 ..............................................................................6 Changes to Power Supply Considerations Section .................... 13 Changes to Level Shifting for Different Voltage Operation Section.............................................................................................. 19 Added Note to Ordering Guide .................................................... 22 11/04--Rev. 0 to Rev. A Changes to Specifications .................................................................3 Changes to Table 3.............................................................................7 Changes to One-Time Programming Section ............................ 11 Changes to Power Supply Consideration Section ...................... 11 Changes to Figure 26 and Figure 27............................................. 12 1/04--Revision 0: Initial Version Rev. D | Page 2 of 24 AD5171 SPECIFICATIONS ELECTRICAL CHARACTERISTICS: 5 k, 10 k, 50 k, AND 100 k VDD = 3 V to 5 V 10%, VA = VDD, VB = 0 V, -40C < TA < +125C, unless otherwise noted. Table 1. Parameter DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity 2 2 Resistor Integral Nonlinearity Nominal Resistor Tolerance 3 Resistance Temperature Coefficient Wiper Resistance DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (SPECIFICATIONS APPLY TO ALL RDACs) Resolution Differential Nonlinearity 4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range 5 Capacitance A, B 6 Capacitance W6 Common-Mode Leakage DIGITAL INPUTS Input Logic High (SDA and SCL) 7 Input Logic Low (SDA and SCL)7 Input Logic High (AD0) Input Logic Low (AD0) Input Current Input Capacitance 8 DIGITAL OUTPUTS Output Logic Low (SDA) Three-State Leakage Current (SDA) Output Capacitance8 POWER SUPPLIES Power Supply Range OTP Power Supply7, 9 Supply Current OTP Supply Current7, 10, 11 Power Dissipation 12 Power Supply Sensitivity Symbol Conditions Min Typ 1 Max Unit R-DNL RWB, VA = no connect, RAB = 10 k, 50 k, and 100 k RWB, VA = no connect, RAB = 5 k RWB, VA = no connect, RAB = 10 k, 50 k, and 100 k RWB, VA = no connect, RAB = 5 k -0.5 0.1 +0.5 LSB -1 -1.5 0.25 0.35 +1 +1.5 LSB LSB -1.5 -30 0.5 +1.5 +30 LSB % ppm/C R-INL RAB/RAB (RAB/RAB)/T RW N DNL INL (VW/VW)/T VWFSE VWFSE VWZSE VA, VB, VW CA, CB CW ICM VIH VIL VIH VIL IIL CIL VOL IOZ COZ VDD VDD_OTP IDD IDD_OTP PDISS PSSR 35 60 VDD = 5 V -0.5 -1 Code = 0x20 Code = 0x3F, RAB = 10 k, 50 k, and 100 k Code = 0x3F, RAB = 5 k Code = 0x00, RAB =10 k, 50 k, and 100 k Code = 0x00, RAB = 5 k VDD = 3 V VDD = 3 V VIN = 0 V or 5 V 0 Bits LSB LSB ppm/C LSB 0 1 LSB LSB 2 LSB VDD 25 V pF 55 pF 1 nA -1 0.1 0.2 5 -0.5 -1.5 0 0.5 0 With respect to GND f = 1 MHz, measured to GND, code = 0x20 f = 1 MHz, measured to GND, code = 0x20 VA = VB = VDD/2 115 0.7 VDD -0.5 3.0 0 6 +0.5 +1 VDD + 0.5 +0.3 VDD VDD 1.0 1 V V V V A pF 0.4 1 V A pF 5.5 5.25 10 V V A mA mW %/% 3 IOL = 6 mA VIN = 0 V or 5 V 3 TA = 25C VIH = 5 V or VIL = 0 V VDD_OTP = 5 V, TA = 25C VIH = 5 V or VIL = 0 V, VDD = 5 V 2.7 4.75 -0.025 Rev. D | Page 3 of 24 5 4 100 0.02 +0.001 0.055 +0.025 AD5171 Parameter DYNAMIC CHARACTERISTICS8, 13, 14 -3 dB Bandwidth Symbol Conditions Total Harmonic Distortion BW_5k BW_10k BW_50k BW_100k THD Adjustment Settling Time tS1 Power-Up Settling Time After Fuses Blown tS2 Resistor Noise Voltage eN_WB RAB = 5 k, code = 0x20 RAB = 10 k, code = 0x20 RAB = 50 k, code = 0x20 RAB = 100 k, code = 0x20 VA = 1 V rms, RAB = 10 k, VB = 0 V dc, f = 1 kHz VA = 5 V 1 LSB error band, VB = 0 V, measured at VW VA = 5 V 1 LSB error band, VB = 0 V, measured at VW RAB = 5 k, f = 1 kHz, code = 0x20 RAB = 10 k, f = 1 kHz, code = 0x20 1 Min Typ 1 Max Unit 1500 600 110 60 0.05 kHz kHz kHz kHz % 5 s 5 s 8 nV/Hz 12 nV/Hz Typical specifications represent average readings at 25C and VDD = 5 V. Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. 3 VAB = VDD, Wiper (VW) = no connect. 4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of 1 LSB maximum are guaranteed monotonic operating conditions. 5 The A, B, and W resistor terminals have no limitations on polarity with respect to each other. 6 Guaranteed by design; not subject to production test. 7 The minimum voltage requirement on the VIH is 0.7 V x VDD. For example, VIH minimum = 3.5 V when VDD = 5 V. It is typical for the SCL and SDA resistors to be pulled up to VDD. However, care must be taken to ensure that the minimum VIH is met when the SCL and SDA are driven directly from a low voltage logic controller without pullup resistors. 8 Guaranteed by design; not subject to production test. 9 Different from operating power supply; power supply for OTP is used one time only. 10 Different from operating current; supply current for OTP lasts approximately 400 ms for one-time need only. 11 See Figure 24 for the energy plot during the OTP program. 12 PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 13 Bandwidth, noise, and settling time depend on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption. 14 All dynamic characteristics use VDD = 5 V. 2 Rev. D | Page 4 of 24 AD5171 TIMING CHARACTERISTICS: 5 k, 10 k, 50 k, AND 100 k VDD = 3 V to 5 V 10%, VA = VDD, VB = 0 V, -40C < TA < +125C, unless otherwise noted. Table 2. Parameter INTERFACE TIMING CHARACTERISTICS (APPLY TO ALL PARTS 2, 3 ) SCL Clock Frequency tBUF Bus Free Time Between Start and Stop tHD;STA Hold Time (Repeated Start) Symbol fSCL t1 t2 tLOW Low Period of SCL Clock tHIGH High Period of SCL Clock tSU;STA Setup Time for Start Condition tHD;DAT Data Hold Time tSU;DAT Data Setup Time tF Fall Time of Both SDA and SCL Signals tR Rise Time of Both SDA and SCL Signals tSU;STO Setup Time for Stop Condition OTP Program Time 2 3 Min After this period, the first clock pulse is generated t3 t4 t5 t6 t7 t8 t9 t10 t11 1.3 0.6 0.6 t3 400 t6 t5 t9 t10 t7 t1 P kHz s s 50 0.6 t8 SDA 400 0.3 0.3 SCL t4 Unit 0.9 t9 t2 Max 0.1 Typical specifications represent average readings at 25C and VDD = 5 V. Guaranteed by design; not subject to production test. All dynamic characteristics use VDD = 5 V. t8 Typ 1 1.3 0.6 S P Figure 3. Interface Timing Diagram Rev. D | Page 5 of 24 03437-024 1 Conditions s s s s s s s s ms AD5171 ABSOLUTE MAXIMUM RATINGS Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter VDD to GND VA, VB, and VW to GND Maximum Current IWB, IWA Pulsed IWB Continuous (RWB 1 k, A Open) 1 IWA Continuous (RWA 1 k, B Open)1 Digital Inputs and Output Voltage to GND Operating Temperature Range Maximum Junction Temperature (TJ max) Storage Temperature Range Reflow Soldering Peak Temperature Time at Peak Temperature Thermal Resistance JA 2 Rating -0.3 V to +7 V GND to VDD 20 mA 5 mA 5 mA 0 V to VDD -40C to +125C 150C -65C to +150C ESD CAUTION 260C 20 sec to 40 sec 230C/W 1 Maximum terminal current is bounded by the maximum applied voltage across any two of the A, B, and W terminals at a given resistance; the maximum current handling of the switches, and the maximum power dissipation of the package. VDD = 5 V. 2 Package power dissipation = (TJ max - TA)/JA. Rev. D | Page 6 of 24 AD5171 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 8 AD5171 A B TOP VIEW GND 3 (Not to Scale) 6 AD0 SCL 4 7 5 SDA 03437-003 W 1 VDD 2 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic W VDD 3 4 GND SCL 5 SDA 6 7 8 AD0 B A Description Wiper Terminal W. GND VW VDD. Positive Power Supply. Specified for operation from 2.7 V to 5.5 V. For OTP programming, VDD needs to be within the 4.75 V and 5.25 V range and capable of driving 100 mA. Common Ground. Serial Clock Input. Requires a pull-up resistor. If it is driven direct from a logic controller without the pull-up resistor, ensure that the VIH minimum is 0.7 V x VDD. Serial Data Input/Output. Requires a pull-up resistor. If it is driven direct from a logic controller without a pull-up resistor, ensure that the VIH minimum is 0.7 V x VDD. I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed. Resistor Terminal B. GND VB VDD. Resistor Terminal A. GND VA VDD. Rev. D | Page 7 of 24 AD5171 TYPICAL PERFORMANCE CHARACTERISTICS 0.10 0.10 VDD = 5V POTENTIOMETER MODE DNL (LSB) -40C 0.04 0.02 0 -0.02 -0.04 +125C -0.06 +25C 0 8 16 24 32 40 +125C 0.02 0 -0.02 -0.04 -0.08 48 56 64 CODE (DECIMAL) -0.10 0 16 24 32 40 48 56 64 120 140 140 Figure 8. DNL vs. Code vs. Temperature 0.10 0 VDD = 5V 0.08 -0.1 +25C 0.06 +125C -0.2 0.04 0.02 FSE (LSB) RHEOSTAT MODE DNL (LSB) 8 CODE (DECIMAL) Figure 5. R-INL vs. Code vs. Temperature 0 -0.02 VDD = 5V -0.3 -0.4 VDD = 3V -40C -0.04 -0.5 -0.06 -0.6 -0.08 0 8 16 24 32 40 48 56 64 CODE (DECIMAL) -0.7 -40 03437-005 -0.10 -20 0 20 40 60 80 100 TEMPERATURE (C) Figure 6. R-DNL vs. Code vs. Temperature Figure 9. Full-Scale Error (FSE) vs. Temperature 0.6 0.10 VDD = 5V 0.08 0.5 0.06 0.04 +25C 0.4 +125C ZSE (LSB) 0.02 0 -0.02 -40C -0.04 VDD = 3V 0.3 VDD = 5V 0.2 -0.06 0.1 -0.08 -0.10 0 8 16 24 32 40 48 CODE (DECIMAL) 56 64 0 -40 03437-006 POTENTIOMETER MODE INL (LSB) +25C -40C -0.06 03437-007 -0.10 0.04 03437-008 -0.08 0.06 03437-009 0.06 VDD = 5V 0.08 03437-004 RHEOSTAT MODE INL (LSB) 0.08 -20 0 20 40 60 80 100 120 TEMPERATURE (C) Figure 7. INL vs. Code vs. Temperature Figure 10. Zero-Scale Error (ZSE) vs. Temperature Rev. D | Page 8 of 24 AD5171 6 10 0 VDD = 5V 0x20 0x10 -12 0x08 -18 1 GAIN (dB) IDD SUPPLY CURRENT (A) -6 VDD = 3V 0x04 -24 0x02 -30 0x01 -36 0x00 -42 0 20 40 60 80 100 120 140 TEMPERATURE (C) -54 100 03437-010 -20 180 6 160 0 140 -6 120 -12 100 -18 80 GAIN (dB) 1M 10M 60 40 0x3F 0x20 0x10 0x08 0x04 -24 0x02 -30 0x01 -36 20 -42 0 8 16 24 32 40 48 56 64 CODE (DECIMAL) -54 100 03437-011 -40 0x00 -48 -20 1k 10k 100k 1M 03437-014 0 1M 03437-015 RHEOSTAT MODE TEMPCO (ppm/C) 10k 100k FREQUENCY (Hz) Figure 14. Gain vs. Frequency vs. Code, RAB = 5 k Figure 11. IDD Supply Current vs. Temperature FREQUENCY (Hz) Figure 15. Gain vs. Frequency vs. Code, RAB = 10 k Figure 12. Rheostat Mode Tempco (RAB/RAB)/T vs. Code 6 25 0 20 -6 -12 15 GAIN (dB) -18 10 5 -24 -30 -36 0x3F 0x20 0x10 0x08 0x04 0x02 0x01 -42 0 -48 -5 0 8 16 24 32 40 48 56 64 CODE (DECIMAL) -54 100 03437-012 POTENTIOMETER MODE TEMPCO (ppm/C) 1k 03437-013 -48 0.1 -40 0x00 1k 10k 100k FREQUENCY (Hz) Figure 16. Gain vs. Frequency vs. Code, RAB = 50 Figure 13. Potentiometer Mode Tempco (VW /VW)/T vs. Code Rev. D | Page 9 of 24 AD5171 6 0x20 -6 DATA 0x00 0x3F 0x10 -12 VW = 5V/DIV 0x08 -18 GAIN (dB) VDD = 5.5V VA = 5.5V VB = GND fCLK = 400kHz 0x3F 0 0x04 -24 0x02 -30 SCL = 5V/DIV 0x01 -36 -48 5V 1k 10k 100k 1M FREQUENCY (Hz) 5V Figure 17. Gain vs. Frequency vs. Code, RAB = 100 k Figure 20. Settling Time 80 VDD = 5.5V VA = 5.5V VB = GND fCLK = 100kHz DATA 0x20 0x1F TA = 25C CODE = 0x20 VA = 2.5V, VB = 0V 60 VW = 50mV/DIV VDD = 5V DC 1.0V p-p AC VDD = 3V DC 0.6V p-p AC 40 20 10k 100k 1M FREQUENCY (Hz) Figure 18. Power Supply Rejection Ratio vs. Frequency 200ns 5s Figure 21. Midscale Glitch Energy fCLK = 100kHz VDD = 5.5V VA = 5.5V VB = GND 5V 03437-020 1k 03437-017 50mV 0 100 03437-021 SCL = 5V/DIV OTP PROGRAMMED AT MS VDD = 5.5V VA = 5.5V RAB = 10k VW = 10mV/DIV VW = 1V/DIV SCL = 5V/DIV 10mV 5V 500ns VDD = 5V/DIV 03437-018 POWER SUPPLY REJECTION RATIO (dB) 5s 03437-016 0x00 -54 100 03437-019 -42 1V Figure 19. Digital Feedthrough vs. Time 5V Figure 22. Power-Up Settling Time After Fuses Blown Rev. D | Page 10 of 24 AD5171 VA = VB = OPEN TA = 25C RAB = 5k CH1 MAX 103mA 1 RAB = 10k CH1 MIN -1.98mA RAB = 50k 0.1 RAB = 100k 0.01 0 8 16 24 32 40 48 CODE (DECIMAL) 56 64 Figure 23. Theoretical IWB_MAX vs. Code Rev. D | Page 11 of 24 CH1 20.0mA M 200ns A CH1 T 588.000ns 32.4mA Figure 24. OTP Program Energy Plot for Single Fuse 03437-023 1 03437-0-022 THEORETICAL IWB_MAX (mA) 10 AD5171 THEORY OF OPERATION A SCL SDA I2C MUX DAC REG. INTERFACE DECODER W B COMPARATOR FUSES EN FUSE REG. 03437-025 ONE-TIME PROGRAM/TEST CONTROL BLOCK Figure 25. Detailed Functional Block Diagram The AD5171 allows unlimited 6-bit adjustments, except for the one-time programmable, set-and-forget resistance setting. OTP technology is a proven, cost-effective alternative over EEMEM in one-time memory programming applications. The AD5171 employs fuse link technology to achieve the memory retention of the resistance setting function. It has six data fuses that control the address decoder for programming the RDAC, one user mode test fuse for checking setup error, and one programming lock fuse for disabling any further programming once the data fuses are blown. ONE-TIME PROGRAMMING (OTP) Prior to OTP activation, the AD5171 presets to midscale during initial power-on. After the wiper is set at the desired position, the resistance can be permanently set by programming the T bit high along with the proper coding (see Table 8 and Table 9) and one-time VDD_OTP. The fuse link technology of the AD517x family of digital potentiometers requires VDD_OTP between 4.75 V and 5.25 V to blow the fuses to achieve a given nonvolatile setting. On the other hand, VDD can be 2.7 V to 5.5 V during operation. As a result, a system supply that is lower than 4.75 V requires external supply for OTP. In addition, the user is only allowed one attempt in blowing the fuses. If the user fails to blow the fuses at the first attempt, the fuse structures may change so that they may never be blown regardless of the energy applied at subsequent events. For details, see the Power Supply Considerations section. The device control circuit has two validation bits, E1 and E0, that can be read back to check the programming status (see Table 5). Users should always read back the validation bits to ensure that the fuses are properly blown. After the fuses are blown, all fuse latches are enabled upon subsequent power-on; therefore, the output corresponds to the stored setting. Table 5. Validation Status E1 0 0 E0 0 1 1 0 1 1 Status Ready for programming. Test fuse not blown successfully. For factory setup checking purpose only. Users should not see these combinations. Fatal error. Some fuses are not blown. Do not retry. Discard the unit. Successful. No further programming is possible. This section discusses the fuse operation in detail. When the OTP T bit is set, the internal clock is enabled. The program then attempts to blow a test fuse. The operation stops if the test fuse is not properly blown. The validation bits, E1 and E0, show 01. This status is intended for factory setup checking purposes only; users should not see this status. If the test fuse is properly blown, the data fuses can be programmed. The six data fuses are programmed in six clock cycles. The output of the fuses is compared with the code stored in the RDAC register. If they do not match, E1 and E0 of 10 are issued as fatal errors and the operation stops. Users should never try blowing the fuses more than once because the fuse structure may have changed prohibiting further programming. As a result, the unit must be discarded. This error status can also occur if the OTP supply voltage goes above or drops below the VDD_OTP requirement, the OTP supply current is limited, or both the voltage and current ramp times are slow. If the output and stored code match, the programming lock fuse is blown so that no further programming is possible. In the meantime, E1 and E0 issue 11, indicating the lock fuse is properly blown. All the fuse latches are enabled at power-on; therefore, from this point on, the output corresponds to the stored setting. Figure 25 shows a detailed functional block diagram. Rev. D | Page 12 of 24 AD5171 VARIABLE RESISTANCE AND VOLTAGE FOR RHEOSTAT MODE If only the W-to-B or W-to-A terminals are used as variable resistors, the unused terminal can be opened or shorted with Terminal W. This operation is called rheostat mode (see Figure 26). W B A W B W B RWA (D) = (2) Table 7. RWA vs. Codes: RAB = 10 k; Terminal B Open Figure 26. Rheostat Mode Configuration The nominal resistance (RAB) of the RDAC has 64 contact points accessed by the wiper terminal, plus Terminal B contact if RWB is considered. The 6-bit data in the RDAC latch is decoded to select one of the 64 settings. Assuming that a 10 k part is used, the first connection of the wiper starts at Terminal B for Data 0x00. Such a connection yields a minimum of 60 resistance between Terminal W and Terminal B due to the 60 wiper contact resistance. The second connection is the first tap point, which corresponds to 219 (RWB = 1 x RAB/63 + RW) for Data 0x01, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,060 (63 x RAB/63 + RW). Figure 27 shows a simplified diagram of the equivalent RDAC circuit. The general equation determining RWB is RWB (D) = 63 - D x R AB + RW 63 D x R AB + RW 63 D (Dec) 63 32 1 0 RWA () 60 4980 9901 10060 Output State Full-scale Midscale 1 LSB Zero-scale The typical distribution of the resistance tolerance from device to device is process-lot dependent; it is possible to have 30% tolerance. A D5 D4 D3 D2 D1 D0 (1) RS RS W where: D is the decimal equivalent of the 6-bit binary code. RAB is the end-to-end resistance. RW is the wiper resistance contributed by the on-resistance of the internal switch. RDAC LATCH AND DECODER RS B D (Dec) 63 32 1 0 RWB () 10060 5139 219 60 Output State Full-scale (RAB + RW) Midscale 1 LSB Zero-scale (wiper contact resistance) Because a finite wiper resistance of 60 is present in the zeroscale condition, care should be taken to limit the current flow between Terminal W and Terminal B in this state to a maximum pulse current 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur. 03437-026 Table 6. RWB vs. Codes: RAB = 10 k; Terminal A Open Figure 27. AD5171 Equivalent RDAC Circuit VARIABLE RESISTANCE AND VOLTAGE FOR POTENTIOMETER MODE If all three terminals are used, the operation is called the potentiometer mode. The most common configuration is the voltage divider operation (see Figure 28). VI A W B VO 03437-051 A 03437-050 A Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper (Terminal W) and Terminal A also produces a complementary resistance, RWA. When these terminals are used, Terminal B can be opened or shorted to Terminal W. Setting the resistance value for RWA starts at a maximum value of resistance and decreases as the data loaded in the latch increases in value. The general equation for this operation is Figure 28. Potentiometer Mode Configuration Rev. D | Page 13 of 24 AD5171 VW (D) = D VA 63 (3) A more accurate calculation, which includes the wiper resistance effect, yields D R AB + RW 63 VW (D) = VA R AB + 2RW (4) Unlike in rheostat mode where the absolute tolerance is high, potentiometer mode yields an almost ratiometric function of D/63 with a relatively small error contributed by the RW terms; thus, the tolerance effect is almost cancelled. Although the thin film step resistor (RS) and CMOS switches resistance (RW) have very different temperature coefficients, the ratiometric adjustment also reduces the overall temperature coefficient effect to 5 ppm/C, except at low value codes where RW dominates. Potentiometer mode includes other operations such as op amp input, feedback resistor networks, and voltage scaling applications. Terminal A, Terminal W, and Terminal B can, in fact, be input or output terminals provided that |VAB|, |VWA|, and |VWB| do not exceed VDD to GND. POWER SUPPLY CONSIDERATIONS To minimize the package pin count, both the OTP and normal operating voltage supplies share the same VDD terminal of the AD5171. The AD5171 employs fuse link technology that requires 4.75 V to 5.25 V for blowing the internal fuses to achieve a given setting, but normal VDD can be anywhere between 2.7 V and 5.5 V after the fuse programming process. As a result, dual voltage supplies and isolation are needed if system VDD is lower than the required VDD_OTP. The fuse programming supply (either an on-board regulator or rack-mount power supply) must be rated at 4.75 V to 5.25 V and able to provide a 100 mA current for 400 ms for successful one-time programming. Once fuse programming is complete, the VDD_OTP supply must be removed to allow normal operation at 2.7 V to 5.5 V; the device then consumes current in the A range. When operating at 2.7 V, use of the bidirectional low threshold P-Ch MOSFETs is recommended for the isolation of the supply. As shown in Figure 29, this assumes that the 2.7 V system voltage is applied first, and the P1 and P2 gates are pulled to ground, thus turning on P1 and, subsequently, P2. As a result, VDD of the AD5171 approaches 2.7 V. When the AD5171 setting is found, the factory tester applies the VDD_OTP to both the VDD and the MOSFETs gates, thus turning off P1 and P2. The OTP command should be executed at this time to program the AD5171 while the 2.7 V source is protected. Once the fuse programming is complete, the tester withdraws the VDD_OTP and the setting of the AD5171 is permanently fixed. The AD5171 achieves the OTP function through blowing internal fuses. Users should always apply the 4.75 V to 5.25 V one-time program voltage requirement at the first fuse programming attempt. Failure to comply with this requirement may lead to a change in the fuse structures, rendering programming inoperable. Care should be taken when SCL and SDA are driven from a low voltage logic controller. Users must ensure that the logic high level is between 0.7 V x VDD and VDD. Refer to the Level Shifting for Different Voltage Operation section. Poor PCB layout introduces parasitics that may affect the fuse programming. Therefore, it is recommended that a 10 F tantalum capacitor be added in parallel with a 1 nF ceramic capacitor as close as possible to the VDD pin. The type and value chosen for both capacitors are important. This combination of capacitor values provides both a fast response and larger supply current handling with minimum supply droop during transients. As a result, these capacitors increase the OTP programming success by not inhibiting the proper energy needed to blow the internal fuses. Additionally, C1 minimizes transient disturbance and low frequency ripple, while C2 reduces high frequency noise during normal operation. ESD PROTECTION Digital inputs SDA and SCL are protected with a series input resistor and parallel Zener ESD structures (see Figure 30). 340 APPLY FOR OTP ONLY 5V R1 GND 10k LOGIC 03437-027 Ignoring the effect of the wiper resistance, the transfer function is simply Figure 30. ESD Protection of Digital Pins 2.7V P1 P2 C1 10F C2 0.1F VDD AD5171 03437-052 P1 = P2 = FDV302P, NDS0610 Figure 29. 5 V OTP Supply Isolated from the 2.7 V Normal Operating Supply; the VDD_OTP supply must be removed once OTP is complete. Rev. D | Page 14 of 24 AD5171 TERMINAL VOLTAGE OPERATING RANGE POWER-UP/POWER-DOWN SEQUENCES There are also ESD protection diodes between VDD and the RDAC terminals; therefore, the VDD of the AD5171 defines their voltage boundary conditions (see Figure 31). Supply signals present on Terminal A, Terminal B, and Terminal W that exceed VDD are clamped by the internal forward-biased diodes and should be avoided. Similarly, because of the ESD protection diodes, it is important to power VDD first before applying any voltages to Terminal A, Terminal B, and Terminal W. Otherwise, the diode is forwardbiased such that VDD is powered unintentionally and can affect the remainder of the users' circuits. The ideal power-up sequence is the following order: GND, VDD, digital inputs, and VA/VB/VW. The order of powering VA, VB, VW, and the digital inputs is not important as long as they are powered after VDD. Similarly, VDD should be powered down last. VDD A W GND 03437-029 B Figure 31. Maximum Terminal Voltages Set by VDD Rev. D | Page 15 of 24 AD5171 CONTROLLING THE AD5171 There are two ways of controlling the AD5171. Users can either program the devices with computer software or employ external I2C controllers. SOFTWARE PROGRAMMING Due to the advantage of the one-time programmable feature, users may consider programming the device in the factory before shipping it to the end users. Analog Devices offers device programming software that can be implemented in the factory on PCs running Windows 95 to Windows XP platforms. As a result, external controllers are not required, which significantly reduces development time. Read To read the validation bits and data from the device, click Read. The user may also set the bit pattern in the upper screen and click Run. The format of reading data out from the device is shown in Table 9. DEVICE PROGRAMMING To apply the device programming software in the factory, users need to modify a parallel port cable and configure Pin 2, Pin 3, Pin 15, and Pin 25 for SDA_write, SCL, SDA_read, and DGND, respectively, for the control signals (see Figure 33). In addition, lay out the PCB of the AD5171 with SCL and SDA pads, as shown in Figure 34, such that pogo pins can be inserted for the factory programming. 03437-032 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 Figure 32. Software Interface Write The AD5171 starts at midscale after power-up prior to the OTP programming. To increment or decrement the resistance, move the scrollbar on the left. To write any specific values, use the bit pattern control in the upper screen and click Run. The format of writing data to the device is shown in Table 8. Once the desired setting is found, click Program Permanent to blow the internal fuse links for permanent setting. The user can also set the programming bit pattern in the upper screen and click Run to achieve the same result. R3 SCL 100 R2 READ SDA 100 R1 WRITE 100 03437-033 The program is an executable file that does not require the user to know any programming languages or programming skills. It is easy to set up and use. Figure 32 shows the software interface. The software can be downloaded from the AD5171 product page. W VDD GND SCL A B AD0 SDA 04104-034 Figure 33. Parallel Port Connection: Pin 2 = SDA_write, Pin 3 = SCL, Pin 15 = SDA_read, and Pin 25 = DGND Figure 34. Recommended AD5171 PCB Layout Table 8. SDA Write Mode Bit Format S 0 1 0 1 1 0 AD0 Slave Address Byte 0 A T X X X X X Instruction Byte X X A X X D5 D4 D3 D2 Data Byte D1 D0 A P Table 9. SDA Read Mode Bit Format S 0 1 0 1 1 0 AD0 Slave Address Byte 1 A E1 E0 Rev. D | Page 16 of 24 D5 D4 D3 Data Byte D2 D1 D0 A P AD5171 Table 10. SDA Bits Definitions and Descriptions Bit S P A AD0 X T D5, D4, D3, D2, D1, D0 E1, E0 Description Start Condition. Stop Condition. Acknowledge. I2C Device Address Bit. Allows a maximum of two AD5171s to be addressed. Don't Care. OTP Programming Bit. Logic 1 programs the wiper position permanently. Data Bits. OTP Validation Bits: 0, 0 = Ready to Program. 0, 1 = Test Fuse Not Blown Successfully. For factory setup checking purpose only. Users should not see these combinations. 1, 0 = Fatal Error. Do not retry. Discard the unit. 1, 1 = Programmed Successfully. No further adjustments are possible. I2C CONTROLLER PROGRAMMING Write Bit Patterns 1 9 9 1 1 9 SCL 1 0 1 0 1 AD0 R/W 0 X X X X X X X ACK. BY AD5171 START BY MASTER X X D4 D5 D3 D2 D1 ACK. BY AD5171 FRAME 1 SLAVE ADDRESS BYTE D0 ACK. BY AD5171 FRAME 2 INSTRUCTION BYTE FRAME 1 DATA BYTE STOP BY MASTER 03437-035 0 STOP BY MASTER 03437-036 SDA Figure 35. Writing to the RDAC Register 1 9 9 1 1 9 SCL SDA 0 1 0 1 0 1 1 AD0 R/W X X X X X X X ACK. BY AD5171 START BY MASTER X X D5 D4 D3 D2 D1 ACK. BY AD5171 FRAME 1 SLAVE ADDRESS BYTE D0 ACK. BY AD5171 FRAME 2 INSTRUCTION BYTE FRAME 1 DATA BYTE Figure 36. Activating One-Time Programming Read Bit Pattern 1 9 1 9 SCL START BY MASTER 0 1 0 1 1 0 E1 AD0 R/W ACK. BY AD5171 E0 D5 D4 D3 D2 D1 D0 NO ACK. BY MASTER FRAME 1 SLAVE ADDRESS BYTE FRAME 2 RDAC REGISTER STOP BY MASTER 03437-037 SDA Figure 37. Reading Data from RDAC Register I2C-COMPATIBLE 2-WIRE SERIAL BUS For users who prefer to use external controllers, the AD5171 can be controlled via an I2C-compatible serial bus; the part is connected to this bus as a slave device. The following section describes how the 2-wire I2C serial bus protocol operates (see Figure 35, Figure 36, and Figure 37). The master initiates data transfer by establishing a start condition, which is when SDA goes from high to low while SCL is high (see Figure 35 and Figure 36). The following byte is the slave address byte, which consists of the 6 MSBs as a slave address defined as 010110. The next bit is AD0, which is an I2C device address bit. Depending on the states of their AD0 bits, two AD5171s can be addressed on the same bus (see Figure 38). The last LSB is the R/W bit, which determines whether data is read from, or written to, the slave device. The slave address corresponding to the transmitted address bit responds by pulling the SDA line low during the 9th clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to, or read from, its serial register. The write operation contains one instruction byte more than the read operation. The instruction byte in the write mode follows the slave address byte. The MSB of the instruction byte labeled T is the one-time programming bit. After acknowledging Rev. D | Page 17 of 24 AD5171 the instruction byte, the last byte in the write mode is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 35). In read mode, the data byte follows immediately after the acknowledgment of the slave address byte. Data is transmitted over the serial bus in sequences of nine clock pulses (note the slight difference from the write mode; there are eight data bits followed by a no acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 37). When all data bits are read or written, a stop condition is established by the master. A stop condition is defined as a lowto-high transition on the SDA line while SCL is high. In the write mode, the master pulls the SDA line high during the 10th clock pulse to establish a stop condition (see Figure 35 and Figure 36). In the read mode, the master issues a no acknowledge for the 9th clock pulse, that is, the SDA line remains high. The master then brings the SDA line low before the 10th clock pulse, which goes high to establish a stop condition (see Figure 37). A repeated write function gives the user flexibility to update the RDAC output a number of times, except after permanent programming, addressing, and instructing the part only once. During the write cycle, each data byte updates the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output updates after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte updates the output of the selected slave device. If different instructions are needed, the write mode has to be started with a new slave address, instruction, and data bytes. Similarly, a repeated read function of the RDAC is also allowed. CONTROLLING TWO DEVICES ON ONE BUS Figure 38 shows two AD5171 devices on the same serial bus. Each has a different slave address because the state of each AD0 pin is different, which allows each device to be independently operated. The master device output bus line drivers are opendrain pull-downs in a fully I2C-compatible interface. 5V Rp Rp SDA MASTER SDA SCL AD0 AD5171 5V SDA SCL AD0 AD5171 Figure 38. Two AD5171 Devices on One Bus Rev. D | Page 18 of 24 03437-038 SCL AD5171 APPLICATIONS INFORMATION DAC It is common to buffer the output of the digital potentiometer as a DAC unless the load is much larger than RWB. The buffer can impede conversion and deliver higher current, if needed. 5V AD5171 VIN 5V A 3 W U1 U2 VO AD8601 AD1582 B GND 2 LEVEL SHIFTING FOR DIFFERENT VOLTAGE OPERATION 03437-039 1 VOUT A1 In this circuit, the inverting input of the op amp forces the VOUT to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the NCh FET N1. N1 power handling must be adequate to dissipate (VI - VO) x IL power. This circuit can source a maximum of 100 mA with a 5 V supply. For precision applications, a voltage reference, such as the ADR421, ADR03, or ADR370, can be applied at Terminal A of the digital potentiometer. Figure 39. Programmable Voltage Reference (DAC) GAIN CONTROL COMPENSATION The digital potentiometers are commonly used in gain controls or sensor transimpedance amplifier signal conditioning applications (see Figure 40). To avoid gain peaking, or in worstcase oscillation due to step response, a compensation capacitor is needed. In general, C2 in the range of a few picofarads to a few tenths of a picofarad is adequate for the compensation. If the SCL and SDA signals come from a low voltage logic controller and are below the minimum VIH level (0.7 V x VDD), level shift the signals for read/write communications between the AD5171 and the controller. Figure 42 shows one of the implementations. For example, when SDA1 is at 2.5 V, M1 turns off, and SDA2 becomes 5 V. When SDA1 is at 0 V, M1 turns on, and SDA2 approaches 0 V. As a result, proper level shifting is established. M1 and M2 should be low threshold N-Ch power MOSFETs, such as FDV301N. VDD2 = 5V VDD1 = 2.5V C2 Rp Rp Rp Rp 4.7pF R2 100k G A W R1 SDA1 U1 VOUT A CC +V W U2 RBIAS IL AD8601 B LD -V SIGNAL 03437-041 U1 AD5171 Figure 42. Level Shifting for Different Voltage Operation For applications that require high current adjustment, such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 41). AD5171 SCL2 2.7V-5.5V 2.5V CONTROLLER PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT U3 2N7002 SDA2 D S M2 Figure 40. Typical Noninverting Gain Amplifier VIN M1 SCL1 03437-040 VI VO G 03437-042 47k D S RESISTANCE SCALING The AD5171 offers 5 k, 10 k, 50 k, and 100 k nominal resistances. For users who need to optimize the resolution with an arbitrary full range resistance, the following techniques can be used. By paralleling a discrete resistor, a proportionately lower voltage appears at Terminal A to Terminal B, which is applicable only to the voltage divider mode (see Figure 43). This translates into a finer degree of precision because the step size at Terminal W is smaller. The voltage can be found as VW (D) = Figure 41. Programmable Booster Voltage Source (R AB || R2) D x x VDD R3 + R AB || R2 64 VDD R3 A R2 R1 B W 03437-043 B Figure 43. Lowering the Nominal Resistance Rev. D | Page 19 of 24 (5) AD5171 VW (D ) = (RWB || R 2) x VI RWA + RWB || R 2 (6) VI A VO R1 W B RDAC CIRCUIT SIMULATION MODEL The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the digital potentiometers. Configured as a potentiometer divider, the -3 dB bandwidth of the AD5171 (5 k resistor) measures 1.5 MHz at half scale. Figure 14 to Figure 17 provide the large signal BODE plot characteristics of the four available resistor versions: 5 k, 10 k, 50 k, and 100 k. A parasitic simulation model is shown in Figure 46. Listing 1 provides a macro model net list for the 10 k device. R2 03437-044 A CA 25pF Figure 44. Resistor Scaling with Log Adjustment Characteristics W The resolution can be doubled in the potentiometer mode of operation by using three digital potentiometers. Borrowed from the Analog Devices patented RDAC segmentation technique, users can configure three AD5171s to double the resolution (see Figure 45). First, U3 must be parallel with a discrete resistor, RP, which is chosen to be equal to a step resistance (RP = RAB/64). Adjusting U1 and U2 together forms the coarse 6-bit adjustment, and adjusting U3 alone forms the finer 6-bit adjustment. As a result, the effective resolution becomes 12-bit. A1 W1 A3 B1 RP U3 Listing 1. Macro Model Net List for RDAC .PARAM D=64, RDAC=10E3 * .SUBCKT DPOT (A,W,B) * CA A 0 25E-12 RWA A W {(1-D/64)*RDAC+60} CW W 0 55E-12 RWB W B {D/64*RDAC+60} CB B 0 25E-12 .ENDS DPOT B3 03437-045 W2 B2 COARSE FINE ADJUSTMENT ADJUSTMENT CB 25pF Figure 46. Circuit Simulation Model for RDAC = 10 k * W3 A2 U2 B CW 55pF RESOLUTION ENHANCEMENT U1 RDAC 10k 03437-046 For log taper adjustment, such as volume control, Figure 44 shows another way of resistance scaling. In this circuit, the smaller the R2 with respect to RAB, the more it behaves like the pseudo log taper characteristic. The wiper voltage is simply Figure 45. Doubling the Resolution Rev. D | Page 20 of 24 AD5171 EVALUATION BOARD JP5 VCC JP3 VDD V+ U4 C4 0.1F ADR03 CP3 VREF C5 0.1F -IN1 CP4 CP2 JP1 JP8 CP1 8 2 A W B VDD VDD C1 10F R2 10k R1 10k J1 8 7 6 5 4 3 2 1 1 2 3 4 C2 0.1F SCL U1 8 A 7 B 6 AD0 SDA 5 W VDD GND SCL 1 2 3 4 C3 0.1F U2 W VDD GND SCL 3 VIN 4 U3A CP6 V- CP5 +IN1 CP7 OUT1 JP4 AGND C8 0.1F AD5171/AD5273 AD5170 OUT1 1 JP7 JP2 8 A 7 B AD0 6 SDA 5 C7 10F SDA JP6 -IN2 VEE 6 7 +IN2 C9 10F 5 U3B OUT2 03437-047 VDD C6 0.1F -IN1 5 1 TEMP TRIM 2 GND 4 3 VIN VOUT Figure 47. Evaluation Board Schematic The AD5171 evaluation board comes with a dual op amp AD822 and a 2.5 V reference ADR03. Users can configure many building block circuits with minimal components needed. Figure 48 shows one of the examples. There is space available on the board where users can build additional circuits for further evaluations as shown in Figure 49. CP2 VREF JP3 W VO JP2 U3A V+ 1 JP7 U2 B 4 2 W 3 11 V- OUT1 AD822 JP4 03437-049 A A 03437-048 JP1 VREF B VDD Figure 49. Evaluation Board Figure 48. Programmable Voltage Reference Rev. D | Page 21 of 24 AD5171 OUTLINE DIMENSIONS 2.90 BSC 8 7 6 5 1 2 3 4 1.60 BSC 2.80 BSC PIN 1 INDICATOR 0.65 BSC 1.95 BSC 1.30 1.15 0.90 1.45 MAX 0.15 MAX 0.38 0.22 0.22 0.08 SEATING PLANE 8 4 0 0.60 0.45 0.30 COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 50. 8-Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD5171BRJ5-R2 AD5171BRJ5-RL7 AD5171BRJZ5-R2 2 AD5171BRJZ5-R72 AD5171BRJ10-R2 AD5171BRJ10-RL7 AD5171BRJZ10-R22 AD5171BRJZ10-R72 AD5171BRJ50-R2 AD5171BRJ50-RL7 AD5171BRJZ50-R22 AD5171BRJZ50-R72 AD5171BRJ100-R2 AD5171BRJ100-RL7 AD5171BRJZ100-R22 AD5171BRJZ100-R72 AD5171EVAL 3 RAB (k) 5 5 5 5 10 10 10 10 50 50 50 50 100 100 100 100 10 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 Evaluation Board 1 Package Option RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 RJ-8 Ordering Quantity 250 3000 250 3000 250 3000 250 3000 250 3000 250 3000 250 3000 250 3000 1 Branding D12 D12 D12# D12# D13 D13 D13# D13# D14 D14 D14# D14# D15 D15 D15# D15# Parts have a YWW or #YWW marking on the bottom of the package. Y shows the year that the part was made, for example, Y = 5 for 2005. WW shows the work week that the part was made. Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked. 3 The evaluation board is shipped with three pieces of 10 k parts. Users should order extra samples or different resistance options if needed. 2 Rev. D | Page 22 of 24 AD5171 NOTES Rev. D | Page 23 of 24 AD5171 NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. (c)2004-2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D03437-0-7/08(D) Rev. D | Page 24 of 24