SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES204J – APRIL 1999 – REVISED JUNE 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Available in the Texas Instruments
NanoStarand NanoFreePackages
D
Supports 5-V VCC Operation
D
Inputs Accept Voltages to 5.5 V
D
Max tpd of 4.3 ns at 3.3 V
D
Low Power Consumption, 10-µA Max ICC
D
±24-mA Output Drive at 3.3 V
D
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
D
Ioff Supports Partial-Power-Down Mode
Operation
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features
dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input
is high.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING‡
NanoStar – WCSP (DSBGA)
0.17-mm Small Bump – YEA SN74LVC2G125YEAR
NanoFree – WCSP (DSBGA)
0.17-mm Small Bump – YZA (Pb-free)
Reel of 3000
SN74LVC2G125YZAR
CM
–
40
°
Cto85
°
C
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
Reel
of
3000
SN74LVC2G125YEPR _ _ _
CM
_
40 C
to
85 C
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free) SN74LVC2G125YZPR
SSOP – DCT Reel of 3000 SN74LVC2G125DCTR C25_ _ _
VSSOP DCU
Reel of 3000 SN74LVC2G125DCUR
C25
VSSOP
–
DCU
Reel of 250 SN74LVC2G125DCUT
C25
_
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
‡DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEA/YZA, YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code,
and one following character to designate the assembly/test site.
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
DCT OR DCU PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
2Y
GND
VCC
2OE
1Y
2A
4
3
2
1
5
6
7
8
GND
2Y
1A
1OE
2A
1Y
2OE
VCC
YEA, YEP, YZA, OR YZP PACKAGE
(BOTTOM VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES204J – APRIL 1999 – REVISED JUNE 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each buffer)
INPUTS OUTPUT
OE A Y
L H H
LLL
H X Z
logic diagram (positive logic)
1A 1Y
1OE 1
26
2A 2Y
2OE 7
53
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, VO
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DCT package 220°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DCU package 227°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
YEA/YZA package 140°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
YEP/YZP package 102°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES204J – APRIL 1999 – REVISED JUNE 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
VCC
Su
pp
ly voltage
Operating 1.65 5.5
V
V
CC
Supply
voltage
Data retention only 1.5
V
VCC = 1.65 V to 1.95 V 0.65 ×VCC
VIH
High level in
p
ut voltage
VCC = 2.3 V to 2.7 V 1.7
V
V
IH
High
-
level
input
voltage
VCC = 3 V to 3.6 V 2
V
VCC = 4.5 V to 5.5 V 0.7 ×VCC
VCC = 1.65 V to 1.95 V 0.35 ×VCC
VIL
Low level in
p
ut voltage
VCC = 2.3 V to 2.7 V 0.7
V
V
IL
Low
-
level
input
voltage
VCC = 3 V to 3.6 V 0.8
V
VCC = 4.5 V to 5.5 V 0.3 ×VCC
VIInput voltage 0 5.5 V
VO
Out
p
ut voltage
High or low state 0 VCC
V
V
O
Output
voltage
3-state 0 5.5
V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current
VCC =3V
–16 mA
V
CC =
3
V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current
VCC =3V
16 mA
V
CC =
3
V
24
VCC = 4.5 V 32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20
∆t/∆vInput transition rise or fall rate VCC = 3.3 V ± 0.3 V 10 ns/V
VCC = 5 V ±0.5 V 5
TAOperating free-air temperature –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES204J – APRIL 1999 – REVISED JUNE 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP†MAX UNIT
IOH = –100
m
A1.65 V to 5.5 V VCC–0.1
IOH = –4 mA 1.65 V 1.2
IOH = –8 mA 2.3 V 1.9
V
OH IOH = –16 mA
3V
2.4
V
IOH = –24 mA
3
V
2.3
IOH = –32 mA 4.5 V 3.8
IOL = 100
m
A1.65 V to 5.5 V 0.1
IOL = 4 mA 1.65 V 0.45
IOL = 8 mA 2.3 V 0.3
V
OL IOL = 16 mA
3V
0.4
V
IOL = 24 mA
3
V
0.55
IOL = 32 mA 4.5 V 0.55
IIA or OE inputs VI = 5.5 V or GND 0 to 5.5 V ±5
m
A
Ioff VI or VO = 5.5 V 0±10
m
A
IOZ VO = 0 to 5.5 V 3.6 V 10
m
A
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10
m
A
∆ICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500
m
A
Ci
Data inputs
VI=V
CC or GND
33V
3.5 p
F
C
iControl inputs
V
I =
V
CC
or
GND
3
.
3
V
4
pF
CoVO = VCC or GND 3.3 V 6.5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V VCC = 5 V
± 0.5 V UNIT
(INPUT)
(OUTPUT)
MIN MAX MIN MAX MIN MAX MIN MAX
tpd AY3.3 9.1 1.5 4.8 1.4 4.3 1 3.7 ns
ten OE Y4 9.9 1.9 5.6 1.2 4.7 1.2 3.8 ns
tdis OE Y1.5 11.6 1 5.8 1.4 4.6 1 3.4 ns
operating characteristics, TA = 25°
PARAMETER
TEST VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
UNIT
PARAMETER
CONDITIONS TYP TYP TYP TYP
UNIT
Cpd
Power dissipation Outputs enabled
f=10MHz
19 19 20 22 p
F
C
p
d
capacitance Outputs disabled
f
=
10
MHz
2 2 2 3
pF
SN74LVC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES204J – APRIL 1999 – REVISED JUNE 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VM
th
tsu
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT
S1 VLOAD
Open
GND
RL
RL
Data Input
Timing Input VI
0 V
VI
0 V
0 V
tw
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VI
0 V
Input
Output
W aveform 1
S1 at VLOAD
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VLOAD/2
0 V
VOL + V∆
VOH – V∆≈0 V
VI
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VMVM
VMVM
VMVM
VM
VMVM
VM
VM
VM
VI
VM
VM
1.8 V ±0.15 V
2.5 V ±0.2 V
3.3 V ±0.3 V
5 V ±0.5 V
1 kΩ
500 Ω
500 Ω
500 Ω
VCC RL
2 × VCC
2 × VCC
6 V
2 × VCC
VLOAD CL
30 pF
30 pF
50 pF
50 pF
0.15 V
0.15 V
0.3 V
0.3 V
V∆
VCC
VCC
3 V
VCC
VI
VCC/2
VCC/2
1.5 V
VCC/2
VM
tr/tf
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
INPUTS
Figure 1. Load Circuit and Voltage Waveforms
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
0,60
0,20
0,25
0°– 8°
0,15 NOM
Gage Plane
4188781/C 09/02
4,25
5
0,30
0,15
2,90 3,75
2,70
8
4
3,15
2,75
1
0,10
0,00
1,30 MAX
Seating Plane
0,10
M
0,13
0,65
PIN 1
INDEX AREA
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
MECHANICAL DATA
MXBG002B AUGUST 2001 – REVISED MAY 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
YEA (R–XBGA–N8) DIE–SIZE BALL GRID ARRAY
ÉÉ
ÉÉ
ÉÉ
ÉÉ
4203167 – 4/C 04/2002
0,50 MAX
0,35 MAX
1,85
1,95
A
0,95
0,85
0,19
C
0,15
0,10
SEATING PLANE
C
0,05
0,05 M
8X 0,15
0,05 MCB
CA
0,25
PIN A1 INDEX AREA
1
A
2
B
C
B0,25
D
0,50
1,50
0,50
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoStar package configuration.
D. Package complies to JEDEC MO–211 variation EB.
E. This package is tin–lead (SnPb). Refer to the 8 YZA package (drawing 4204151) for lead–free.
 
MXBG006A – JANUARY 2002 – REVISED APRIL 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
YZA (R-XBGA-N8) DIE-SIZE BALL GRID ARRAY
1,85
1,95
A
0,95
0,85 B
A
1
B
C
0,19
0,15
8X
2
D
4204151-4/B 03/2002
0,10
0,15
Seating Plane
C
0,05 C
Pin A1 Index Area
0,50 MAX
0,35 MAX
0,50
0,25
0,50
0,25
1,50
0,05
0,05 BCA
MC
M
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoFree package configuration.
D. Package complies to JEDEC MO-211 variation EB.
E. This package is lead-free. Refer to the 8 YEA package (drawing 4203167) for tin-lead (SnPb).
NanoFree is a trademark of Texas Instruments.
MECHANICAL DATA
MXBG020 – OCTOBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
YZP (R-XBGA-N8) DIE-SIZE BALL GRID ARRAY
1,85
1,95
A
0,95
0,85
0,25
0,05
8X 0,20
0,05 MCBCA
0,25
Pin A1 Index Area
1
A
2
B
C
B0,25
D
0,50
1,50
0,50
4204741-4/A 10/2002
0,05
0,50 Max
0,20
0,15
C
Seating Plane
C
M
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoFree package configuration.
D. This package is lead-free. Refer to the 8 YEP package (drawing 4204725) for tin-lead (SnPb).
NanoFree is a trademark of Texas Instruments.
MECHANICAL DATA
MXBG023 – OCTOBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
YEP (R-XBGA-N8) DIE-SIZE BALL GRID ARRAY
1,85
1,95
A
0,95
0,85
0,25
8X 0,20
0,25
Pin A1 Index Area
1
A
2
B
C
B0,25
D
0,50
1,50
0,50
4204725-4/A 10/2002
0,50 Max
0,20
0,15
C
Seating Plane
0,05
0,05 MCB
CA
0,05 C
M
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. NanoFree package configuration.
D. This package is tin-lead (SnPb). Refer to the 8 YZP package (drawing 420741) for lead-free.
NanoFree is a trademark of Texas Instruments.
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enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
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Mailing Address:
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Post Office Box 655303
Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated