56F800
16-bit Digital Signal Controllers
freescale.com
56F826
Data Sheet
Preliminary Technical Data
DSP56F826
Rev. 14
01/2007
56F826 Technical Data, Rev. 14
Freescale Semiconductor 3
56F826 Block Diagram
JTAG/
OnCE
Port
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36 → 36-Bit MAC
Three 16-bit Input Registers
Two 36-bit Accumulators
Address
Generation
Unit
Bit
Manipulation
Unit
PLL
Clock Gen
16-Bit
56800
Core
PAB
PDB
XDB2
CGDB
XAB1
XAB2
XTAL
EXTAL
INTERRUPT
CONTROLS
IPBB
CONTROLS
IPBus Bridge
(IPBB)
MODULE CONTROLS
ADDRESS BUS [8:0]
DATA BUS [15:0]
COP
RESET
Applica-
tion-Specific
Memory &
Peripherals
Interrupt
Controller
Program Memory
32252 x 16 Flash
512 x 16 SRAM
Boot Flash
2048 x 16 Flash
Data Memory
2048 x 16 Flash
4096 x 16 SRAM
COP/
Watchdog
SCI0 & SCI1
or
SPI0
SSI
or
GPIO
Quad Timer
or
GPIO
4
6
4
16 16
VDDIO VSSIO VDDA VSSA
644
SPI1
or
GPIO
4
Dedicated
GPIO
16
External
Bus
Interface
Unit
External
Address Bus
Switch
Bus
Control
External
Data Bus
Switch
RD Enable
WR Enable
DS Select[1]
PS Select[0]
16
16
D[00:15]
A[00:15]
or
GPIO
CLKO
RESET
IRQA
IRQB
EXTBOOT
VDD VSS
34
TOD
Timer
Low Voltage SupervisorAnalog Reg
56F826 General Description
• Up to 40 MIPS at 80MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Hardware DO and REP loops
• MCU-friendly instruction set supports both DSP
and controller functions: MAC, bit manipulation
unit, 14 addressing modes
• 31.5K × 16-bit words (64KB) Program Flash
• 512 × 16-bit words (1KB) Program RAM
•2K × 16-bit words (4KB) Data Flash
•4K × 16-bit words (8KB) Data RAM
•2K × 16-bit words (4KB) BootFLASH
• Up to 64K × 16-bit words each of external memory
expansion for Program and Data memory
• One Serial Port Interface (SPI)
• One additional SPI or two optional Serial
Communication Interfaces (SCI)
• One Synchronous Serial Interface (SSI)
• One General Purpose Quad Timer
• JTAG/OnCE™ for debugging
• 100-pin LQFP Package
• 16 dedicated and 30 shared GPIO
• Time-of-Day (TOD) Timer
56F826 Technical Data, Rev. 14
4 Freescale Semiconductor
Part 1 Overview
1.1 56F826 Features
1.1.1 Processing Core
• Efficient 16-bit 56800 family controller engine with dual Harvard architecture
• As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency
• Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC)
• Two 36-bit accumulators, including extension bits
• 16-bit bidirectional barrel shifter
• Parallel instruction set with unique processor addressing modes
• Hardware DO and REP loops
• Three internal address buses and one external address bus
• Four internal data buses and one external data bus
• Instruction set supports both DSP and controller functions
• Controller-style addressing modes and instructions for compact code
• Efficient C Compiler and local variable support
• Software subroutine and interrupt stack with depth limited only by memory
• JTAG/OnCE Debug Programming Interface
1.1.2 Memory
• Harvard architecture permits as many as three simultaneous accesses to Program and Data memory
• On-chip memory including a low-cost, high-volume Flash solution
—31.5K
× 16-bit words of Program Flash
—512 × 16-bit words of Program RAM
—2K
× 16-bit words of Data Flash
—4K
× 16-bit words of Data RAM
—2K
× 16-bit words of BootFLASH
• Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states
— As much as 64K × 16-bit Data memory
— As much as 64K × 16-bit Program memory
1.1.3 Peripheral Circuits for 56F826
• One General Purpose Quad Timer totalling 7 pins
• One Serial Peripheral Interface with 4 pins (or four additional GPIO lines)
• One Serial Peripheral Interface, or multiplexed with two Serial Communications Interfaces
totalling 4 pins
• Synchronous Serial Interface (SSI) with configurable six-pin port (or six additional GPIO lines)
56F826 Description
56F826 Technical Data, Rev. 14
Freescale Semiconductor 5
• Sixteen (16) dedicated General Purpose I/O (GPIO) pins
• Thirty (30) shared General Purpose I/O (GPIO) pins
• Computer-Operating Properly (COP) Watchdog timer
• Two external interrupt pins
• External reset pin for hardware reset
• JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugging
• Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock
• Fabricated in high-density EMOS with 5V-tolerant, TTL-compatible digital inputs
• One Time of Day module
1.1.4 Energy Information
• Dual power supply, 3.3V and 2.5V
• Wait and Multiple Stop modes available
1.2 56F826 Description
The 56F826 is a member of the 56800 core-based family of processors. It combines, on a single chip, the
processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to
create an extremely cost-effective solution for general purpose applications. Because of its low cost,
configuration flexibility, and compact program code, the 56F826 is well-suited for many applications.
The 56F826 includes many peripherals that are especially useful for applications such as: noise
suppression, ID tag readers, sonic/subsonic detectors, security access devices, remote metering, sonic
alarms, POS terminals, feature phones.
The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The microprocessor-style programming
model and optimized instruction set allow straightforward generation of efficient, compact code for both
DSP and MCU applications. The instruction set is also highly efficient for C/C++ Compilers to enable
rapid development of optimized control applications.
The 56F826 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F826 also provides two external
dedicated interrupt lines, and up to 46 General Purpose Input/Output (GPIO) lines, depending on
peripheral configuration.
The 56F826 controller includes 31.5K words (16-bit) of Program Flash and 2K words of Data Flash (each
programmable through the JTAG port) with 512 words of Program RAM, and 4K words of Data RAM. It
also supports program execution from external memory.
The 56F826 incorporates a total of 2K words of Boot Flash for easy customer-inclusion of
field-programmable software routines that can be used to program the main Program and Data Flash
memory areas. Both Program and Data Flash memories can be independently bulk-erased or erased in page
sizes of 256 words. The Boot Flash memory can also be either bulk- or page-erased.
56F826 Technical Data, Rev. 14
6 Freescale Semiconductor
This controller also provides a full set of standard programmable peripherals including one Synchronous
Serial Interface (SSI), one Serial Peripheral Interface (SPI), the option to select a second SPI or two Serial
Communications Interfaces (SCIs), and one Quad Timer. The SSI, SPI, and Quad Timer can be used as
General Purpose Input/Outputs (GPIOs) if a timer function is not required.
1.3 Award-Winning Development Environment
• Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
component-based software application creation with an expert knowledge system.
• The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards
will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable
tools solution for easy, fast, and efficient development.
1.4 Product Documentation
The four documents listed in Table 1-1 are required for a complete description and proper design with the
56F826. Documentation is available from local Freescale distributors, Freescale Semiconductor sales
offices, Freescale Literature Distribution Centers, or online at www.freescale.com.
Table 1-1 56F826 Chip Documentation
Topic Description Order Number
56800E
Family Manual
Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set
56800EFM
DSP56F826/F827
User’s Manual
Detailed description of memory, peripherals, and
interfaces of the 56F826 and 56F827
DSP56F826-827UM
56F826
Technical Data Sheet
Electrical and timing specifications, pin descriptions,
and package descriptions (this document)
DSP56F826
56F826
Product Brief
Summary description and block diagram of the 56F826
core, memory, peripherals and interfaces
DSP56F826PB
56F826
Errata
Details any chip issues that might be present DSP56F826E
Data Sheet Conventions
56F826 Technical Data, Rev. 14
Freescale Semiconductor 7
1.5 Data Sheet Conventions
This data sheet uses the following conventions:
OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.
“asserted” A high true (active high) signal is high or a low true (active low) signal is low.
“deasserted” A high true (active high) signal is low or a low true (active low) signal is high.
Examples: Signal/Symbol Logic State Signal State Voltage1
1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
PIN True Asserted VIL/VOL
PIN False Deasserted VIH/VOH
PIN True Asserted VIH/VOH
PIN False Deasserted VIL/VOL
56F826 Technical Data, Rev. 14
8 Freescale Semiconductor
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56F826 are organized into functional groups, as shown in Table 2-1
and as illustrated in Figure 2-1. Table 2-1 describes the signal or signals present on a pin.
Table 2-1 Functional Group Pin Allocations
Functional Group Number of Pins
Power (VDD, VDDIO or VDDA) (3,4,1)
Ground (VSS, VSSIO or VSSA) (3,4,1)
PLL and Clock 3
Address Bus116
Data Bus116
Bus Control 4
Quad Timer Module Ports14
JTAG/On-Chip Emulation (OnCE) 6
Dedicated General Purpose Input/Output 16
Synchronous Serial Interface (SSI) Port16
Serial Peripheral Interface (SPI) Port1
1. Alternately, GPIO pins
4
Serial Communications Interface (SCI) Ports 4
Interrupt and Program Control 5
Introduction
56F826 Technical Data, Rev. 14
Freescale Semiconductor 9
Figure 2-1 56F826 Signals Identified by Functional Group1
1. Alternate pin functionality is shown in parentheses.
56F826
2.5V Power
3.3V Analog Power
3.3V Power
Ground
Analog Ground
Ground
PLL
and
Clock
External
Address Bus or
GPIO
External Data
Bus
External
Bus Control
Dedicated
GPIO
SPI1 Port
or GPIO
SCI0, SCI1
Port or
SPI0 Port
VDD
VDDA
VDDIO
VSS
VSSA
VSSIO
EXTAL
XTAL (CLOCKIN)
CLKO
A0-A7 (GPIOE)
A8-A15 (GPIOA)
D0–D15
PS
DS
RD
WR
TA0 (GPIOF0)
TA1 (GPIOF1)
TA2 (GPIOF2)
TA3 (GPIOF3)
TCK
TMS
TDI
TDO
TRST
DE
Quad Timer A
or GPIO
JTAG/OnCE™
Port
GPIOB0–7
GPIOD0–7
SRD (GPIOC0)
SRFS (GPIOC1)
SRCK (GPIOC2)
STD (GPIOC3)
STFS (GPIOC4)
STCK (GPIOC5)
SCLK (GPIOF4)
MOSI (GPIOF5)
MISO (GPIOF6)
SS (GPIOF7)
TXD0 (SCLK0)
RXD0 (MOSI0)
TXD1 (MISO0)
RXD1 (SS0)
IRQA
IRQB
RESET
EXTBOOT
SSI Port
or GPIO
3
1
4
4*
1
4
1
1
1
8
8
16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Interrupt/
Program
Control
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
*Includes TCS pin, which is reserved for factory use and is tied to VSS
56F826 Technical Data, Rev. 14
10 Freescale Semiconductor
2.2 Signals and Package Information
All inputs have a weak internal pull-up circuit associated with them. These pull-up circuits are always
enabled. Exceptions:
1. When a pin is owned by GPIO, then the pull-up may be disabled under software control.
2. TCK has a weak pull-down circuit always active.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP
Signal
Name Pin No. Type Description
VDD 20 VDD Power—These pins provide power to the internal structures of the chip, and are
generally connected to a 2.5V supply.
VDD 64 VDD
VDD 94 VDD
VDDA 59 VDDA Analog Power—This pin is a dedicated power pin for the analog portion of the
chip and should be connected to a low-noise 3.3V supply.
VDDIO 5V
DDIO Power In/Out—These pins provide power to the I/O structures of the chip, and
are generally connected to a 3.3V supply.
VDDIO 30 VDDIO
VDDIO 57 VDDIO
VDDIO 80 VDDIO
VSS 19 VSS GND—These pins provide grounding for the internal structures of the chip. All
should be attached to VSS.
VSS 63 VSS
VSS 95 VSS
VSSA 60 VSSA Analog Ground—This pin supplies an analog ground.
VSSIO 6V
SSIO GND In/Out—These pins provide grounding for the I/O ring on the chip. All
should be attached to VSS.
VSSIO 31 VSSIO
VSSIO 58 VSSIO
VSSIO 81 VSSIO
TCS 99 Input/Output
(Schmitt)
TCS—This pin is reserved for factory use. It must be tied to VSS for normal use.
In block diagrams, this pin is considered an additional VSS.
EXTAL 61 Input External Crystal Oscillator Input—This input should be connected to a 4MHz
external crystal or ceramic resonator. For more information, please refer to
Section 3.6.
Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor 11
XTAL
(CLOCKIN)
62 Output
Input
Crystal Oscillator Output—This output connects the internal crystal oscillator
output to an external crystal or ceramic resonator. If an external clock source
over 4MHz is used, XTAL must be used as the input and EXTAL connected to
VSS. For more information, please refer to Section 3.6.3.
External Clock Input—This input should be asserted when using an external
clock or ceramic resonator.
CLKO 65 Output Clock Output—This pin outputs a buffered clock signal. By programming the
CLKO Select Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the device master clock at
the output of the PLL. The clock frequency on this pin can be disabled by
programming the CLKO Select Register (CLKOSR).
A0
(GPIOE0)
24 Output
Input/Output
Address Bus—A0–A7 specify the address for external program or data memory
accesses.
Port E GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
A1
(GPIOE1)
23
A2
(GPIOE2)
22
A3
(GPIOE3)
21
A4
(GPIOE4)
18
A5
(GPIOE5)
17
A6
(GPIOE6)
16
A7
(GPIOE7)
15
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
56F826 Technical Data, Rev. 14
12 Freescale Semiconductor
A8
(GPIOA0)
14 Output
Input/Output
Address Bus—A8–A15 specify the address for external program or data
memory accesses.
Port A GPIO—These eight General Purpose I/O (GPIO) pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
A9
(GPIOA1)
13
A10
(GPIOA2)
12
A11
(GPIOA3)
11
A12
(GPIOA4)
10
A13
(GPIOA5)
9
A14
(GPIOA6)
8
A15
(GPIOA7)
7
D0 34 Input/Output Data Bus— D0–D15 specify the data for external program or data memory
accesses. D0–D15 are tri-stated when the external bus is inactive.
D1 35
D2 36
D3 37
D4 38
D5 39
D6 40
D7 41
D8 42
D9 43
D10 44
D11 46
D12 47
D13 48
D14 49
D15 50
PS 29 Output Program Memory Select—PS is asserted low for external program memory
access.
DS 28 Output Data Memory Select—DS is asserted low for external data memory access.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor 13
RD 26 Output Read Enable—RD is asserted during external memory read cycles. When RD is
asserted low, pins D0–D15 become inputs and an external device is enabled
onto the device data bus. When RD is deasserted high, the external data is
latched inside the device. When RD is asserted, it qualifies the A0–A15, PS, and
DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM.
WR 27 Output Write Enable—WR is asserted during external memory write cycles. When WR
is asserted low, pins D0–D15 become outputs and the device puts data on the
bus. When WR is deasserted high, the external data is latched inside the
external device. When WR is asserted, it qualifies the A0–A15, PS, and DS pins.
WR can be connected directly to the WE pin of a Static RAM.
TA0
(GPIOF0)
91 Input/Output
Input/Output
TA0–3—Timer A Channels 0, 1, 2, and 3
Port F GPIO—These four General Purpose I/O (GPIO) pins can be individually
programmed as input or output.
After reset, the default state is Quad Timer.
TA1
(GPIOF1)
90
TA2
(GPIOF2)
89
TA3
(GPIOF3)
88
TCK 100 Input
(Schmitt)
Test Clock Input—This input pin provides a gated clock to synchronize the test
logic and shift serial data to the JTAG/OnCE port. The pin is connected internally
to a pull-down resistor.
TMS 1 Input
(Schmitt)
Test Mode Select Input—This input pin is used to sequence the JTAG TAP
controller’s state machine. It is sampled on the rising edge of TCK and has an
on-chip pull-up resistor.
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
TDI 2 Input
(Schmitt)
Test Data Input—This input pin provides a serial input data stream to the
JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip
pull-up resistor.
TDO 3 Output Test Data Output—This tri-statable output pin provides a serial output data
stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR
controller states, and changes on the falling edge of TCK.
TRST 4 Input
(Schmitt)
Test Reset—As an input, a low signal on this pin provides a reset signal to the
JTAG TAP controller. To ensure complete hardware reset, TRST should be
asserted whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is required and it is
necessary not to reset the JTAG/OnCE module. In this case, assert RESET, but
do not assert TRST. TRST must always be asserted at power-up.
Note: For normal operation, connect TRST directly to VSS. If the design is to be used
in a debugging environment, TRST may be tied to VSS through a 1K resistor.
DE 98 Output Debug Event—DE provides a low pulse on recognized debug events.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
56F826 Technical Data, Rev. 14
14 Freescale Semiconductor
GPIOB0 66 Input or
Output
Port B GPIO—These eight dedicated General Purpose I/O (GPIO) pins can be
individually programmed as input or output pins.
After reset, the default state is GPIO input.
GPIOB1 67
GPIOB2 68
GPIOB3 69
GPIOB4 70
GPIOB5 71
GPIOB6 72
GPIOB7 73
GPIOD0 74 Input or
Output
Port D GPIO—These eight dedicated GPIO pins can be individually
programmed as an input or output pins.
After reset, the default state is GPIO input.
GPIOD1 75
GPIOD2 76
GPIOD3 77
GPIOD4 78
GPIOD5 79
GPIOD6 82
GPIOD7 83
SRD
(GPIOC0)
51 Input/Output
Input/Output
SSI Receive Data (SRD)—This input pin receives serial data and transfers the
data to the SSI Receive Shift Receiver.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SRFS
(GPIOC1)
52 Input/ Output
Input/Output
SSI Serial Receive Frame Sync (SRFS)—This bidirectional pin is used by the
receive section of the SSI as frame sync I/O or flag I/O. The STFS can be used
only by the receiver. It is used to synchronize data transfer and can be an input
or an output.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor 15
SRCK
(GPIOC2)
53 Input/Output
Input/Output
SSI Serial Receive Clock (SRCK)—This bidirectional pin provides the serial bit
rate clock for the Receive section of the SSI. The clock signal can be continuous
or gated and can be used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STD
(GPIOC3)
54 Output
Input/Output
SSI Transmit Data (STD)—This output pin transmits serial data from the SSI
Transmitter Shift Register.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STFS
(GPIOC4)
55 Input
Input/Output
SSI Serial Transmit Frame Sync (STFS)—This bidirectional pin is used by the
Transmit section of the SSI as frame sync I/O or flag I/O. The STFS can be used
by both the transmitter and receiver in synchronous mode. It is used to
synchronize data transfer and can be an input or output pin.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
STCK
(GPIOC5)
56 Input/ Output
Input/Output
SSI Serial Transmit Clock (STCK)—This bidirectional pin provides the serial bit
rate clock for the transmit section of the SSI. The clock signal can be continuous
or gated. It can be used by both the transmitter and receiver in synchronous
mode.
Port C GPIO—This is a General Purpose I/O (GPIO) pin with the capability of
being individually programmed as input or output.
After reset, the default state is GPIO input.
SCLK
(GPIOF4)
84 Input/Output
Input/Output
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SCLK.
MOSI
(GPIOF5)
85 Input/Output
Input/Output
SPI Master Out/Slave In (MOSI)—This serial data pin is an output from a
master device and an input to a slave device. The master device places data on
the MOSI line a half-cycle before the clock edge that the slave device uses to
latch the data.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
56F826 Technical Data, Rev. 14
16 Freescale Semiconductor
MISO
(GPIOF6)
86 Input/Output
Input/Output
SPI Master In/Slave Out (MISO)—This serial data pin is an input to a master
device and an output from a slave device. The MISO line of a slave device is
placed in the high-impedance state if the slave device is not selected.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is MISO.
SS
(GPIOF7)
87 Input
Input/Output
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
Port F GPIO—This General Purpose I/O (GPIO) pin can be individually
programmed as input or output.
After reset, the default state is SS.
TXD0
(SCLK0)
97 Output
Input/Output
Transmit Data (TXD0)—transmit data output
SPI Serial Clock—In master mode, this pin serves as an output, clocking slaved
listeners. In slave mode, this pin serves as the data clock input.
After reset, the default state is SCI output.
RXD0
(MOSI0)
96 Input
Input/Output
Receive Data (RXD0)— receive data input
SPI Master Out/Slave In—This serial data pin is an output from a master
device, and an input to a slave device. The master device places data on the
MOSI line one half-cycle before the clock edge the slave device uses to latch the
data.
After reset, the default state is SCI input.
TXD1
(MISO0)
93 Output
Input/Output
Transmit Data (TXD1)—transmit data output
SPI Master In/Slave Out—This serial data pin is an input to a master device and
an output from a slave device. The MISO line of a slave device is placed in the
high-impedance state if the slave device is not selected.
After reset, the default state is SCI output.
RXD1
(SS0)
92 Input
(Schmitt)
Input
Receive Data (RXD1)— receive data input
SPI Slave Select—In master mode, this pin is used to arbitrate multiple masters.
In slave mode, this pin is used to select the slave.
After reset, the default state is SCI input.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
Signals and Package Information
56F826 Technical Data, Rev. 14
Freescale Semiconductor 17
IRQA 32 Input
(Schmitt)
External Interrupt Request A—The IRQA input is a synchronized external
interrupt request that indicates that an external device is requesting service. It
can be programmed to be level-sensitive or negative-edge-triggered. If
level-sensitive triggering is selected, an external pull-up resistor is required for
wired-OR operation.
If the processor is in the Stop state and IRQA is asserted, the processor will exit
the Stop state.
IRQB 33 Input
(Schmitt)
External Interrupt Request B—The IRQB input is an external interrupt request
that indicates that an external device is requesting service. It can be
programmed to be level-sensitive or negative-edge-triggered. If level-sensitive
triggering is selected, an external pull-up resistor is required for wired-OR
operation.
RESET 45 Input
(Schmitt)
Reset—This input is a direct hardware reset on the processor. When RESET is
asserted low, the device is initialized and placed in the Reset state. A Schmitt
trigger input is used for noise immunity. When the RESET pin is deasserted, the
initial chip operating mode is latched from the external boot pin. The internal
reset signal will be deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be asserted
together. The only exception occurs in a debugging environment when a
hardware device reset is required and it is necessary not to reset the
OnCE/JTAG module. In this case, assert RESET, but do not assert TRST.
EXTBOOT 25 Input
(Schmitt)
External Boot—This input is tied to VDD to force device to boot from off-chip
memory. Otherwise, it is tied to ground.
Table 2-1 56F826 Signal and Package Information for the 100 Pin LQFP (Continued)
Signal
Name Pin No. Type Description
56F826 Technical Data, Rev. 14
18 Freescale Semiconductor
Part 3 Specifications
3.1 General Characteristics
The 56F826 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
“5V-tolerant” refers to the capability of an I/O pin, built on a 3.3V-compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V- and 5V-compatible
I/O voltage levels. A standard 3.3V I/O is designed to receive a maximum voltage of 3.3V ± 10% during
normal operation without causing damage. This 5V-tolerant capability, therefore, offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56F826 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate voltage level.
General Characteristics
56F826 Technical Data, Rev. 14
Freescale Semiconductor 19
Table 3-1 Absolute Maximum Ratings
Characteristic Symbol Min Max Unit
Supply voltage, core VDD1VSS – 0.3 VSS + 3.0 V
Supply voltage, IO
Supply voltage, Analog
VDDIO2
VDDA2
VSSIO – 0.3
VSSA – 0.3
VSSIO + 4.0
VSSA + 4.0 V
Digital input voltages
Analog input voltages - XTAL, EXTAL
VIN
VINA
VSSIO – 0.3
VSSA – 0.3
VSSIO + 5.5
VDDA + 0.3 V
Voltage difference VDD to VDD_IO, VDDA ΔVDD - 0.3 0.3 V
Voltage difference VSS to VSS _IO, VSSA ΔVSS - 0.3 0.3 V
Current drain per pin excluding VDD, VSS, VDDA, VSSA,
VDDIO, VSSIO
I— 10
mA
Junction temperature TJ—150°C
Storage temperature range TSTG –55 150 °C
1. VDD must not exceed VDDIO
2. VDDIO and VDDA must not differ by more that 0.5V
Table 3-2 Recommended Operating Conditions
Characteristic Symbol Min Typ Max Unit
Supply voltage, core VDD 2.25 2.5 2.75 V
Supply Voltage, IO and analog VDDIO,VDDA 3.0 3.3 3.6 V
Voltage difference VDD to VDD_IO, VDDA ΔVDD -0.1 - 0.1 V
Voltage difference VSS to VSS _IO, VSSA ΔVSS -0.1 - 0.1 V
Ambient operating temperature TA–40 – 85 °C
56F826 Technical Data, Rev. 14
20 Freescale Semiconductor
Notes:
1. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.
2. Junction to ambient thermal resistance, Theta-JA (RθJA) was simulated to be equivalent to the JEDEC
specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on
a thermal test board with two internal planes (2s2p, where “s” is the number of signal layers and “p” is the
number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with
the non-single layer boards is Theta-JMA.
3. Junction to case thermal resistance, Theta-JC (RθJC), was simulated to be equivalent to the measured values
using the cold plate technique with the cold plate temperature used as the “case” temperature. The basic cold
plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal
metric to use to calculate thermal performance when the package is being used with a heat sink.
4. Thermal Characterization Parameter, Psi-JT (ΨJT), is the “resistance” from junction to reference point
thermocouple on top center of case as defined in JESD51-2. ΨJT is a useful value to use to estimate junction
temperature in steady state customer environments.
5. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
6. See Section 5.1 for more details on thermal design considerations.
7. TJ = Junction Temperature
TA = Ambient Temperature
Table 3-3 Thermal Characteristics6
Characteristic Comments Symbol
Value
Unit Notes
100-pin LQFP
Junction to ambient
Natural convection
RθJA 48.3 °C/W 2
Junction to ambient (@1m/sec) RθJMA 43.9 °C/W 2
Junction to ambient
Natural convection
Four layer board (2s2p) RθJMA
(2s2p)
40.7 °C/W 1.2
Junction to ambient (@1m/sec) Four layer board (2s2p) RθJMA 38.6 °C/W 1,2
Junction to case RθJC 13.5 °C/W 3
Junction to center of case ΨJT 1.0 °C/W 4, 5
I/O pin power dissipation P I/O User Determined W
Power dissipation P D P D = (IDD x VDD + P I/O)W
Junction to center of case PDMAX (TJ - TA) /RθJA W7
DC Electrical Characteristics
56F826 Technical Data, Rev. 14
Freescale Semiconductor 21
3.2 DC Electrical Characteristics
Table 3-4 DC Electrical Characteristics
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
Input high voltage (XTAL/EXTAL) VIHC 2.25 — 3.6 V
Input low voltage (XTAL/EXTAL) VILC 0—0.5V
Input high voltage (Schmitt trigger inputs)1VIHS 2.2 — 5.5 V
Input low voltage (Schmitt trigger inputs)1VILS -0.3 — 0.8 V
Input high voltage (all other digital inputs) VIH 2.0 — 5.5 V
Input low voltage (all other digital inputs) VIL -0.3 — 0.8 V
Input current high (pull-up/pull-down resistors disabled,
VIN=VDD)
IIH -1 — 1 μA
Input current low (pull-up/pull-down resistors disabled,
VIN=VSS)
IIL -1 — 1 μA
Input current high (with pull-up resistor, VIN=VDD)I
IHPU -1 — 1 μA
Input current low (with pull-up resistor, VIN=VSS)I
ILPU -210 — -50 μA
Input current high (with pull-down resistor, VIN=VDD)I
IHPD 20 — 180 μA
Input current low (with pull-down resistor, VIN=VSS)I
ILPD -1 — 1 μA
Nominal pull-up or pull-down resistor value RPU, RPD 30 KΩ
Output tri-state current low IOZL -10 — 10 μA
Output tri-state current high IOZH -10 — 10 μA
Input current high (analog inputs, VIN=VDDA)2IIHA -15 — 15 μA
Input current low (analog inputs, VIN=VSSA)2IILA -15 — 15 μA
Output High Voltage (at IOH) VOH VDD – 0.7 — — V
Output Low Voltage (at IOL) VOL ——0.4V
Output source current IOH 4——mA
Output sink current IOL 4——mA
PWM pin output source current3IOHP 10 — — mA
PWM pin output sink current4IOLP 16 — — mA
56F826 Technical Data, Rev. 14
22 Freescale Semiconductor
Input capacitance CIN —8—pF
Output capacitance COUT —12—pF
VDD supply current IDDT5
Run 6—4775mA
Wait7—2136mA
Stop —28mA
Low Voltage Interrupt, VDDIO power supply8VEIO 2.4 2.7 3.0 V
Low Voltage Interrupt, VDD power supply9VEIC 2.0 2.2 2.4 V
Power on Reset10 VPOR —1.72.0V
1.
1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, TCK, TRST, TMS, TDI and RXD1
2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.
3. PWM pin output source current measured with 50% duty cycle.
4. PWM pin output sink current measured with 50% duty cycle.
5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA)
6. Run (operating) IDD measured using 4MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as
inputs; measured with all modules enabled.
7. Wait IDD measured using external square wave clock source (fosc = 4MHz) into XTAL; all inputs 0.2V from rail; no DC loads;
less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD;
measured with PLL enabled.
8. This low-voltage interrupt monitors the VDDIO power supply. If VDDIO drops below VEIO, an interrupt is generated. Functionality
of the device is guaranteed under transient conditions when VDDIO >VEIO (between the minimum specified VDDIO and the point when
the VEIO interrupt is generated).
9. This low-voltage interrupt monitors theVDD power supply. If VDDIO drops below VEIC, an interrupt is generated. Functionality of
the device is guaranteed under transient conditions when VDD >VEIC (between the minimum specified VDD and the point when the
VEIC interrupt is generated).
10. Power–on reset occurs whenever the VDD power supply drops below VPOR. While power is ramping up, this signal remains
active for as long as VDD is below VPOR no matter how long the ramp-up rate is.
Table 3-4 DC Electrical Characteristics (Continued)
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
Supply Voltage Sequencing and Separation Cautions
56F826 Technical Data, Rev. 14
Freescale Semiconductor 23
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-4)
3.3 Supply Voltage Sequencing and Separation Cautions
Figure 3-2 shows two situations to avoid in sequencing the VDD and VDDIO, VDDA supplies.
Notes: 1. VDD rising before VDDIO, VDDA
2. VDDIO, VDDA rising much faster than VDD
Figure 3-2 Supply Voltage Sequencing and Separation Cautions
0
25
75
100
50
20 40 60 80
Freq. (MHz)
IDD (mA)
IDD Digital IDD Analog IDD Total
3.3V
2.5V
Time
0
2
1
Supplies Stable
VDD
VDDIO, VDDA
DC Power Supply Voltage
56F826 Technical Data, Rev. 14
24 Freescale Semiconductor
VDD should not be allowed to rise early (1). This is usually avoided by running the regulator for the VDD
supply (2.5V) from the voltage generated by the 3.3V VDDIO supply, see Figure 3-3. This keeps VDD from
rising faster than VDDIO.
VDD should not rise so late that a large voltage difference is allowed between the two supplies (2).
Typically this situation is avoided by using external discrete diodes in series between supplies, as shown
in Figure 3-3. The series diodes forward bias when the difference between VDDIO and VDD reaches
approximately 1.4, causing VDD to rise as VDDIO ramps up. When the VDD regulator begins proper
operation, the difference between supplies will typically be 0.8V and conduction through the diode chain
reduces to essentially leakage current. During supply sequencing, the following general relationship
should be adhered to:
VDDIO > VDD > (VDDIO - 1.4V)
In practice, VDDA is typically connected directly to VDDIO with some filtering.
Figure 3-3 Example Circuit to Control Supply Sequencing
3.4 AC Electrical Characteristics
Timing waveforms in Section 3.4 are tested using the VIL and VIH levels specified in the DC Characteristics
table. The levels of VIH and VIL for an input signal are shown in Figure 3-4.
Figure 3-4 Input Signal Measurement References
Figure 3-5 shows the definitions of the following signal states:
• Active state, when a bus or signal is driven, and enters a low impedance state
• Tri-stated, when a bus or signal is placed in a high impedance state
• Data Valid state, when a signal level has reached VOL or VOH
• Data Invalid state, when a signal level is in transition between VOL and VOH
3.3V
Regulator
2.5V
Regulator
Supply
VDD
VDDIO, VDDA
VIH
VIL
Fall Time
Input Signal
Note: The midpoint is VIL + (VIH – VIL)/2.
Midpoint1
Low High
Pulse Width
90%
50%
10%
Rise Time
Flash Memory Characteristics
56F826 Technical Data, Rev. 14
Freescale Semiconductor 25
Figure 3-5 Signal States
3.5 Flash Memory Characteristics
Table 3-5 Flash Memory Truth Table
Mode XE1
1. X address enable, all rows are disabled when XE = 0
YE2
2. Y address enable, YMUX is disabled when YE = 0
SE3
3. Sense amplifier enable
OE4
4. Output enable, tri-state Flash data out bus when OE = 0
PROG5
5. Defines program cycle
ERASE6
6. Defines erase cycle
MAS17
7. Defines mass erase cycle, erase whole block
NVSTR8
8. Defines non-volatile store cycle
Standby L L L L L L L L
Read HHHH L L L L
Word Program H H L L H L L H
Page Erase H L L L L H L H
Mass Erase H L L L L H H H
Table 3-6 IFREN Truth Table
Mode IFREN = 1 IFREN = 0
Read Read information block Read main memory block
Word program Program information block Program main memory block
Page erase Erase information block Erase main memory block
Mass erase Erase both block Erase main memory block
Data Invalid State
Data1
Data2 Valid
Data
Tri-stated
Data3 Valid
Data2 Data3
Data1 Valid
Data Active Data Active
56F826 Technical Data, Rev. 14
26 Freescale Semiconductor
Table 3-7 Flash Timing Parameters
Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic Symbol Min Typ Max Unit Figure
Program time Tprog* 20 – – us Figure 3-6
Erase time Terase* 20 – – ms Figure 3-7
Mass erase time Tme* 100 – – ms Figure 3-8
Endurance1
1. One cycle is equal to an erase program and read.
ECYC 10,000 20,000 – cycles
Data Retention1DRET 10 30 – years
The following parameters should only be used in the Manual Word Programming Mode
PROG/ERASE to NVSTR set
up time
Tnvs* –5–usFigure 3-6,
Figure 3-7,
Figure 3-8
NVSTR hold time Tnvh* –5–usFigure 3-6,
Figure 3-7
NVSTR hold time (mass erase) Tnvh1* –100–usFigure 3-8
NVSTR to program set up time Tpgs* –10–usFigure 3-6
Recovery time Trcv* –1–usFigure 3-6,
Figure 3-7,
Figure 3-8
Cumulative program
HV period2
2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be
programmed twice before next erase.
Thv –3–ms Figure 3-6
Program hold time3
3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.
*The Flash interface unit provides registers for the control of these parameters.
Tpgh ––– Figure 3-6
Address/data set up time3Tads ––– Figure 3-6
Address/data hold time3Tadh ––– Figure 3-6
Flash Memory Characteristics
56F826 Technical Data, Rev. 14
Freescale Semiconductor 27
Figure 3-6 Flash Program Cycle
Figure 3-7 Flash Erase Cycle
XADR
YADR
YE
DIN
PROG
NVSTR
Tnvs
Tpgs
Tadh
Tprog
Tads
Tpgh
Tnvh
Trcv
Thv
IFREN
XE
XADR
YE=SE=OE=MAS1=0
ERASE
NVSTR
Tnvs
Tnvh
Trcv
Terase
IFREN
XE
56F826 Technical Data, Rev. 14
28 Freescale Semiconductor
Figure 3-8 Flash Mass Erase Cycle
3.6 External Clock Operation
The 56F826 system clock can be derived from a crystal or an external system clock signal. To generate a
reference frequency using the internal oscillator, a reference crystal must be connected between the
EXTAL and XTAL pins.
3.6.1 Crystal Oscillator
The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in Table 3-9. A recommended crystal oscillator circuit
is shown in Figure 3-9. Follow the crystal supplier’s recommendations when selecting a crystal, because
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL
and XTAL pins to minimize output distortion and start-up stabilization time.The internal 56F82x
oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-9, no
external load capacitors should be used.
The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF
XADR
YE=SE=OE=0
ERASE
NVSTR
Tnvs
Tnvh1
Trcv
Tme
MAS1
IFREN
XE
External Clock Operation
56F826 Technical Data, Rev. 14
Freescale Semiconductor 29
as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:
This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.
Figure 3-9 Connecting to a Crystal Oscillator Circuit
3.6.2 Ceramic Resonator
It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. A typical ceramic resonator circuit is shown in
Figure 3-10. Refer to supplier’s recommendations when selecting a ceramic resonator and associated
components. The resonator and components should be mounted as close as possible to the EXTAL and
XTAL pins. The internal 56F82x oscillator circuitry is designed to have no external load capacitors
present. As shown in Figure 3-10, no external load capacitors should be used.
Figure 3-10 Connecting a Ceramic Resonator
Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators
(which contain an internal bypass capacitor to ground).
CL = CL1 * CL2
CL1 + CL2 + Cs = + 3 = 6 + 3 = 9pF
12 * 12
12 + 12
Recommended External Crystal
Parameters:
Rz = 1 to 3MΩ
fc = 4Mhz (optimized for 4MHz)
EXTAL XTAL
Rz
fc
Recommended Ceramic Resonator
Parameters:
Rz = 1 to 3 MΩ
fc = 4Mhz (optimized for 4MHz)
EXTAL XTAL
Rz
fc
56F826 Technical Data, Rev. 14
30 Freescale Semiconductor
3.6.3 External Clock Source
The recommended method of connecting an external clock is given in Figure 3-11. The external clock
source is connected to XTAL and the EXTAL pin is held VDDA/2.
Figure 3-11 Connecting an External Clock Signal
Figure 3-12 External Clock Timing
Table 3-8 External Clock Operation Timing Requirements
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
Frequency of operation (external clock driver)1
1. See Figure 3-11 for details on using the recommended connection of an external clock driver.
fosc 04
802
2. When using Time of Day (TOD), maximum external frequency is 6MHz.
MHz
Clock Pulse Width3, 4
3. The high or low pulse width must be no smaller than 6.25ns or the chip will not function.
4. Parameters listed are guaranteed by design.
tPW 6.25 — — ns
56F826
XTAL EXTAL
External VDDA/2
Clock
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10% tPW tPW
External Bus Asynchronous Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 31
3.6.4 Phase Locked Loop Timing
3.7 External Bus Asynchronous Timing
Table 3-9 PLL Timing
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL < 50pF, fop = 80MHz
Characteristic Symbol Min Typ Max Unit
External reference crystal frequency for the PLL1
1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work
correctly. The PLL is optimized for 4MHz input crystal.
fosc 246MHz
PLL output frequency2
2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the
User Manual. ZCLK = fop
fout/2 40 — 110 MHz
PLL stabilization time 3 -40o to +85oC
3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation.
tplls —110ms
Table 3-10 External Bus Asynchronous Timing1, 2
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Max Unit
Address Valid to WR Asserted tAWR 6.5 — ns
WR Width Asserted
Wait states = 0
Wait states > 0
tWR
7.5
(T*WS) + 7.5
—
—
ns
ns
WR Asserted to D0–D15 Out Valid tWRD —T + 4.2ns
Data Out Hold Time from WR Deasserted tDOH 4.8 — ns
Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0
tDOS
2.2
(T*WS) + 6.4
—
—
ns
ns
RD Deasserted to Address Not Valid tRDA 0—ns
Address Valid to RD Deasserted
Wait states = 0
Wait states > 0
tARDD
18.7
(T*WS) + 18.7
—
ns
ns
56F826 Technical Data, Rev. 14
32 Freescale Semiconductor
Input Data Hold to RD Deasserted tDRD 0—ns
RD Assertion Width
Wait states = 0
Wait states > 0
tRD
19
(T*WS) + 19
—
—
ns
ns
Address Valid to Input Data Valid
Wait states = 0
Wait states > 0
tAD
—
—
1
(T*WS) + 1
ns
ns
Address Valid to RD Asserted tARDA -4.4 — ns
RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0
tRDD
—
—
2.4
(T*WS) + 2.4
ns
ns
WR Deasserted to RD Asserted tWRRD 6.8 — ns
RD Deasserted to RD Asserted tRDRD 0—ns
WR Deasserted to WR Asserted tWRWR 14.1 — ns
RD Deasserted to WR Asserted tRDWR 12.8 — ns
1. Timing is both wait state- and frequency-dependent. In the formulas listed, WS = the number of wait states and
T = Clock Period. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
To calculate the required access time for an external memory for any frequency < 80Mhz, use this formula:
Top = Clock period @ desired operating frequency
WS = Number of wait states
Memory Access Time = (Top*WS) + (Top- 11.5)
Table 3-10 External Bus Asynchronous Timing1, 2 (Continued)
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Max Unit
External Bus Asynchronous Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 33
Figure 3-13 External Bus Asynchronous Timing
A0–A15,
PS, DS
(See Note)
WR
D0–D15
RD
Note: During read-modify-write instructions and internal instructions, the address lines do not change state.
Data InData Out
tAWR
tARDA
tARDD
tRDA
tRD
tRDRD
tRDWR
tWRWR tWR
tDOS
tWRD
tWRRD
tAD
tDOH
tDRD
tRDD
56F826 Technical Data, Rev. 14
34 Freescale Semiconductor
3.8 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 5
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
Characteristic Symbol Min Max Unit See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ —21nsFigure 3-14
Minimum RESET Assertion Duration2
OMR Bit 6 = 0
OMR Bit 6 = 1
2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
• After power-on reset
• When recovering from Stop state
tRA
275,000T
128T
—
—
ns
ns
Figure 3-14
RESET Deassertion to First External Address Output tRDA 33T 34T ns Figure 3-14
Edge-sensitive Interrupt Request Width tIRW 1.5T — ns Figure 3-15
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM 15T — ns Figure 3-16
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG 16T — ns Figure 3-16
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
tIRI 13T — ns Figure 3-17
IRQA Width Assertion to Recover from Stop State4
4. The interrupt instruction fetch is visible on the pins only in Mode 3.
5. Parameters listed are guaranteed by design.
tIW 2T — ns Figure 3-18
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
—
275,000T
12T
ns
ns
Figure 3-18
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
—
275,000T
12T
ns
ns
Figure 3-19
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
—
275,000T
12T
ns
ns
Figure 3-19
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 35
Figure 3-14 Asynchronous Reset Timing
Figure 3-15 External Interrupt Timing (Negative-Edge-Sensitive)
Figure 3-16 External Level-Sensitive Interrupt Timing
First Fetch
A0–A15,
D0–D15
PS, DS,
RD, WR
RESET
First Fetch
tRA
tRAZ tRDA
IRQA,
IRQB tIRW
A0–A15,
PS, DS,
RD, WR
IRQA,
IRQB
First Interrupt Instruction Execution
a) First Interrupt Instruction Execution
General
Purpose
I/O Pin
IRQA,
IRQB
b) General Purpose I/O
tIDM
tIG
56F826 Technical Data, Rev. 14
36 Freescale Semiconductor
Figure 3-17 Interrupt from Wait State Timing
Figure 3-18 Recovery from Stop State Using Asynchronous Interrupt Timing
Figure 3-19 Recovery from Stop State Using IRQA Interrupt Service
Instruction Fetch
IRQA,
IRQB
First Interrupt Vector
A0–A15,
PS, DS,
RD, WR
tIRI
Not IRQA Interrupt Vector
IRQA
A0–A15,
PS, DS,
RD, WR
First Instruction Fetch
tIW
tIF
Instruction Fetch
IRQA
A0–A15
PS, DS,
RD, WR
First IRQA Interrupt
tIRQ
tII
Serial Peripheral Interface (SPI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 37
3.9 Serial Peripheral Interface (SPI) Timing
Table 3-12 SPI Timing1
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. Parameters are guaranteed by design.
Characteristic Symbol Min Max Unit See Figure
Cycle time
Master
Slave
tC
50
25
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Enable lead time
Master
Slave
tELD
—
25
—
—
ns
ns
Figure 3-23
Enable lag time
Master
Slave
tELG
—
100
—
—
ns
ns
Figure 3-23
Clock (SCLK) high time
Master
Slave
tCH
24
12
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Clock (SCLK) low time
Master
Slave
tCL
24.1
12
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Data set-up time required for inputs
Master
Slave
tDS
20
0
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Data hold time required for inputs
Master
Slave
tDH
0
2
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Access time (time to data active from high-impedance state)
Slave
tA
4.8 15 ns
Figure 3-23
Disable time (hold time to high-impedance state)
Slave
tD
3.7 15.2 ns
Figure 3-23
Data Valid for outputs
Master
Slave (after enable edge)
tDV
—
—
4.5
20.4
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Data invalid
Master
Slave
tDI
0
0
—
—
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Rise time
Master
Slave
tR
—
—
11.5
10.0
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
Fall time
Master
Slave
tF
—
—
9.7
9.0
ns
ns
Figures
3-20, 3-21,
3-22, 3-23
56F826 Technical Data, Rev. 14
38 Freescale Semiconductor
Figure 3-20 SPI Master Timing (CPHA = 0)
Figure 3-21 SPI Master Timing (CPHA = 1)
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14–1 Master LSB out
SS
(Input) SS is held High on master
tR
tF
tF
tDI
tDS
tDI(ref)
tDV
tCH
tDH
tC
tR
tF
tR
tCL
tCH
tCL
SCLK (CPOL = 0)
(Output)
SCLK (CPOL = 1)
(Output)
MISO
(Input)
MOSI
(Output)
MSB in Bits 14–1 LSB in
Master MSB out Bits 14– 1 Master LSB out
SS
(Input) SS is held High on master
tC
tCL
tF
tDI
tDV(ref) tDV
tR
tDH
tDS
tR
tCH
tCH
tCL
tF
tR
tF
Serial Peripheral Interface (SPI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 39
Figure 3-22 SPI Slave Timing (CPHA = 0)
Figure 3-23 SPI Slave Timing (CPHA = 1)
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tELG
tF
tR
tC
tCL
tCH
tCL
tELD
tAtCH tRtF
tD
tDI
tDI
tDS
tDH
tDV
SCLK (CPOL = 0)
(Input)
SCLK (CPOL = 1)
(Input)
MISO
(Output)
MOSI
(Input)
Slave MSB out Bits 14–1
MSB in Bits 14–1 LSB in
SS
(Input)
Slave LSB out
tC
tCL
tDV
tA
tELD
tR
tF
tELG
tCH
tCL
tCH
tF
tDS tDV tDI
tDH
tD
tR
56F826 Technical Data, Rev. 14
40 Freescale Semiconductor
3.10 Synchronous Serial Interface (SSI) Timing
Table 3-13 SSI Master Mode1 Switching Characteristics
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. Master mode is internally generated clocks and frame syncs
Parameter Symbol Min Typ Max Units
STCK frequency fs 102
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
MHz
STCK period3tSCKW 100 — — ns
STCK high time tSCKH 504——ns
STCK low time tSCKL 504——ns
Output clock rise/fall time (STCK, SRCK) — 4—ns
Delay from STCK high to STFS (bl) high - Master5tTFSBHM 0.1 — 0.5 ns
Delay from STCK high to STFS (wl) high - Master5tTFSWHM 0.1 — 0.5 ns
Delay from SRCK high to SRFS (bl) high - Master5tRFSBHM 0.6 — 1.3 ns
Delay from SRCK high to SRFS (wl) high - Master5tRFSWHM 0.6 — 1.3 ns
Delay from STCK high to STFS (bl) low - Master5tTFSBLM -1.0 — -0.1 ns
Delay from STCK high to STFS (wl) low - Master5tTFSWLM -1.0 — -0.1 ns
Delay from SRCK high to SRFS (bl) low - Master5tRFSBLM -0.1 — 0 ns
Delay from SRCK high to SRFS (wl) low - Master5tRFSWLM -0.1 — 0 ns
STCK high to STXD enable from high impedance - Master tTXEM 20 — 22 ns
STCK high to STXD valid - Master tTXVM 24 — 26 ns
STCK high to STXD not valid - Master tTXNVM 0.1 — 0.2 ns
STCK high to STXD high impedance - Master tTXHIM 24 — 25.5 ns
SRXD Setup time before SRCK low - Master tSM 4—— ns
SRXD Hold time after SRCK low - Master tHM 4—— ns
Synchronous Operation (in addition to standard internal clock parameters)
SRXD Setup time before STCK low - Master tTSM 4——
SRXD Hold time after STCK low - Master tTHM 4——
Synchronous Serial Interface (SSI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 41
Figure 3-24 Master Mode Timing Diagram
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync have
been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS in the
tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
tTHM
tTSM
tHM
tSM
tRFSWLM
tRFSWHM
tRFBLM
tRFSBHM
tTXHIM
tTXNVM
tTXVM
tTXEM
tTFSWLM
tTFSWHM
tTFSBLM
tTFSBHM
tSCKL
tSCKW
tSCKH
First Bit Last Bit
STCK output
STFS (bl) output
STFS (wl) output
STXD
SRCK output
SRFS (bl) output
SRFS (wl) output
SRXD
56F826 Technical Data, Rev. 14
42 Freescale Semiconductor
Table 3-14 SSI Slave Mode1 Switching Characteristics
Operating Conditions: V
SSIO
= V
SS
= V
SSA
= 0V, V
DDA
= V
DDIO
= 3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Parameter Symbol Min Typ Max Units
STCK frequency fs — 102MHz
STCK period3tSCKW 100 — — ns
STCK high time tSCKH 504—— ns
STCK low time tSCKL 504—— ns
Output clock rise/fall time — TBD —ns
Delay from STCK high to STFS (bl) high - Slave5tTFSBHS 0.1 — 46 ns
Delay from STCK high to STFS (wl) high - Slave5tTFSWHS 0.1 — 46 ns
Delay from SRCK high to SRFS (bl) high - Slave5tRFSBHS 0.1 — 46 ns
Delay from SRCK high to SRFS (wl) high - Slave5tRFSWHS 0.1 — 46 ns
Delay from STCK high to STFS (bl) low - Slave5tTFSBLS -1 — — ns
Delay from STCK high to STFS (wl) low - Slave5tTFSWLS -1 — — ns
Delay from SRCK high to SRFS (bl) low - Slave5tRFSBLS -46 — — ns
Delay from SRCK high to SRFS (wl) low - Slave5tRFSWLS -46 — — ns
STCK high to STXD enable from high impedance - Slave tTXES —— ns
STCK high to STXD valid - Slave tTXVS 1—25 ns
STFS high to STXD enable from high impedance (first bit) -
Slave
tFTXES 5.5 — 25 ns
STFS high to STXD valid (first bit) - Slave tFTXVS 6—27 ns
STCK high to STXD not valid - Slave tTXNVS 11 — 13 ns
STCK high to STXD high impedance - Slave tTXHIS 11 — 28.5 ns
SRXD Setup time before SRCK low - Slave tSS 4—— ns
SRXD Hold time after SRCK low - Slave tHS 4—— ns
Synchronous Serial Interface (SSI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 43
Synchronous Operation (in addition to standard external clock parameters)
SRXD Setup time before STCK low - Slave tTSS 4——
SRXD Hold time after STCK low - Slave tTHS 4——
1. Slave mode is externally generated clocks and frame syncs
2. Max clock frequency is IP_clk/4 = 40MHz / 4 = 10MHz for an 80MHz part.
3. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP=0 in SCR2 and RSCKP=0 in SCSR)
and a non-inverted frame sync (TFSI=0 in SCR2 and RFSI=0 in SCSR). If the polarity of the clock and/or the frame sync
have been inverted, all the timings remain valid by inverting the clock signal STCK/SRCK and/or the frame sync STFS/SRFS
in the tables and in the figures.
4. 50% duty cycle
5. bl = bit length; wl = word length
Table 3-14 SSI Slave Mode1 Switching Characteristics
Operating Conditions: V
SSIO
= V
SS
= V
SSA
= 0V, V
DDA
= V
DDIO
= 3.0–3.6V, V
DD
= 2.25–2.75V, T
A
= –40
°
to +85
°
C, C
L
≤
50pF, f
op
= 80MHz
Parameter Symbol Min Typ Max Units
56F826 Technical Data, Rev. 14
44 Freescale Semiconductor
Figure 3-25 Slave Mode Clock Timing
3.11 Quad Timer Timing
Table 3-15 Timer Timing1, 2
Operating Conditions: VSSIO = VSS = VSSA = 0V, VDDA = VDDIO = 3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. In the formulas listed, T = clock cycle. For 80MHz operation, T = 12.5ns.
2. Parameters listed are guaranteed by design.
Characteristic Symbol Min Max Unit
Timer input period PIN 4T+6 — ns
Timer input high/low period PINHL 2T+3 — ns
Timer output period POUT 2T — ns
Timer output high/low period POUTHL 1T — ns
tTHS
tTSS
tHS
tSS
tRFSWLS
tRFSWHS
tRFBLS
tRFSBHS
tTXHIS
tTXNVS
tFTXVS
tTXVS
tFTXES
tTXES
tTFSWLS
tTFSWHS
tTFSBLS
tTFSBHS
tSCKL
tSCKW
tSCKH
First Bit Last Bit
STCK input
STFS (bl) input
STFS (wl) input
STXD
SRCK input
SRFS (bl) input
SRFS (wl) input
SRXD
Serial Communication Interface (SCI) Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 45
Figure 3-26 Quad Timer Timing
3.12 Serial Communication Interface (SCI) Timing
Figure 3-27 RXD Pulse Width
Table 3-16 SCI Timing4
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
Characteristic Symbol Min Max Unit
Baud Rate1
1. fMAX is the frequency of operation of the system clock in MHz.
BR — (fMAX*2.5)/(80) Mbps
RXD2 Pulse Width
2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.
RXDPW 0.965/BR 1.04/BR ns
TXD3 Pulse Width
3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.
4. Parameters listed are guaranteed by design.
TXDPW 0.965/BR 1.04/BR ns
Timer Inputs
Timer Outputs
PIN PINHL PINHL
POUT POUTHL POUTHL
RXD
SCI receive
data pin
(Input) RXDPW
56F826 Technical Data, Rev. 14
46 Freescale Semiconductor
Figure 3-28 TXD Pulse Width
3.13 JTAG Timing
Figure 3-29 Test Clock Input Timing Diagram
Table 3-17 JTAG Timing1, 3
Operating Conditions: VSSIO=VSS = VSSA = 0V, VDDA =VDDIO=3.0–3.6V, VDD = 2.25–2.75V, TA = –40° to +85°C, CL ≤ 50pF, fop = 80MHz
1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz
operation, T = 12.5ns.
Characteristic Symbol Min Max Unit
TCK frequency of operation2
2. TCK frequency of operation must be less than 1/8 the processor rate.
3. Parameters listed are guaranteed by design.
fOP DC 10 MHz
TCK cycle time tCY 100 — ns
TCK clock pulse width tPW 50 — ns
TMS, TDI data set-up time tDS 0.4 — ns
TMS, TDI data hold time tDH 1.2 — ns
TCK low to TDO data valid tDV — 26.6 ns
TCK low to TDO tri-state tTS — 23.5 ns
TRST assertion time tTRST 50 — ns
DE assertion time tDE 4T — ns
TXD
SCI receive
data pin
(Input) TXDPW
TCK
(Input)
VM
VIL
VM = VIL + (VIH – VIL)/2
VM
VIH
tPW
tCY
tPW
JTAG Timing
56F826 Technical Data, Rev. 14
Freescale Semiconductor 47
Figure 3-30 Test Access Port Timing Diagram
Figure 3-31 TRST Timing Diagram
Figure 3-32 OnCE—Debug Event
Input Data Valid
Output Data Valid
Output Data Valid
TCK
(Input)
TDI
(Input)
TDO
(Output)
TDO
(Output)
TDO
(Output)
TMS
tDV
tTS
tDV
tDS tDH
TRST
(Input) tTRST
DE
tDE
56F826 Technical Data, Rev. 14
48 Freescale Semiconductor
Part 4 Packaging
4.1 Package and Pin-Out Information 56F826
This section contains package and pin-out information for the 100-pin LQFP configuration of the 56F826.
Figure 4-1 Top View, 56F826 100-pin LQFP Package
PIN 1
PIN 26 PIN 51
PIN 76
TMS
TDI
TDO
TRST
VDDIO
VSSIO
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
VSS
VDD
A3
A2
A1
A0
EXTBOOT
ORIENTATION
MARK
RD
WR
DS
PS
VDDIO
VSSIO
IRQA
IRQB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
RESET
D11
D12
D13
D14
D15
GPIOD1
GPIOD0
GPIOB7
GPIOB6
GPIOB5
GPIOB4
GPIOB3
GPIOB2
GPIOB1
GPIOB0
CLKO
VDD
VSS
XTAL
EXTAL
VSSA
VDDA
VSSIO
VDDIO
STCK
STFS
STD
SRCK
SRFS
SRD
TCK
TCS
DE
TXD0
RXD0
VSS
VDD
TXD1
RXD1
TA0
TA1
TA2
TA3
SS
MISO
MOSI
SCLK
GPIOD7
GPIOD6
VSSIO
VDDIO
GPIOD5
GPIOD4
GPIOD3
GPIOD2
Package and Pin-Out Information 56F826
56F826 Technical Data, Rev. 14
Freescale Semiconductor 49
Table 4-1 56F826 Pin Identification by Pin Number
Pin No. Signal
Name Pin No. Signal Name Pin No. Signal Name Pin No. Signal
Name
1TMS26 RD 51 SRD 76 GPIOD2
2TDI27 WR 52 SRFS 77 GPIOD3
3 TDO 28 DS 53 SRCK 78 GPIOD4
4TRST
29 PS 54 STD 79 GPIOD5
5V
DDIO 30 VDDIO 55 STFS 80 VDDIO
6V
SSIO 31 VSSIO 56 STCK 81 VSSIO
7 A15 32 IRQA 57 VDDIO 82 GPIOD6
8 A14 33 IRQB 58 VSSIO 83 GPIOD7
9 A13 34 D0 59 VDDA 84 SCLK
10A1235D160 V
SSA 85 MOSI
11 A11 36 D2 61 EXTAL 86 MISO
12A1037D362XTAL87SS
13 A9 38 D4 63 VSS 88 TA3
14 A8 39 D5 64 VDD 89 TA2
15 A7 40 D6 65 CLKO 90 TA1
16 A6 41 D7 66 GPIOB0 91 TA0
17 A5 42 D8 67 GPIOB1 92 RXD1
18 A4 43 D9 68 GPIOB2 93 TXD1
19 VSS 44 D10 69GPIOB394V
DD
20 VDD 45 RESET 70 GPIOB4 95 VSS
21 A3 46 D11 71 GPIOB5 96 RXD0
22 A2 47 D12 72 GPIOB6 97 TXD0
23 A1 48 D13 73 GPIOB7 98 DE
24 A0 49 D14 74 GPIOD0 99 TCS
25 EXTBOOT 50 D15 75 GPIOD1 100 TCK
56F826 Technical Data, Rev. 14
50 Freescale Semiconductor
Figure 4-2 100-pin LQPF Mechanical Information
Please see www.freescale.com for the most current case outline.
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM
OF LEAD AND IS COINCIDENT WITH THE
LEAD WHERE THE LEAD EXITS THE PLASTIC
BODY AT THE BOTTOM OF THE PARTING
LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED
AT SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.250 (0.010) PER SIDE.
DIMENSIONS A AND B DO INCLUDE MOLD
MISMATCH AND ARE DETERMINED AT
DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.350 (0.014). DAMBAR CAN NOT BE LOCATED
ON THE LOWER RADIUS OR THE FOOT.
MINIMUM SPACE BETWEEN PROTRUSION
AND AN ADJACENT LEAD IS 0.070 (0.003).
8. MINIMUM SOLDER PLATE THICKNESS
SHALL BE 0.0076 (0.003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
AE
AE
AD
SEATING
(24X PER SIDE)
R
GAUGE PLANE
DETAIL AD
SECTION AE-AE
S
V
B
A
96X
X
E
C
K
HW
D
F
J
N
9
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A13.950 14.050 0.549 0.553
B13.950 14.050 0.549 0.553
C1.400 1.600 0.055 0.063
D0.170 0.270 0.007 0.011
E1.350 1.450 0.053 0.057
F0.170 0.230 0.007 0.009
G0.500 BSC 0.020 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
Q1 5 1 5
R0.150 0.250 0.006 0.010
S15.950 16.050 0.628 0.632
V15.950 16.050 0.628 0.632
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
°°
°°°°
CASE 842F-01
-T-
S
T-U
S
0.15(0.006) Z S
AC
S
T-U
S
0.15(0.006) Z S
AC
S
T-U
S
0.15(0.006) Z S
AC
-U-
S
T-U
S
0.15(0.006) Z S
AB
-Z-
-AC-
G
PLANE
-AB-
S
T-U
M
0.20(0.008) Z S
AC
0.100(0.004) AC
Q°
M°
0.25 (0.010)
Thermal Design Considerations
56F826 Technical Data, Rev. 14
Freescale Semiconductor 51
Part 5 Design Considerations
5.1 Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the equation:
Equation 1:
Where:
TA = ambient temperature °C
RθJA = package junction-to-ambient thermal resistance °C/W
PD = power dissipation in package
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:
Equation 2:
Where:
RθJA = package junction-to-ambient thermal resistance °C/W
RθJC = package junction-to-case thermal resistance °C/W
RθCA = package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case-to-ambient thermal resistance, RθCA. For example, the user can change the air flow around
the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where
the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the
device thermal performance may need the additional modeling capability of a system-level thermal
simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which
the package is mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether
the thermal performance is adequate, a system-level model may be appropriate.
Definitions:
A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:
• Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the
chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation
across the surface.
• Measure the thermal resistance from the junction to where the leads are attached to the case. This definition
is approximately equal to a junction-to-board thermal resistance.
TJTAPDRθJA
×()+=
RθJA RθJC RθCA
+=
56F826 Technical Data, Rev. 14
52 Freescale Semiconductor
• Use the value obtained by the equation (TJ – TT)/PD, where TT is the temperature of the package case
determined by a thermocouple.
The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back-calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction-to-case
thermal resistance.
5.2 Electrical Design Considerations
Use the following list of considerations to assure correct operation:
• Provide a low-impedance path from the board power supply to each VDD, VDDIO, and VDDA pin on the
controller, and from the board ground to each VSS,VSSIO, and VSSA (GND) pin.
• The minimum bypass requirement is to place 0.1μF capacitors positioned as close as possible to the package
supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the
VDD/VSS pairs, including VDDA/VSSA and VDDIO/VSSIO. Ceramic and tantalum capacitors tend to provide
better performance tolerances.
• Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD, VDDIO, and
VDDA and VSS, VSSIO, and VSSA (GND) pins are less than 0.5 inch per capacitor lead.
• Bypass the VDD and VSS layers of the PCB with approximately 100μF, preferably with a high-grade
capacitor such as a tantalum capacitor.
CAUTION
This device contains protective circuitry to guard
against damage due to high static voltage or
electrical fields. However, normal precautions are
advised to avoid application of any voltages higher
than maximum-rated voltages to this high-impedance
circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate voltage level.
Electrical Design Considerations
56F826 Technical Data, Rev. 14
Freescale Semiconductor 53
• Because the controller’s output signals have fast rise and fall times, PCB trace lengths should be minimal.
• Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance.
This is especially critical in systems with higher capacitive loads that could create higher transient currents
in the VDD and VSS circuits.
• Take special care to minimize noise levels on the VREF, VDDA and VSSA pins.
• When using Wired-OR mode on the SPI or the IRQx pins, the user must provide an external pull-up device.
• Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or
debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means
to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs
that do not require debugging functionality, such as consumer products, TRST should be tied low.
• Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an
interface to this port to allow in-circuit Flash programming.
56F826 Technical Data, Rev. 14
54 Freescale Semiconductor
Part 6 Ordering Information
Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor
sales office or authorized distributor to determine availability and to order parts.
*This package is RoHS compliant.
Table 6-1 56F826 Ordering Information
Part Supply
Voltage Package Type Pin
Count
Ambient
Frequency
(MHz)
Order Number
56F826 3.0–3.6 V
2.25-2.75 V
Plastic Quad Flat Pack (LQFP) 100 80 DSP56F826BU80
56F826 3.0–3.6 V
2.25-2.75 V
Plastic Quad Flat Pack (LQFP) 100 80 DSP56F826BU80E *
Electrical Design Considerations
56F826 Technical Data, Rev. 14
Freescale Semiconductor 55
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This product incorporates SuperFlash® technology licensed from SST.
© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56F826
Rev. 14
01/2007
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