STM32H743IIK6 - STMICROELECTRONICS

This is information on a product in full production.

October 2017 DocID030538 Rev 3 1/226

STM32H743xI

32-bit Arm® Cortex®-M7 400MHz MCUs, up to 2MB Flash,

1MB RAM, 46 com. and analog interfaces

Datasheet - production data

Features

Core

•32-bit Arm® Cortex®-M7 core with double-

precision FPU and L1 cache: 16 Kbytes of data

and 16 Kbytes of instruction cache allowing

one cache line to be filled in a single access

from the 256-bit embedded Flash memory;

frequency up to 400 MHz, MPU, 856 DMIPS/

2.14 DMIPS/MHz (Dhrystone 2.1), and DSP

instructions

Memories

•Up to 2 Mbytes of Flash memory with read-

while-write support

•1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.

64 Kbytes of ITCM RAM + 128 Kbytes of

DTCM RAM for time critical routines),

864 Kbytes of user SRAM, and 4 Kbytes of

SRAM in Backup domain

•Dual mode Quad-SPI memory interface

running up to 133 MHz

•Flexible external memory controller with up to

32-bit data bus: SRAM, PSRAM,

SDRAM/LPSDR SDRAM, NOR/NAND Flash

clocked up to 133 MHz in synchronous mode

•CRC calculation unit

Security

•ROP, PC-ROP, active tamper

General-purpose input/outputs

•Up to 168 I/O ports with interrupt capability

– Fast I/Os capable of up to 133 MHz

– Up to 164 5 V-tolerant I/Os

Reset and power management

•3 separate power domains which can be

independently clock gated or switched off to

maximize power efficiency:

– D1: high-performance capabilities for high

bandwidth peripherals

– D2: communication peripherals and timers

– D3: reset/clock control/power management

•1.62 to 3.6 V application supply and I/Os

•POR, PDR, PVD and BOR

•Dedicated USB power embedding a 3.3 V

internal regulator to supply the internal PHYs

•Embedded regulator (LDO) with configurable

scalable output to supply the digital circuitry

•Voltage scaling in Run and Stop mode (5

configurable ranges)

•Backup regulator (~0.9 V)

•Voltage reference for analog peripheral/VREF+

•Low-power modes: Sleep, Stop, Standby and

VBAT supporting battery charging

Low-power consumption

•Total current consumption down to 4

µA

Clock management

•Internal oscillators: 64 MHz HSI, 48 MHz

HSI48, 4 MHz CSI, 40 kHz LSI

•External oscillators: 4-48 MHz HSE,

32.768 kHz LSE

•3× PLLs (1 for the system clock, 2 for kernel

clocks) with fractional mode

FBGA

LQFP208

(28x28 mm)

LQFP176

(24x24 mm)

LQFP144

(20x20 mm)

LQFP100

(14x14 mm)

UFBGA176+25 (10x10 mm)

UFBGA169 (7x7 mm)(1)

FBGA

TFBGA240+25 (14x14 mm)

TFBGA100 (8x8 mm)(1)

1. Package under development.

www.st.com

STM32H743xI

2/226 DocID030538 Rev 3

Interconnect matrix

•3 bus matrices (1 AXI and 2 AHB)

•Bridges (5× AHB2-APB, 2× AXI2-AHB)

4 DMA controllers to unload the CPU

•1× high-speed general-purpose master direct

memory access controller (MDMA) with linked

list support

•2× dual-port DMAs with FIFO and request

router capabilities

•1× basic DMA with request router capabilities

Up to 35 communication peripherals

•4× I2C FM+ interfaces (SMBus/PMBus)

•4× USART/4x UARTs (ISO7816 interface, LIN,

IrDA, modem control, up to 12.5 Mbit/s) and

1x LPUART

•6× SPIs, including 3 with muxed duplex I2S

audio class accuracy via internal audio PLL or

external clock, 1x I2S in LP domain (up to

133 MHz)

•4x SAIs (serial audio interface)

•SPDIFRX interface

•SWPMI single-wire protocol master I/F

•MDIO Slave interface

•2× SD/SDIO/MMC interfaces (up to 125 MHz)

•2× CAN controllers: 2 with CAN FD, 1 with

time-triggered CAN (TT-CAN)

•2× USB OTG interfaces (1FS, 1HS/FS)

•Ethernet MAC interface with DMA controller

•HDMI-CEC

•8- to 14-bit camera interface (up to 80 MHz)

11 analog peripherals

•3× ADCs with 16-bit max. resolution (14 bits

4 MSPS, 16 bits 3.6 MSPS)

•1× temperature sensor

•2× 12-bit D/A converters (1 MHz)

•2× ultra-low-power comparators

•2× operational amplifiers (8 MHz bandwidth)

•1× digital filters for sigma delta modulator

(DFSDM) with 8 channels/4 filters

Graphics

•LCD-TFT controller up to XGA resolution

•Chrom-ART graphical hardware Accelerator™

(DMA2D) to reduce CPU load

•Hardware JPEG Codec

Up to 22 timers and watchdogs

•1× high-resolution timer (2.5 ns max

resolution)

•2× 32-bit timers with up to 4 IC/OC/PWM or

pulse counter and quadrature (incremental)

encoder input (up to 200 MHz)

•2× 16-bit advanced motor control timers (up to

200 MHz)

•10× 16-bit general-purpose timers (up to

200 MHz)

•5× 16-bit low-power timers (up to 200 MHz)

•2× watchdogs (independent and window)

•1× SysTick timer

•RTC with sub-second accuracy & HW calendar

Debug mode

•SWD & JTAG interfaces

•4 Kbyte Embedded Trace Buffer

True random number generators (3

oscillators each)

96-bit unique ID

All packages are ECOPACK®2 compliant

Table 1. Device summary

Reference Part number

STM32H743xI STM32H743VI, STM32H743ZI, STM32H743II, STM32H743BI, STM32H743XI,

STM32H743AI

DocID030538 Rev 3 3/226
STM32H743xI Contents
6
Contents
Introduction  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1 Arm® Cortex®-M7 with FPU  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
2 Memory protection unit (MPU)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
3 Memories  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
3.1 Embedded Flash memory  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Embedded SRAM   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 Boot modes   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
5 Power supply management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
5.1 Power supply scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.2 Power supply supervisor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 Voltage regulator  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6 Low-power strategy  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  21
7 Reset and clock controller (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  22
7.1 Clock management  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 System reset sources   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
8 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . .  23
9 Bus-interconnect matrix  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  24
10 DMA controllers  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
11 Chrom-ART Accelerator™ (DMA2D)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  26
12 Nested vectored interrupt controller (NVIC)  . . . . . . . . . . . . . . . . . . . . . . .  27
13 Extended interrupt and event controller (EXTI)  . . . . . . . . . . . . . . . . . . . .  27
14 Cyclic redundancy check calculation unit (CRC)  . . . . . . . . . . . . . . . . . . .  27
15 Flexible memory controller (FMC)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
16 Quad-SPI memory interface (QUADSPI)  . . . . . . . . . . . . . . . . . . . . . . . . .  28
17 Analog-to-digital converters (ADCs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  28
18 Temperature sensor  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
19 VBAT operation  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  29
20 Digital-to-analog converters (DAC)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30

Contents STM32H743xI
4/226 DocID030538 Rev 3
21 Ultra-low-power comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
22 Operational amplifiers (OPAMP)   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  30
23 Digital filter for sigma-delta modulators (DFSDM)  . . . . . . . . . . . . . . . . . .  31
24 Digital camera interface (DCMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  32
25 LCD-TFT controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
26 JPEG Codec (JPEG)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
27 Random number generator (RNG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
28 Timers and watchdogs  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  33
28.1 High-resolution timer (HRTIM1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
28.2 Advanced-control timers (TIM1, TIM8)   . . . . . . . . . . . . . . . . . . . . . . . . . 36
28.3 General-purpose timers (TIMx)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
28.4 Basic timers TIM6 and TIM7   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
28.5 Low-power timers (LPTIM1, LPTIM2, LPTIM3, LPTIM4, LPTIM5)   . . . . 37
28.6 Independent watchdog   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
28.7 Window watchdog  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
28.8 SysTick timer  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
29 Real-time clock (RTC), backup SRAM and backup registers . . . . . . . . . .  38
30 Inter-integrated circuit interface (I2C)  . . . . . . . . . . . . . . . . . . . . . . . . . . . .  39
31 Universal synchronous/asynchronous receiver transmitter (USART)   . . .  39
32 Low-power universal asynchronous receiver transmitter (LPUART)  . . . .  40
33 Serial peripheral interface (SPI)/inter- integrated sound interfaces (I2S) .  41
34 Serial audio interfaces (SAI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  41
35 SPDIFRX Receiver Interface (SPDIFRX) . . . . . . . . . . . . . . . . . . . . . . . . .  42
36 Single wire protocol master interface (SWPMI)  . . . . . . . . . . . . . . . . . . . .  42
37 Management Data Input/Output (MDIO) slaves . . . . . . . . . . . . . . . . . . . .  43
38 SD/SDIO/MMC card host interfaces (SDMMC)  . . . . . . . . . . . . . . . . . . . .  43
39 Controller area network (FDCAN1, FDCAN2)  . . . . . . . . . . . . . . . . . . . . .  43
40 Universal serial bus on-the-go high-speed (OTG_HS) . . . . . . . . . . . . . . .  44
41 Ethernet MAC interface with dedicated DMA controller (ETH) . . . . . . . . .  44
42 High-definition multimedia interface (HDMI)  
- consumer electronics control (CEC)   . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
43 Debug infrastructure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  45
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DocID030538 Rev 3 5/226
STM32H743xI Contents
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Pin descriptions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1 Parameter conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  94
1.1 Minimum and maximum values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.2 Typical values   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.3 Typical curves   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.4 Loading capacitor   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.5 Pin input voltage   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
1.6 Power supply scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
1.7 Current consumption measurement   . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  96
3 Operating conditions   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  98
3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.2 VCAP1/VCAP2/VCAP3 external capacitor   . . . . . . . . . . . . . . . . . . . . . . 99
3.3 Operating conditions at power-up / power-down  . . . . . . . . . . . . . . . . . . 99
3.4 Embedded reset and power control block characteristics  . . . . . . . . . . 100
3.5 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
3.6 Supply current characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
3.7 Wakeup time from low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 115
3.8 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 116
3.9 Internal clock source characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . 120
3.10 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
3.11 Memory characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3.13 Absolute maximum ratings (electrical sensitivity)   . . . . . . . . . . . . . . . . 126
3.14 I/O current injection characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.15 I/O port characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
3.16 NRST pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
3.17 FMC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3.18 Quad-SPI interface characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
3.19 Delay block (DLYB) characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.20 16-bit ADC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3.21 DAC electrical characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
3.22 Voltage reference buffer characteristics   . . . . . . . . . . . . . . . . . . . . . . . 166
3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
3.24 VBAT monitoring characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

Contents STM32H743xI
6/226 DocID030538 Rev 3
3.25 Voltage booster for analog switch  . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
3.26 Comparator characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
3.27 Operational amplifiers characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . 170
3.28 Digital filter for Sigma-Delta Modulators (DFSDM) characteristics   . . . 173
3.29 Camera interface (DCMI) timing specifications  . . . . . . . . . . . . . . . . . . 176
3.30 LCD-TFT controller (LTDC) characteristics  . . . . . . . . . . . . . . . . . . . . . 177
3.31 Timer characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
3.32 Communications interfaces  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
3.33 JTAG/SWD interface characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
1 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  197
2 TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array 
package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  201
3 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  204
4 UFBGA169 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  208
5 LQFP176 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  209
6 LQFP208 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  213
7 UFBGA176+25 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . .  217
8 TFBGA240+25 package information  . . . . . . . . . . . . . . . . . . . . . . . . . . .  220
9 Thermal characteristics   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  223
9.1 Reference document  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Ordering information   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Revision history   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

DocID030538 Rev 3 7/226
STM32H743xI List of tables
9
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. STM32H743xI features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 3. System vs domain low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. DFSDM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 5. Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 6. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 8. STM32H743xI pin/ball definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 9. Port A alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 10. Port B alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 11. Port C alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 12. Port D alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 13. Port E alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 14. Port F alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 15. Port G alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 16. Port H alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 17. Port I alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 18. Port J alternate functions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 19. Port K alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 20. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 21. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 22. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 23. General operating conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 24. VCAP1/VCAP2/VCAP3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 25. Operating conditions at power-up / power-down (regulator ON)  . . . . . . . . . . . . . . . . . . . . 99
Table 26. Reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 27. Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Table 28. Internal reference voltage calibration values  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Table 29. Typical and maximum current consumption in Run mode, code with data processing 
running from ITCM, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 30. Typical and maximum current consumption in Run mode, code with data processing 
running from Flash memory, cache ON, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 31. Typical and maximum current consumption in Run mode, code with data processing 
running from Flash memory, cache OFF, regulator ON . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Table 32. Typical consumption in Run mode and corresponding performance  
versus code position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 33. Typical current consumption batch acquisition mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 34. Typical and maximum current consumption in Sleep mode, regulator ON. . . . . . . . . . . . 105
Table 35. Typical and maximum current consumption in Stop mode, regulator ON. . . . . . . . . . . . . 106
Table 36. Typical and maximum current consumption in Standby mode . . . . . . . . . . . . . . . . . . . . . 106
Table 37. Typical and maximum current consumption in VBAT mode . . . . . . . . . . . . . . . . . . . . . . . 107
Table 38. Peripheral current consumption in Run mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 39. Peripheral current consumption in Stop, Standby and VBAT mode . . . . . . . . . . . . . . . . . 114
Table 40. Low-power mode wakeup timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Table 41. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 42. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 43.  4-48 MHz HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 44. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

List of tables STM32H743xI
8/226 DocID030538 Rev 3
Table 45. HSI48 oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Table 46. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 47. CSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 48. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 49. Main PLL characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Table 50. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Table 51. Flash memory programming (single bank configuration nDBANK=1)  . . . . . . . . . . . . . . . 124
Table 52. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 53. EMS characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Table 54. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 55. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Table 56. Electrical sensitivities  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 57. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Table 58. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 59. Output voltage characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Table 60. Output timing characteristics (HSLV OFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 61. Output timing characteristics (HSLV ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Table 62. NRST pin characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 63. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings  . . . . . . . . . . . . . . . . . 137
Table 64. Asynchronous non-multiplexed SRAM/PSRAM/NOR read - NWAIT timings . . . . . . . . . . 137
Table 65. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . 138
Table 66. Asynchronous non-multiplexed SRAM/PSRAM/NOR write - NWAIT timings. . . . . . . . . . 139
Table 67. Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Table 68. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . 140
Table 69. Asynchronous multiplexed PSRAM/NOR write timings  . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Table 70. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 142
Table 71. Synchronous multiplexed NOR/PSRAM read timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 72. Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 73. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 147
Table 74. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Table 75. Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 76. Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Table 77. SDRAM read timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Table 78. LPSDR SDRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 79. SDRAM write timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 80. LPSDR SDRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 81. Quad-SPI characteristics in SDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 82. Quad SPI characteristics in DDR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 83. Dynamics characteristics: Delay Block characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 84. ADC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 85. ADC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Table 86. DAC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Table 87. DAC accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 88. VREFBUF characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Table 89. Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 90. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Table 91. VBAT monitoring characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 92. VBAT charging characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 93. Voltage booster for analog switch characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
Table 94. COMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 95. OPAMP characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 96. DFSDM measured timing 1.62-3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173

DocID030538 Rev 3 9/226
STM32H743xI List of tables
9
Table 97. DCMI characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Table 98. LTDC characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 99. TIMx characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 100. Minimum i2c_ker_ck frequency in all I2C modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 101. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 102. SPI dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 103. I2S dynamic characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Table 104. SAI characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Table 105. MDIO Slave timing parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Table 106. Dynamic characteristics: SD / MMC characteristics, VDD=2.7V to 3.6V . . . . . . . . . . . . . 188
Table 107. Dynamic characteristics: eMMC characteristics, VDD=1.71V to 1.9V . . . . . . . . . . . . . . . 189
Table 108. USB OTG_FS electrical characteristics  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 109. Dynamic characteristics: USB ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Table 110. Dynamics characteristics: Ethernet MAC signals for SMI. . . . . . . . . . . . . . . . . . . . . . . . . 192
Table 111. Dynamics characteristics: Ethernet MAC signals for RMII . . . . . . . . . . . . . . . . . . . . . . . . 193
Table 112. Dynamics characteristics: Ethernet MAC signals for MII  . . . . . . . . . . . . . . . . . . . . . . . . . 194
Table 113. Dynamics characteristics: JTAG characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 114. Dynamics characteristics: SWD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 115. LQPF100 - 100-pin, 14 x 14 mm low-profile quad flat package  
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 116. TFBGA100, 8 x 8 × 0.8 mm thin fine-pitch ball grid array 
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 117. TFBGA100 recommended PCB design rules (0.8 mm pitch BGA). . . . . . . . . . . . . . . . . . 203
Table 118. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package  
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 119. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball 
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 120. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package  
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 121. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package  
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
Table 122. UFBGA176+25 - ball, 10 x 10 mm, 0.65 mm  pitch,  
ultra fine pitch ball grid array package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . 217
Table 123. UFBGA 176+25 recommended PCB design rules (0.65 mm  pitch BGA)  . . . . . . . . . . . . 218
Table 124. TFBGA240+25 - 265 pin, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array 
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 125. TFBGA240+25, 265 pin recommended PCB design rules (0.8 mm pitch) . . . . . . . . . . . . 222
Table 126. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Table 127. STM32H743xI ordering information scheme  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224
Table 128. Document revision history  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

List of figures STM32H743xI
10/226 DocID030538 Rev 3
List of figures
Figure 1. STM32H743xI block diagram   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 2. STM32H743xI bus matrix   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 3. LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Figure 4. TFBGA100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 5. LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 6. UFBGA169 ballout  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 7. LQFP176 pinout   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 8. UFBGA176+25 ballout   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 9. LQFP208 pinout   . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10. TFBGA240+25 ballout    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 12. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 13. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 14. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Figure 15. External capacitor CEXT  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 16. High-speed external clock source AC timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Figure 17. Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Figure 18. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 19. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 20. VIL/VIH for all I/Os except BOOT0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 21. Recommended NRST pin protection  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Figure 22. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . 136
Figure 23. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . 138
Figure 24. Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . 139
Figure 25. Asynchronous multiplexed PSRAM/NOR write waveforms  . . . . . . . . . . . . . . . . . . . . . . . 141
Figure 26. Synchronous multiplexed NOR/PSRAM read timings  . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Figure 27. Synchronous multiplexed PSRAM write timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Figure 28. Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 147
Figure 29. Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Figure 30. NAND controller waveforms for read access  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Figure 31. NAND controller waveforms for write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Figure 32. NAND controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . 150
Figure 33. NAND controller waveforms for common memory write access. . . . . . . . . . . . . . . . . . . . 151
Figure 34. SDRAM read access waveforms (CL = 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Figure 35. SDRAM write access waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Figure 36. Quad-SPI timing diagram - SDR mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 37. Quad-SPI timing diagram - DDR mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Figure 38. ADC accuracy characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Figure 39. Typical connection diagram using the ADC  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 40. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 162
Figure 41. Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . 162
Figure 42. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Figure 43. Channel transceiver timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Figure 44. DCMI timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Figure 45. LCD-TFT horizontal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 46. LCD-TFT vertical timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Figure 47. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 48. SPI timing diagram - slave mode and CPHA = 1(1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

DocID030538 Rev 3 11/226
STM32H743xI List of figures
11
Figure 49. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 50. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 51. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Figure 52. SAI master timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 53. SAI slave timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Figure 54. MDIO Slave timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Figure 55. SDIO high-speed mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 56. SD default mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 57. DDR mode  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Figure 58. ULPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192
Figure 59. Ethernet SMI timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 60. Ethernet RMII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Figure 61. Ethernet MII timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 62. JTAG timing diagram  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 63. SWD timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 64. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat package outline  . . . . . . . . . . . . . . 197
Figure 65. LQFP100 - 100-pin, 14 x 14 mm low-profile quad flat  
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 66. LQFP100 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 67. TFBGA100, 8 × 8 × 0.8 mm thin fine-pitch ball grid array 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 68. TFBGA100, 8 x 8 x 0.8 mm thin fine-pitch ball grid array 
package recommended footprint  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 69. TFBGA100 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Figure 70. LQFP144 - 144-pin, 20 x 20 mm low-profile quad flat package outline  . . . . . . . . . . . . . . 204
Figure 71. LQFP144 - 144-pin,20 x 20 mm low-profile quad flat package  
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Figure 72. LQFP144 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 73. UFBGA169 - 169-pin, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid 
array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 74. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package outline  . . . . . . . . . . . . . . 209
Figure 75. LQFP176 - 176-pin, 24 x 24 mm low profile quad flat package  
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Figure 76. LQFP176 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Figure 77. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package outline  . . . . . . . . . . . . . . 213
Figure 78. LQFP208 - 208-pin, 28 x 28 mm low-profile quad flat package  
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
Figure 79. LQFP208 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216
Figure 80. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch,  
ultra fine pitch ball grid array package outline  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217
Figure 81. UFBGA176+25 - 201-ball, 10 x 10 mm, 0.65 mm pitch, ultra fine pitch ball 
grid array package recommended footprint  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
Figure 82. UFBGA176+25 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . 219
Figure 83. TFBGA240+25 - 265 pin, 14x14 mm, 0.8 mm pitch, fine pitch ball grid array 
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Figure 84. TFBGA240+25 - 265 pin pin, 14x14 mm 0.8 mm pitch 
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Figure 85. TFBGA240+25 marking example (package top view)  . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Introduction STM32H743xI

12/226 DocID030538 Rev 3

1 Introduction

This datasheet provides the ordering information and mechanical device characteristics of

the STM32H743xI microcontrollers.

This document should be read in conjunction with the STM32H743xI reference manual

(RM0433). The reference manual is available from the STMicroelectronics website

www.st.com.

For information on the Arm® Cortex®-M7 core, please refer to the Cortex®-M7 Technical

Reference Manual, available from the www.arm.com website.

DocID030538 Rev 3 13/226

STM32H743xI Description

2 Description

STM32H743xI devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC

core operating at up to 400 MHz. The Cortex® -M7 core features a floating point unit (FPU)

which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-

processing instructions and data types. STM32H743xI devices support a full set of DSP

instructions and a memory protection unit (MPU) to enhance application security.

STM32H743xI devices incorporate high-speed embedded memories with a dual-bank Flash

memory up to 2 Mbytes, 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, 864 Kbytes of

user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced

I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix

and a multi layer AXI interconnect supporting internal and external memory access.

All the devices offer three ADCs, two DACs, two ultra-low power comparators, a low-power

RTC, a high-resolution timer, 12 general-purpose 16-bit timers, two PWM timers for motor

control, five low-power timers and a true random number generator (RNG). The devices

support four digital filters for external sigma-delta modulators (DFSDM). They also feature

standard and advanced communication interfaces.

•Standard peripherals

–Four I

2Cs

– Four USARTs, four UARTs and one LPUART

– Six SPIs, three I2Ss in half-duplex mode. To achieve audio class accuracy, the I2S

peripherals can be clocked by a dedicated internal audio PLL or by an external

clock to allow synchronization.

– Four SAI serial audio interfaces

– One SPDIFRX interface

– One SWPMI (Single Wire Protocol Master Interface)

– Management Data Input/Output (MDIO) slaves

– Two SDMMC interfaces

– A USB OTG full-speed and a USB OTG high-speed interface with full-speed

capability (with the ULPI)

– One FDCAN plus one TT-CAN interface

– An Ethernet interface

– Chrom-ART Accelerator™

– HDMI-CEC

•Advanced peripherals including

– A flexible memory control (FMC) interface

– A Quad-SPI Flash memory interface

– A camera interface for CMOS sensors

– An LCD-TFT display controller

– A JPEG hardware compressor/decompressor

Refer to Table 2: STM32H743xI features and peripheral counts for the list of peripherals

available on each part number.

Description STM32H743xI

14/226 DocID030538 Rev 3

STM32H743xI devices operate in the –40 to +85 °C temperature range from a 1.62 to 3.6 V

power supply. The supply voltage can drop down to 1.62 V by using an external power

supervisor (see Section 3.5.2: Power supply supervisor) and connecting the PDR_ON pin to

VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power

voltage detector enabled.

Dedicated supply inputs for USB (OTG_FS and OTG_HS) are available on all packages

except LQFP100 to allow a greater power supply choice.

A comprehensive set of power-saving modes allows the design of low-power applications.

STM32H743xI devices are offered in 8 packages ranging from 100 pins to 240 pins/balls.

The set of included peripherals changes with the device chosen.

These features make STM32H743xI microcontrollers suitable for a wide range of

applications:

•Motor drive and application control

•Medical equipment

•Industrial applications: PLC, inverters, circuit breakers

•Printers, and scanners

•Alarm systems, video intercom, and HVAC

•Home audio appliances

•Mobile applications, Internet of Things

•Wearable devices: smart watches.

Figure 1 shows the general block diagram of the device family.

Table 2. STM32H743xI features and peripheral counts

Peripherals STM32H

743VI

STM32H

743ZI

STM32H

743AI

STM32H

743II

STM32H

743BI

STM32H

743XI

Flash memory in Kbytes 2048

SRAM in

Kbytes

SRAM mapped onto

AXI bus 512

SRAM1 (D2 domain) 128

SRAM2 (D2 domain) 128

SRAM3 (D2 domain) 32

SRAM4 (D3 domain) 64

TCM RAM in

Kbytes

ITCM RAM

(instruction) 64

DTCM RAM (data) 128

Backup SRAM (Kbytes) 4

FMC Yes

Quad-SPI Yes

Ethernet Yes

DocID030538 Rev 3 15/226

STM32H743xI Description

Timers

High-resolution 1

General-purpose 10

Advanced-control

(PWM) 2

Basic 2

Low-power 5

Random number generator Yes

Communicati

on interfaces

SPI / I2S6/3

(1)

I2C4

USART/UART/

LPUART

4/4

SAI 4

SPDIFRX 4 inputs

SWPMI Yes

MDIO Yes

SDMMC 2

FDCAN/TT-CAN 1/1

USB OTG_FS Yes

USB OTG_HS Yes

Ethernet and camera interface Yes

LCD-TFT Yes

JPEG Codec Yes

Chrom-ART Accelerator™ (DMA2D) Yes

GPIOs 82 114 131 140 168

8 to 16-bit ADCs

Number of channels

12-bit DAC

Number of channels

Yes

Comparators 2

Operational amplifiers 2

DFSDM Yes

Maximum CPU frequency 400 MHz

Operating voltage 1.71 to

3.6 V(2) 1.62 to 3.6 V(3)

Table 2. STM32H743xI features and peripheral counts (continued)

Peripherals STM32H

743VI

STM32H

743ZI

STM32H

743AI

STM32H

743II

STM32H

743BI

STM32H

743XI

Description STM32H743xI

16/226 DocID030538 Rev 3

Operating temperatures

Ambient temperatures: –40 up to +85 °C(4)

Junction temperature: –40 to + 125 °C

Package LQFP100

TFBGA100(5) LQFP144 UFBGA

169(5)

LQFP176

UFBGA

176+25

LQFP208 TFBGA

240+25

1. The SPI1, SPI2 and SPI3 interfaces give the flexibility to work in an exclusive way in either the SPI mode or the I2S audio

mode.

2. Since the LQFP100 package does not feature the PDR_ON pin (tied internally to VDD), the minimum VDD value for this

package is 1.71 V.

3. VDD/VDDA can drop down to 1.62 V by using an external power supervisor (see Section 3.5.2: Power supply supervisor)

and connecting PDR_ON pin to VSS. Otherwise the supply voltage must stay above 1.71 V with the embedded power

voltage detector enabled.

4. The product junction temperature must be kept within the –40 to +125 °C temperature range.

5. This package is under development. Please contact STMicroelectronics for details.

Table 2. STM32H743xI features and peripheral counts (continued)

Peripherals STM32H

743VI

STM32H

743ZI

STM32H

743AI

STM32H

743II

STM32H

743BI

STM32H

743XI

DocID030538 Rev 3 17/226

STM32H743xI Description

Figure 1. STM32H743xI block diagram

MSv41922V8

TT-FDCAN1

FDCAN2

I2C1/SMBUS

I2C2/SMBUS

I2C3/SMBUS

AXI/AHB12 (200MHz)

4 compl. chan. (TIM1_CH1[1:4]N),

4 chan. (TIM1_CH1[1:4]ETR, BKIN as AF

APB1 30MHz

TX, RX

SCL, SDA, SMBAL as AF

APB1 100 MHz (max)

MDMA

PK[7:0]

4 compl. chan.(TIM8_CH1[1:4]N),

4 chan. (TIM8_CH1[1:4], ETR,

BKIN as AF

RX, TX, SCK, CTS, RTS as AF

SCL, SDA, SMBAL as AF

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

TX, RX

RX, TX as AF

RX, TX, SCK

CTS, RTS as AF

RX, TX, SCK, CTS,

RTS as AF

1 channel as AF

smcard

irDA

1 channel as AF

2 channels as AF

4 channels

4 channels, ETR as AF

RX, TX as AF

FIFO

LCD-TFT

FIFO

CHROM-ART

(DMA2D)

SD, SCK, FS, MCLK, D/CK[4:1] as

FIFO

LCD_R[7:0], LCD_G[7:0],

LCD_B[7:0], LCD_HSYNC,

LCD_VSYNC, LCD_DE, LCD_CLK

CLK, CS,D[7:0]

64-bit AXI BUS-MATRIX

HDMI_CEC as AF

SPDIFRX[3:0] as AF

MDC, MDIO

AXIM

Arm CPU

Cortex-M7

400 MHz

AHBP

AHBS

TRACECK

TRACED[3:0]

JTRST, JTDI,

JTCK/SWCLK

JTDO/SWD, JTDO

JTAG/SW

ETM

I-Cache

16KB

D-Cache

16KB

I-TCM

64KB

D-TCM

64KB

16 Streams

FIFO

SDMMC1

SDMMC_D[7:0],SDMMC_D[7:3,1]Dir

SDMMC_D0dir, SDMMC_D2dir

CMD, CMDdir, CK, Ckin,

CKio as AF

FIFO

DMA1

FIFOs

8 Stream

DMA2

FIFOs

ETHER

MAC

FIFO

SDMMC2

FIFO

OTG_HS

FIFO

OTG_FS

FIFO

SRAM1

128 KB

8 Stream

FMC_signals

DMA/ DMA/ DMA/

PHY PHY

MII / RMII

MDIO

as AF

DP, DM, STP,

NXT,ULPI:CK

, D[7:0], DIR,

ID, VBUS

AHB1 (200MHz)

ADC1

DAC_OUT1, DAC_OUT2 as AF

16b

AXI/AHB34 (200MHz)

JPEG

WWDG

AHB2 (200MHz)

PA..J[15:0]

HSYNC, VSYNC, PIXCLK, D[13:0]

SAI3

MOSI, MISO, SCK, NSS as AF

smcard

irDA 32-bit AHB BUS-MATRIX

AHB4 (200MHz)

BDMA

DMA

Mux2

Up to 20 analog inputs

common to ADC1 & 2

HSEM

AHB4 (200MHz)

AHB3

AHB4

VDDA, VSSA

NRESET

WKUP[4:0]

@VDD

RCC

Reset &

control

OSC32_IN

OSC32_OUT

VBAT = 1.8 to 3.6 V

AWU

VDD12 BBgen + POWER MNGT

LS LS

OSC_IN

OSC_OUT

RTC_TS

RTC_TAMP[1:3]

RTC_OUT

RTC_REFIN

VDDMMC33 = 1.8 to 3.6V

VDDUSB33 = 3.0 to 3.6 V

VDD = 1.8 to 3.6 V

VSS

VCAP1/2/3

@VDD

@VDD33

@VSW

PWRCTRL

AHB4 (200MHz)

SUPPLY SUPERVISION

Int

POR

reset

@VDD

WDG_LS_D1

LPTIM1_IN1, LPTIM1_IN2,

LPTIM1_OUT as AF

OPAMPx_VINM

OPAMPx_VINP

OPAMPx_VOUT as AF

HRTIM1_CH[A..E]x

HRTIM1_FLT[5:1],

HRTIM1_FLT[5:1]_in, SYSFLT

DFSDM_CKOUT,

DFSDM_DATAIN[0:7],

DFSDM_CKIN[0:7]

2 compl. chan.(TIM15_CH1[1:2]N),

2 chan. (TIM_CH15[1:2], BKIN as AF

1 compl. chan.(TIM16_CH1N),

1 chan. (TIM16_CH1, BKIN as AF

1 compl. chan.(TIM17_CH1N),

1 chan. (TIM17_CH1, BKIN as AF

SDMMC_

D[7:0],

CMD, CK as AF

Up to 17 analog inputs

common to ADC1 and 2

SD, SCK, FS, MCLK,

D[3;1], CK[2:1] as AF

SCL, SDA, SMBAL as AF

COMPx_INP, COMPx_INM,

COMPx_OUT as AF

LPTIM5_OUT as AF

D-TCM

64KB

AHB/APB

Quad-SPI

1 MB FLASH

512 KB AXI

SRAM

FMC

Delay block

DCMI AHB/APB

HRTIM1

DFSDM

SD, SCK, FS, MCLK, CK[2:1] as AF

FIFO

SAI2

SD, SCK, FS, MCLK, D[3:1],

CK[2:1] as AF

FIFO

SAI1

SPI5

TIM17

TIM16

TIM15

SPI4

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF SPI1/I2S1

USART6

RX, TX, SCK, CTS, RTS as AF irDA USART1

TIM1/PWM 16b

TIM8/PWM 16b

APB2 100 MHz (max)

ADC3

GPIO PORTA.. J

GPIO PORTK

SAI4

COMP1&2

LPTIM5

LPTIM4_OUT as AF LPTIM4

LPTIM3_OUT as AF LPTIM3

I2C4

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF SPI6/I2S6

RX, TX, CK, CTS, RTS as AF LPUART1

LPTIM2

Tamper monitor

VREF

SYSCFG

EXTI WKUP

CRC

DAP

RNG

DMA

Mux1

To APB1-2

peripherals

SRAM2

128 KB

SRAM3

32 KB

ADC2

AHB/APB

TIM6 16b

TIM7 16b

SWPMI

TIM2

32b

TIM3

16b

TIM4

16b

TIM5

32b

TIM12

16b

TIM13

16b

TIM14

16b

USART2

smcard

irDA

USART3

UART4

UART5

UART7

RX, TX as AF

UART8

SPI2/I2S2

MOSI, MISO, SCK, NSS /

SDO, SDI, CK, WS, MCK, as AF

SPI3/I2S3

Digital filter

MDIOs

FIFO

10 KB SRAM

RAM

I/F

USBCR

SPIFRX

HDMI-CEC

DAC

LPTIM1

OPAMP1&2

AHB/APB

XTAL 32 kHz

RTC

Backup registers

XTAL OSC

4- 48 MHz

HS RC

LS RC

PLL1+PLL2+PLL3

POR/PDR/BOR

PVD

smcard

Voltage

regulator

3.3 to 1.2V

LSI

HSI

CSI

HSI48

LPTIM2_IN1, LPTIM2_IN2 and

LPTIM2_OUT

AHB1 (200MHz)

DP, DM, ID,

VBUS

64 KB SRAM 4 KB BKP

RAM

AHB4

32-bit AHB BUS-MATRIX

APB4 100 MHz (max)

IWDG

Temperature

sensor

Functional overview STM32H743xI

18/226 DocID030538 Rev 3

3 Functional overview

3.1 Arm® Cortex®-M7 with FPU

The Arm® Cortex®-M7 with double-precision FPU processor is the latest generation of Arm

processors for embedded systems. It was developed to provide a low-cost platform that

meets the needs of MCU implementation, with a reduced pin count and optimized power

consumption, while delivering outstanding computational performance and low interrupt

latency.

The Cortex®-M7 processor is a highly efficient high-performance featuring:

•Six-stage dual-issue pipeline

•Dynamic branch prediction

•Harvard architecture with L1 caches (16 Kbytes of I-cache and 16 Kbytes of D-cache)

•64-bit AXI interface

•64-bit ITCM interface

•2x32-bit DTCM interfaces

The following memory interfaces are supported:

•Separate Instruction and Data buses (Harvard Architecture) to optimize CPU latency

•Tightly Coupled Memory (TCM) interface designed for fast and deterministic SRAM

accesses

•AXI Bus interface to optimize Burst transfers

•Dedicated low-latency AHB-Lite peripheral bus (AHBP) to connect to peripherals.

The processor supports a set of DSP instructions which allow efficient signal processing and

complex algorithm execution.

It also supports single and double precision FPU (floating point unit) speeds up software

development by using metalanguage development tools, while avoiding saturation.

Figure 1 shows the general block diagram of the STM32H743xI family.

Note: Cortex®-M7 with FPU core is binary compatible with the Cortex®-M4 core.

3.2 Memory protection unit (MPU)

The memory protection unit (MPU) manages the CPU access rights and the attributes of the

system resources. It has to be programmed and enabled before use. Its main purposes are

to prevent an untrusted user program to accidentally corrupt data used by the OS and/or by

a privileged task, but also to protect data processes or read-protect memory regions.

The MPU defines access rules for privileged accesses and user program accesses. It

allows defining up to 16 protected regions that can in turn be divided into up to 8

independent subregions, where region address, size, and attributes can be configured. The

protection area ranges from 32 bytes to 4 Gbytes of addressable memory.

When an unauthorized access is performed, a memory management exception is

generated.

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STM32H743xI Functional overview

3.3 Memories

3.3.1 Embedded Flash memory

The STM32H743xI devices embed up to 2 Mbytes of Flash memory that can be used for

storing programs and data.

The Flash memory is organized as 266-bit Flash words memory that can be used for storing

both code and data constants. Each word consists of:

•One Flash word (8 words, 32 bytes or 256 bits)

•10 ECC bits.

The Flash memory is divided into two independent banks. Each bank is organized as

follows:

•A 1 Mbyte user Flash memory block containing eight user sectors of

128 Kbytes(4 K Flash words)

•128 Kbytes of System Flash memory from which the device can boot

•2 Kbytes (64 Flash words) of user option bytes for user configuration

3.3.2 Embedded SRAM

All devices feature:

•512 Kbytes of AXI-SRAM mapped onto AXI bus on D1 domain.

•SRAM1 mapped on D2 domain: 128 Kbytes

•SRAM2 mapped on D2 domain: 128 Kbytes

•SRAM3 mapped on D2 domain: 32 Kbytes

•SRAM4 mapped on D3 domain: 64 Kbytes

•4 Kbytes of backup SRAM

The content of this area is protected against possible unwanted write accesses,

and is retained in Standby or VBAT mode.

•RAM mapped to TCM interface (ITCM and DTCM):

Both ITCM and DTCM RAMs are 0 wait state memories that are accessible from the

CPU or the MDMA (even in Sleep mode) through a specific AHB slave of the

CPU(AHBP).

– 64 Kbytes of ITCM-RAM (instruction RAM)

This RAM is connected to ITCM 64-bit interface designed for execution of critical

real-times routines by the CPU.

– 128 Kbytes of DTCM-RAM (2x 64 Kbyte DTCM-RAMs on 2x32-bit DTCM ports)

The DTCM-RAM could be used for critical real-time data, such as interrupt service

routines or stack/heap memory. Both DTCM-RAMs can be used in parallel (for

load/store operations) thanks to the Cortex®-M7 dual issue capability.

Error code correction (ECC)

Over the product lifetime, and/or due to external events such as radiations, invalid bits in

memories may occur. They can be detected and corrected by ECC. This is an expected

behavior that has to be managed at final-application software level in order to ensure data

integrity through ECC algorithms implementation.

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20/226 DocID030538 Rev 3

SRAM data are protected by ECC:

•7 ECC bits are added per 32-bit word.

•8 ECC bits are added per 64-bit word for AXI-SRAM and ITCM-RAM.

The ECC mechanism is based on the SECDED algorithm. It supports single- and double-

error correction.

3.4 Boot modes

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDx option

bytes, allowing to program any boot memory address from 0x0000 0000 to 0x3FFF FFFF

which includes:

•All Flash address space

•All RAM address space: ITCM, DTCM RAMs and SRAMs

•The System memory bootloader

The boot loader is located in non-user System memory. It is used to reprogram the Flash

memory through a serial interface (USART, I2C, SPI, USB-DFU). Refer to STM32

microcontroller System memory boot mode application note (AN2606) for details.

3.5 Power supply management

3.5.1 Power supply scheme

•VDD = 1.62 to 3.6 V: external power supply for I/Os, provided externally through VDD

pins.

•VDDLDO = 1.62 to 3.6 V: supply voltage for the internal regulator supplying VCORE

•VDDA = 1.62 to 3.6 V: external analog power supplies for ADC, DAC, COMP and

OPAMP.

•VDD33USB and VDD50USB:

VDD50USB can be supplied through the USB cable to generate the VDD33USB via the

USB internal regulator. This allows supporting a VDD supply different from 3.3 V.

The USB regulator can be bypassed to supply directly VDD33USB if VDD = 3.3 V.

•VBAT = 1.2 to 3.6 V: power supply for the VSW domain when VDD is not present.

•VCAP1/VCAP2/VCAP3: VCORE supplies, which values depend on voltage scaling (0.7 V,

0.9 V, 1.0 V, 1.1 V or 1.2 V). They are configured through VOS bits in PWR_D3CR

independently switch off.

– D1 domain containing some peripherals and the Cortex®-M7 core.

– D2 domain containing a large part of the peripherals.

– D3 domain containing some peripherals and the system control.

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STM32H743xI Functional overview

3.5.2 Power supply supervisor

The devices have an integrated power-on reset (POR)/ power-down reset (PDR) circuitry

coupled with a Brownout reset (BOR) circuitry:

•Power-on reset (POR)

The POR supervisor monitors VDD power supply and compares it to a fixed threshold.

The devices remain in reset mode when VDD is below this threshold,

•Power-down reset (PDR)

The PDR supervisor monitors VDD power supply. A reset is generated when VDD drops

below a fixed threshold.

The PDR supervisor can be enabled/disabled through PDR_ON pin.

•Brownout reset (BOR)

The BOR supervisor monitors VDD power supply. Three BOR thresholds (from 2.1 to

2.7 V) can be configured through option bytes. A reset is generated when VDD drops

below this threshold.

3.5.3 Voltage regulator

The same voltage regulator supplies the 3 power domains (D1, D2 and D3). D1 and D2 can

be independently switched off.

Voltage regulator output can be adjusted according to application needs through 5 power

supply levels:

•Run mode (VOS1 to VOS3)

– Scale 1: high performance

– Scale 2: medium performance and consumption

– Scale 3: optimized performance and low-power consumption

•Stop mode (SVOS3 to SVOS5)

– Scale 3: peripheral with wakeup from stop mode capabilities (UART, SPI, I2C,

LPTIM) are operational

– Scale 4 and 5 where the peripheral with wakeup from Stop mode is disabled

The peripheral functionality is disabled but wakeup from Stop mode is possible

through GPIO or asynchronous interrupt.

3.6 Low-power strategy

There are several ways to reduce power consumption on STM32H743xI:

•Decrease dynamic power consumption by slowing down the system clocks even in

Run mode and individually clock gating the peripherals that are not used.

•Save power consumption when the CPU is idle, by selecting among the available low-

power mode according to the user application needs. This allows achieving the best

compromise between short startup time, low-power consumption, as well as available

wakeup sources.

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The devices feature several low-power modes:

•CSleep (CPU clock stopped)

•CStop (CPU sub-system clock stopped)

•DStop (Domain bus matrix clock stopped)

•Stop (System clock stopped)

•DStandby (Domain powered down)

•Standby (System powered down)

CSleep and CStop low-power modes are entered by the MCU when executing the WFI

(Wait for Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit of

the Cortex®-Mx core is set after returning from an interrupt service routine.

A domain can enter low-power mode (DStop or DStandby) when the processor, its

subsystem and the peripherals allocated in the domain enter low-power mode.

If part of the domain is not in low-power mode, the domain remains in the current mode.

Finally the system can enter Stop or Standby when all EXTI wakeup sources are cleared

and the power domains are in DStop or DStandby mode.

3.7 Reset and clock controller (RCC)

The clock and reset controller is located in D3 domain. The RCC manages the generation of

all the clocks, as well as the clock gating and the control of the system and peripheral

resets. It provides a high flexibility in the choice of clock sources and allows to apply clock

ratios to improve the power consumption. In addition, on some communication peripherals

that are capable to work with two different clock domains (either a bus interface clock or a

kernel peripheral clock), the system frequency can be changed without modifying the

baudrate.

Table 3. System vs domain low-power mode

System power mode D1 domain power

mode

D2 domain power

mode

D3 domain power

mode

Run DRun/DStop/DStandby DRun/DStop/DStandby DRun

Stop DStop/DStandby DStop/DStandby DStop

Standby DStandby DStandby DStandby

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STM32H743xI Functional overview

3.7.1 Clock management

The devices embed four internal oscillators, two oscillators with external crystal or

resonator, two internal oscillators with fast startup time and three PLLs.

The RCC receives the following clock source inputs:

•Internal oscillators:

–64 MHz HSI clock (1% accuracy)

– 48 MHz RC oscillator

– 4 MHz CSI clock

– 32 kHz LSI clock

•External oscillators:

– 4-48 MHz HSE clock

– 32.768 kHz LSE clock

The RCC provides three PLLs: one for system clock, two for kernel clocks.

The system starts on the HSI clock. The user application can then select the clock

configuration.

3.7.2 System reset sources

Power-on reset initializes all registers while system reset reinitializes the system except for

the debug, part of the RCC and power controller status registers, as well as the backup

power domain.

A system reset is generated in the following cases:

•Power-on reset (pwr_por_rst)

•Brownout reset

•Low level on NRST pin (external reset)

•Window watchdog

•Independent watchdog

•Software reset

•Low-power mode security reset

•Exit from Standby

3.8 General-purpose input/outputs (GPIOs)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain,

with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)

or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog

alternate functions. All GPIOs are high-current-capable and have speed selection to better

manage internal noise, power consumption and electromagnetic emission.

After reset, all GPIOs are in Analog mode to reduce power consumption.

The I/O configuration can be locked if needed by following a specific sequence in order to

avoid spurious writing to the I/Os registers.

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3.9 Bus-interconnect matrix

The devices feature an AXI bus matrix, two AHB bus matrices and bus bridges that allow

interconnecting bus masters with bus slaves (see Figure 2).

STM32H743xI Functional overview

DocID030538 Rev 3 25/226

Figure 2. STM32H743xI bus matrix

MSv46613V1

AXIM

DMA2 Ethernet

MAC SDMMC2DMA1 USBHS1 USBHS2

APB1

SDMMC1 MDMA DMA2D LTDC

BDMA

APB4

Cortex-M7

16KB

AHBP

DMA1_MEM

DMA1_PERIPH

DMA2_MEM

DMA2_PERIPH

APB3

32-bit AHB bus matrix

D2 domain

64-bit AXI bus matrix

D1 domain

32-bit AHB bus matrix

D3 domain

DTCM

128 Kbyte

ITCM

64 Kbyte

Flash A

1 Mbyte

Flash B

1 Mbyte

AXI SRAM

512 Kbyte

QSPI

FMC

SRAM1 128

Kbyte

SRAM2 128

Kbyte

SRAM3

32 Kbyte

AHB1

AHB2

AHB4

SRAM4

64 Kbyte

Backup

SRAM

4 Kbyte

AHBS

CPU

D2-to-D1 AHB

D2-to-D3 AHB

D1-to-D2 AHB

D1-to-D3 AHB

32-bit bus

64-bit bus

Bus multiplexer

Legend

Master interface

Slave interface

AHB3

AXI

AHB

APB

APB2

TCM

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3.10 DMA controllers

The devices feature four DMA instances to unload CPU activity:

•A master direct memory access (MDMA)

The MDMA is a high-speed DMA controller, which is in charge of all types of memory

transfers (peripheral to memory, memory to memory, memory to peripheral), without

any CPU action. It features a master AXI interface and a dedicated AHB interface to

access Cortex®-M7 TCM memories.

The MDMA is located in D1 domain. It is able to interface with the other DMA

controllers located in D2 domain to extend the standard DMA capabilities, or can

manage peripheral DMA requests directly.

Each of the 16 channels can perform single block transfers, repeated block transfers

and linked list transfers.

•Two dual-port DMAs (DMA1, DMA2) located in D2 domain, with FIFO and request

router capabilities.

•One basic DMA (BDMA) located in D3 domain, with request router capabilities.

The DMA request router could be considered as an extension of the DMA controller. It

routes the DMA peripheral requests to the DMA controller itself. This allowing managing the

DMA requests with a high flexibility, maximizing the number of DMA requests that run

concurrently, as well as generating DMA requests from peripheral output trigger or DMA

event.

3.11 Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphical accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•Rectangle filling with a fixed color

•Rectangle copy

•Rectangle copy with pixel format conversion

•Rectangle composition with blending and pixel format conversion

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables. The DMA2D also

supports block based YCbCr to handle JPEG decoder output.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

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STM32H743xI Functional overview

3.12 Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller which is able to manage 16

priority levels, and handle up to 150 maskable interrupt channels plus the 16 interrupt lines

of the Cortex®-M7 with FPU core.

•Closely coupled NVIC gives low-latency interrupt processing

•Interrupt entry vector table address passed directly to the core

•Allows early processing of interrupts

•Processing of late arriving, higher-priority interrupts

•Support tail chaining

•Processor context automatically saved on interrupt entry, and restored on interrupt exit

with no instruction overhead

This hardware block provides flexible interrupt management features with minimum interrupt

latency.

3.13 Extended interrupt and event controller (EXTI)

The EXTI controller performs interrupt and event management. In addition, it can wake up

the processor, power domains and/or D3 domain from Stop mode.

The EXTI handles up to 89 independent event/interrupt lines split as 28 configurable events

and 61 direct events .

Configurable events have dedicated pending flags, active edge selection, and software

trigger capable.

Direct events provide interrupts or events from peripherals having a status flag.

3.14 Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

programmable polynomial.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

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3.15 Flexible memory controller (FMC)

The FMC controller main features are the following:

•Interface with static-memory mapped devices including:

– Static random access memory (SRAM)

– NOR Flash memory/OneNAND Flash memory

– PSRAM (4 memory banks)

– NAND Flash memory with ECC hardware to check up to 8 Kbytes of data

•Interface with synchronous DRAM (SDRAM/Mobile LPSDR SDRAM) memories

•8-,16-,32-bit data bus width

•Independent Chip Select control for each memory bank

•Independent configuration for each memory bank

•Write FIFO

•Read FIFO for SDRAM controller

•The maximum FMC_CLK/FMC_SDCLK frequency for synchronous accesses is the

FMC kernel clock divided by 2.

3.16 Quad-SPI memory interface (QUADSPI)

All devices embed a Quad-SPI memory interface, which is a specialized communication

interface targeting Single, Dual or Quad-SPI Flash memories. It supports both single and

double datarate operations.

It can operate in any of the following modes:

•Direct mode through registers

•External Flash status register polling mode

•Memory mapped mode.

Up to 256 Mbytes of external Flash memory can be mapped, and 8-, 16- and 32-bit data

accesses are supported as well as code execution.

The opcode and the frame format are fully programmable.

3.17 Analog-to-digital converters (ADCs)

The STM32H743xI devices embed three analog-to-digital converters, which resolution can

be configured to 16, 14, 12, 10 or 8 bits. Each ADC shares up to 20 external channels,

performing conversions in the single-shot or scan mode. In scan mode, automatic

conversion is performed on a selected group of analog inputs.

Additional logic functions embedded in the ADC interface allow:

•Simultaneous sample and hold

•Interleaved sample and hold

The ADC can be served by the DMA controller, thus allowing to automatically transfer ADC

converted values to a destination location without any software action.