TM4C1290NCPDTT3 - TEXAS INSTRUMENTS

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Typical applicaTion

neTwork FeaTures DescripTion

SmartMesh IP Network Manager

2.4GHz 802.15.4e

Wireless Embedded Manager

lTp5901/2-ipr FeaTures

n Complete Radio Transceiver, Embedded Processor,

and Networking Software for Forming a Self-Healing

Mesh Network

n SmartMesh

Networks Incorporate:

n Time Synchronized Network-Wide Scheduling

n Per Transmission Frequency Hopping

n Redundant Spatially Diverse Topologies

n Network-Wide Reliability and Power Optimization

n NIST Certified Security

n SmartMesh Networks Deliver:

n >99.999% Network Reliability Achieved in the

Most Challenging RF Environments

n Sub 50µA Routing Nodes

n Compliant to 6LoWPAN Internet Protocol (IP) and

IEEE 802.15.4e Standards

n Manages Networks of Up to 32 Nodes (LT P 5901/2-

IPRA) or Up to 100 Nodes (LT P 5901/2-IPRB)

n Sub 1mA Average Current Consumption Enables

Battery Powered Network Management

n RF Modular Certification Include USA, Canada, EU,

Japan, Taiwan, Korea, India, Australia and New

Zealand

n PCB Assembly with Chip Antenna (LT P 5901-IPR) or

with MMCX Antenna Connector (LT P 5902-IPR)

SmartMesh IP™ wireless sensor networks are self man-

aging, low power internet protocol (IP) networks built

from wireless nodes called motes. The LT P ™5901-IPR/

LT P 5902-IPR is the IP manager product in the Eterna

family of IEEE 802.15.4e printed circuit board assembly

solutions, featuring a highly integrated, low power radio

design by Dust Networks

as well as an ARM Cortex-M3

32-bit microprocessor running Dust’s embedded Smart-

Mesh IP networking software.

Based on the IETF 6LoWPAN and IEEE-802.15.4e stan-

dards, the LT P 5901/2-IPR runs SmartMesh IP network

management software to monitor and manage network

performance and provide a data ingress/egress point via

a UART interface. The SmartMesh IP software provided

with the LT P 5901/2-IPR is fully tested and validated, and

is readily configured via a software application program-

ming interface. With Dust’s time-synchronized SmartMesh

IP networks, all motes in the network may route, source

or terminate data, while providing many years of battery

powered operation.

SmartMesh IP motes deliver a highly flexible network

with proven reliability and low power performance in an

easy-to-integrate platform.

L, LT , LT C , LT M , Linear Technology, Dust, Dust Networks, Eterna, SmartMesh and the

Linear logo are registered trademarks and LT P , SmartMesh IP and the Dust Networks logo are

trademarks of Linear Technology Corporation. All other trademarks are the property of their

respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419,

7881239, 7898322, 8222965.

* Eterna is Dust Networks’ low power radio SoC architecture.

59012IPR TA01

µCONTROLLERSENSOR

IN+

IN–

SPILT C

2379-18

LTP5901/2-IPM

UART

MOTE

EXPANDED VIEW

ANTENNA

LTP5901-IPR

HOST

APPLICATION

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Table oF conTenTs

Network Features .......................................... 1

LTP5901/2-IPR Features .................................. 1

Typical Application ........................................ 1

Description.................................................. 1

SmartMesh Network Overview ........................... 3

Absolute Maximum Ratings .............................. 4

Pin Configuration .......................................... 4

Order Information .......................................... 5

Recommended Operating Conditions ................... 5

DC Characteristics ......................................... 5

Radio Specifications ...................................... 6

Radio Receiver Characteristics .......................... 6

Radio Transmitter Characteristics ....................... 7

Digital I/O Characteristics ................................ 7

Temperature Sensor Characteristics .................... 7

System Characteristics ................................... 8

UART AC Characteristics .................................. 8

Time AC Characteristics .................................. 9

Radio_INHIBIT AC Characteristics ..................... 10

Flash AC Characteristics ................................. 10

Flash SPI Slave AC Characteristics .................... 10

External Bus AC Characteristics ........................ 11

Typical Performance Characteristics .................. 14

Pin Functions .............................................. 19

Operation................................................... 22

Power Supply ..........................................................23

Supply Monitoring and Reset ................................. 23

Precision Timing ..................................................... 23

Application Time Synchronization ..........................23

Time References ..................................................... 23

Radio ...................................................................... 24

UARTs ..................................................................... 24

API UART Protocol ................................................. 24

CLI UART ................................................................ 25

Autonomous MAC ...................................................25

Security .................................................................. 25

Temperature Sensor ...............................................25

Radio Inhibit ...........................................................25

Factory Installed Software ......................................25

Flash Data Retention ...............................................26

Networking .............................................................27

Applications Information ................................ 29

Regulatory and Standards Compliance ...................29

Soldering Information ............................................. 29

Related Documentation .................................. 29

Package Description ..................................... 30

Typical Application ....................................... 32

Related Parts .............................................. 32

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

smarTmesh neTwork overview

A SmartMesh network consists of a self-forming multi-hop,

mesh of nodes, known as motes, which collect and relay

data, and a network manager that monitors and manages

network performance and security, and exchanges data

with a host application.

SmartMesh networks communicate using a time slotted

channel hopping(TSCH) link layer, pioneered by Dust

Networks. In a TSCH network, all motes in the network

are synchronized to within less than a millisecond. Time

in the network is organized into timeslots, which enables

collision-free packet exchange and per-transmission

channel-hopping. In a SmartMesh network, every device

has one or more parents (e.g. mote 3 has motes 1 and

2 as parents) that provide redundant paths to overcome

communications interruption due to interference, physical

obstruction or multi-path fading. If a packet transmission

fails on one path, the next retransmission may try on a

different path and different RF channel.

A network begins to form when the network manager

instructs its onboard access point (AP) radio to begin

sendingadvertisements—packets that contain information

that enables a device to synchronize to the network and

request to join. This message exchange is part of thesecu-

rityhandshake that establishes encrypted communications

between the manager or application, and mote. Once motes

have joined the network, they maintain synchronization

through time corrections when a packet is acknowledged.

to the network manager in packets called health reports.

The network manager uses health reports to continually

optimize the network to maintain >99.999% data reliability

even in the most challenging RF environments.

The use of TSCH allows SmartMesh devices to sleep in-

between scheduled communications and draw very little

power in this state. Motes are only active in timeslots

where they are scheduled to transmit or receive, typically

resulting in a duty cycle of < 1%. The optimization soft-

ware in the network manager coordinates this schedule

automatically. When combined with the Eterna low power

radio, every mote in a SmartMesh network—even busy

routing ones—can run on batteries for years. By default,

all motes in a network are capable of routing traffic from

other motes, which simplifies installation by avoiding the

complexity of having distinct routers vs non-routing end

nodes. Motes may be configured as non-routing to further

reduce that particular mote’s power consumption and to

support a wide variety of network topologies.

An ongoing discovery process ensures that the network

continually discovers new paths as the RF conditions

change. In addition, each mote in the network tracks per-

formance statistics (e.g. quality of used paths, and lists of

potential paths) and periodically sends that information

At the heart of SmartMesh motes and network managers

is the Eterna IEEE 802.15.4e System-on-Chip (SoC), fea-

turing Dust Networks’ highly integrated, low power radio

design, plus an ARM Cortex-M3 32-bit microprocessor

running SmartMesh networking software. The SmartMesh

networking software comes fully compiled yet is configu-

rable via a rich set of application programming interfaces

(APIs) which allows a host application to interact with

the network, e.g. to transfer information to a device, to

configure data publishing rates on one or more motes,

or to monitor network state or performance metrics. Data

publishing can be uniform or different for each device,

with motes being able to publish infrequently or faster

than once per second as needed.

HOST

APPLICATION

NETWORK MANAGER

59012IPR SNO01

Mote

ALL NODES ARE ROUTERS.

THEY CAN TRANSMIT AND RECEIVE.

THIS NEW NODE CAN JOIN

ANYWHERE BECAUSE ALL

NODES CAN ROUTE.

59012IPR SNO02

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

pin conFiguraTion

absoluTe maximum raTings

Supply Voltage on VSUPPLY ..................................3.76V

Input Voltage on AI_0/1/2/3 Inputs ........................1.80V

Voltage on Any Digital I/O Pin .... –0.3V to VSUPPLY + 0.3V

Input RF Level ...................................................... 10dBm

Storage Temperature Range (Note 3) ..... –55°C to 105°C

(Notes 1, 2) Operating Temperature Range

LTP5901I/LPT5902I .............................–40°C to 85°C

CAUTION: This part is sensitive to electrostatic discharge

(ESD). It is very important that proper ESD precautions

be observed when handling the LTP5901/LTP5902-IPR.

Pin functions shown in italics are currently not supported in software.

GND

RESERVED

GPIO17

GPIO18

GPIO19

AI_2

AI_1

AI_3

AI_0

GND

RESERVED

RESETn

TDI

TDO

TMS

TCK

GND

DP4

RESERVED

EB_DATA_7

EB_DATA_6

EB_DATA_4

EB_DATA_0

GND

RADIO_INHIBIT

TIMEn

UART_TX

UART_TX_CTSn

UART_TX_RTSn

UART_RX

UART_RX_CTSn

UART_RX_RTSn

GND

VSUPPLY

RESERVED

FLASH_P_ENn / EB_IO_LE1

EB_IO_OEn

EB_IO_WEn

RESERVED / UARTC1_RX

RESERVED / UARTC1_TX

EB_IO_CS0n

EB_DATA_5

EB_DATA_2

EB_DATA_3

GND

EB_ADDR_0

EB_ADDR_1

IPCS_SSn

EB_IO_LE2

GND

IPCS_MISO

UARTCO_RX / EB_DATA_1

UARTCO_TX / EB_IO_LE0

PC PACKAGE

66-LEAD PCB

IPCS_SCK

IPCS_MOSI

GND

31 32 33 34 35 36

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

orDer inFormaTion

LEAD FREE FINISH** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LT P 5901IPC-IPRA???#PBF LT P 5901IPC-IPRA???#PBF 66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna –40°C to 85°C

LT P 5901IPC-IPRB???#PBF LT P 5901IPC-IPRB???#PBF 66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna –40°C to 85°C

LT P 5901IPC-IPRC???#PBF LT P 5901IPC-IPRC???#PBF 66-Lead (42mm × 24mm × 5.5mm) PCB with Chip Antenna –40°C to 85°C

LT P 5902IPC-IPRA???#PBF LT P 5902IPC-IPRA???#PBF 66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX

Connector

–40°C to 85°C

LT P 5902IPC-IPRB???#PBF LT P 5902IPC-IPRB???#PBF 66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX

Connector

–40°C to 85°C

LT P 5902IPC-IPRC???#PBF LT P 5902IPC-IPRC???#PBF 66-Lead (37.5mm × 24mm × 5.5mm) PCB with MMCX

Connector

–40°C to 85°C

*The temperature grade is identified by a label on the shipping container.

**The sofware version is indicated by ???. For specific ordering information, go to: www.linear.com/ltp5901-ipr#orderinfo or

www.linear.com/ltp5902-ipr#orderinfo

For a description of the dash options see the IP Manager Options section.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

recommenDeD operaTing conDiTions

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VSUPPLY Supply Voltage Including Noise and Load Regulation l 2.1 3.76 V

Supply Noise 50Hz to 2MHz l250 mV

Operating Relative Humidity Non-Condensing l10 90 % RH

Temperature Ramp Rate While Operating in

Network

l–8 8 °C/min

The l denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

Dc characTerisTics

OPERATION/STATE CONDITIONS MIN TYP MAX UNITS

Power-On Reset During Power-On Reset, Maximum 750µs + VSUPPLY Rise Time from 1V to

1.9V

12 mA

Doze RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and

State Retained, 32.768kHz Reference Active

1.2 µA

Deep Sleep RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and

State Retained, 32.768kHz Reference Inactive

0.8 µA

In-Circuit Programming RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz 20 mA

Peak Operating Current

8dBm

0dBm

System Operating at 14.7MHz, Radio Transmitting, During Flash Write.

Maximum Duration 4.33 ms.

Active ARM Cortex-M3, RAM and Flash Operating, Radio and All Other Peripherals

Off. Clock Frequency of CPU and Peripherals Set to 7.3728MHz, VCORE =

1.2V

1.3 mA

Flash Write Single Bank Flash Write 3.7 mA

Flash Erase Single Bank Page or Mass Erase 2.5 mA

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

OPERATION/STATE CONDITIONS MIN TYP MAX UNITS

Radio Tx

0dBm

8dBm

Current with Autonomous MAC Managing Radio Operation, CPU Inactive.

Clock Frequency of CPU and Peripherals Set to 7.3728MHz.

5.4

9.7

Radio Rx Current with Autonomous MAC Managing Radio Operation, CPU Inactive.

Clock Frequency of CPU and Peripherals Set to 7.3728MHz.

4.5 mA

Dc characTerisTics

The l denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Frequency Band l2.4000 2.4835 GHz

Number of Channels l15

Channel Separation l5 MHz

Channel Center Frequency Where k = 11 to 25, as Defined by IEEE.802.4.15 l2405 + 5*(k-11) MHz

Raw Data Rate l250 kbps

Antenna Pin ESD Protection HBM Per JEDEC JESD22-A114F (Note 2) ±6000 V

Range

Indoor

Outdoor

Free Space

25°C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m Above

Ground

100

300

1200

raDio speciFicaTions

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Receiver Sensitivity Packet Error Rate (PER) = 1% (Note 5) –93 dBm

Receiver Sensitivity PER = 50% –95 dBm

Saturation Maximum Input Level the Receiver Will

Properly Receive Packets

0 dBm

Adjacent Channel Rejection

(High Side)

Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Above the Desired Signal, PER = 1% (Note 5)

22 dBc

Adjacent Channel Rejection

(Low Side)

Desired Signal at –82dBm, Adjacent Modulated Channel 5MHz

Below the Desired Signal, PER = 1% (Note 5)

19 dBc

Alternate Channel Rejection

(High Side)

Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Above the Desired Signal, PER = 1% (Note 5)

40 dBc

Alternate Channel Rejection

(Low Side)

Desired Signal at –82dBm, Alternate Modulated Channel 10MHz

Below the Desired Signal, PER = 1% (Note 5)

36 dBc

Second Alternate Channel

Rejection

Desired Signal at –82dBm, Second Alternate Modulated Channel

Either 15MHz Above or Below, PER = 1% (Note 5)

42 dBc

Co-Channel Rejection Desired Signal at –82dBm, Undesired Signal is an 802.15.4

Modulated Signal at the Same Frequency, PER = 1%

–6 dBc

LO Feed Through –55 dBm

Frequency Error Tolerance

(Note 6)

±50 ppm

Symbol Error Tolerance ±50 ppm

Received Signal Strength

Indicator (RSSI) Input

Range

–90 to -10 dBm

RSSI Accuracy ±6 dB

RSSI Resolution 1 dB

raDio receiver characTerisTics

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

PARAMETER CONDITIONS MIN TYP MAX UNITS

Output Power

High Calibrated Setting

Low Calibrated Setting

Delivered to a 50Ω Load

dBm

Spurious Emissions

30MHz to 1000MHz

1GHz to 12.75GHz

2.4GHz ISM Upper Band Edge (Peak)

2.4GHz ISM Upper Band Edge (Average)

2.4GHz ISM Lower Band Edge

Conducted Measurement with a 50Ω Single-Ended

Load, 8dBm Output Power. All Measurements Made

with Max Hold.

RBW = 120kHz, VBW = 100Hz

RBW = 1MHz, VBW = 3MHz

RBW = 1MHz, VBW = 10Hz

RBW = 100kHz, VBW = 100kHz

< –70

–45

–37

–49

–45

dBm

dBc

Harmonic Emissions

2nd Harmonic

3rd Harmonic

Conducted Measurement Delivered to a 50Ω Load,

Resolution Bandwidth = 1MHz, Video Bandwidth =

1MHz.

–50

–45

dBm

raDio TransmiTTer characTerisTics

The l denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

VIL Low Level Input Voltage l–0.3 0.6 V

VIH High Level Input Voltage (Note 8) lVSUPPLY

– 0.3

VSUPPLY

+ 0.3

VOL Low Level Output Voltage Type 1, IOL(MAX) = 1.2mA l0.4 V

VOH High Level Output Voltage Type 1, IOH(MAX) = –0.8mA lVSUPPLY

– 0.3

VSUPPLY

+ 0.3

VOL Low Level Output Voltage Type 2, Low Drive, IOL(MAX) = 2.2mA l0.4 V

VOH High Level Output Voltage Type 2, Low Drive, IOH(MAX) = –1.6mA lVSUPPLY

– 0.3

VSUPPLY

+ 0.3

VOL Low Level Output Voltage Type 2, High Drive, IOL(MAX) = 4.5mA l0.4 V

VOH High Level Output Voltage Type 2, High Drive, IOH(MAX) = –3.2mA lVSUPPLY

– 0.3

VSUPPLY

+ 0.3

Input Leakage Current Input Driven to VSUPPLY or GND 50 nA

Pull-Up/Pull-Down Resistance 50 kΩ

DigiTal i/o characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

PARAMETER CONDITIONS MIN TYP MAX UNITS

Offset Temperature Offset Error at 25°C ±0.25 °C

Slope Error ±0.033 °C/°C

TemperaTure sensor characTerisTics

The l denotes the specifications which apply over

the full operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

sysTem characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted.

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

Permitted Rx Baud Rate Error Both Application Programming Interface

(API) and Command Line Interface (CLI)

UARTs

l–2 2 %

Generated Tx Baud Rate Error Both API and CLI UARTs l–1 1 %

tRX_RTS to RX_CTS Assertion of UART_RX_RTSn to Assertion of

UART_RX_CTSn, or Negation of UART_RX_

RTSn to Negation of UART_RX_CTSn

l0 2 ms

tCTS_R to RX Assertion of UART_RX_CTSn to Start of Byte l0 20 ms

tEOP to RX_RTS End of Packet (End of the Last Stop Bit) to

Negation of UART_RX_RTSn

l0 22 ms

tBEG_TX_RTS to TX_CTS Assertion of UART_TX_RTSn to Assertion of

UART_TX_CTSn

l0 22 ms

tEND_TX_CTS to TX_RTS Negation of UART_TX_CTSn to Negation of

UART_TX_RTSn

2 Bit

Period

tTX_CTS to TX Assertion of UART_TX_CTSn to Start of Byte l0 2 Bit

Period

tEOP to TX_RTS End of Packet (End of the Last Stop Bit) to

Negation of UART_TX_RTSn

l0 1 Bit

Period

tRX_INTERBYTE Receive Inter-Byte Delay l100 ms

tTX to TX_CTS Start of Byte to Negation of UART_TX_CTSn l0 µs

uarT ac characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

Doze to Active State Transmit 5 µs

Doze to Radio Tx or Rx 1.2 ms

QCCA Charge to Sample RF Channel RSSI Charge Consumed Starting from Doze State

and Completing an RSSI Measurement

4 µC

QMAX Largest Atomic Charge Operation Flash Erase, 21ms Max Duration l200 µC

RESETn Pulse Width l125 µs

LTP5901-IPR/LTP5902-IPR

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For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Figure 1. API UART Timing

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

tSTROBE TIMEn Signal Strobe Width l125 µs

tRESPONSE Delay from Rising Edge of TIMEn to the Start of

Time Packet on API UART

l0 100 ms

tTIME_HOLD Delay from End of Time Packet on API UART to

Falling Edge of Subsequent TIMEn

l0 ns

Timestamp Resolution (Note 9) l1 µs

Network-Wide Time Accuracy (Note 10) l±5 µs

Time ac characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

Figure 2. Timestamp Timing

uarT ac characTerisTics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

59012IPR F01

UART_TX_RTSn

UART_TX_CTSn

UART_TX BYTE 0 BYTE 1

tBEG_TX_RTS TO TX_CTS

tEND_TX_CTS TO TX_RTS

tTX_CTS TO TX

tTX TO TX_CTS

tEOP TO TX_RTS

tEND_TX_RTS TO TX_CTS

UART_RX_RTSn

UART_RX_CTSn

tRX_RTS TO RX_CTS

UART_RX

tEOP TO RX_RTS

tRX_RTS TO RX_CTS

tRX_CTS TO RX

tRX_INTERBYTE

BYTE 0 BYTE 1

59012IPR F02

TIMEn

UART_TX

tSTROBE tTIME_HOLD

tRESPONSE

TIME INDICATION PAYLOAD

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Flash spi slave ac characTerisTics

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

tFP_EN_to_RESET Setup from Assertion of FLASH_P_ENn to

Assertion of RESETn

l0 ns

tFP_ENTER Delay from the Assertion RESETn to the First

Falling Edge of IPCS_SSn

l125 µs

tFP_EXIT Delay from the Completion of the Last Flash SPI

Slave Transaction to the Negation of RESETn

and FLASH_P_ENn

l10 µs

tSSS IPCS_SSn Setup to the Leading Edge of

IPCS_SCK

l15 ns

tSSH IPCS_SSn Hold from Trailing Edge of IPCS_SCK l15 ns

tCK IPCS_SCK Period l50 ns

tDIS IPCS_MOSI Data Setup l15 ns

tDIH IPCS_MOSI Data Hold l5 ns

tDOV IPCS_MISO Data Valid l3 ns

tOFF IPCS_MISO Data Three-State l0 30 ns

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

tWRITE Time to Write a 32-Bit Word (Note 11) l21 ms

tPAGE_ERASE Time to Erase a 2k Byte Page (Note 11) l21 ms

tMASS_ERASE Time to Erase 256k Byte Flash Bank (Note 11) l21 ms

Data Retention 25°C

85°C

105°C

100

Years

Flash ac characTerisTics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX UNITS

tRADIO_OFF Delay from Rising Edge of RADIO_

INHIBIT to Radio Disabled

l20 ms

tRADIO_INHIBIT_STROBE Maximum RADIO_INHIBIT Strobe Width l2 s

raDio_inhibiT ac characTerisTics

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

Figure 3. RADIO_INHIBIT Timing

59012IPR F03

RADIO_INHIBIT

RADIO STATE

tRADIO_OFF

tRADIO_INHIBIT_STROBE

ACTIVE/OFF ACTIVE/OFFOFF

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Figure 4. Flash Programming Interface Timing

59012IPR F04

IPCS_SCK

IPCS_MOSI

IPCS_SSn

RESETn

FLASH_P_ENn

tFP_EN_TO_RESET

tFP_ENTER

tSSS

tDIS

tDIH

tCK

tSSH

tFP_EXIT

Flash spi slave ac characTerisTics

exTernal bus ac characTerisTics

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tLEPW EB_IO_LE0, EB_IO_LE1, EB_IO_LE2 Pulse

Width

l100 ns

tAH EB_DATA_[7:0] Address Hold from the

Rising Edge of EB_IO_LE0, EB_IO_LE1, and

EB_IO_LE2

EB_DATA_[7:0] During Address

Phase

l90 ns

tAV_to_DL EB_ADDR_[1:0] Address Valid Until

EB_DATA_[7:0] Data Latched

l90 ns

tCSn_to_OEn EB_CS0n Asserted Until EB_OEn Asserted l150 ns

tCSn_OFF EB_CS0n Negated Between External Bus

Transfers

l100 ns

tSU_to_CSn EB_ADDR_[1:0], EB_IO_WEn Setup to

EB_CSn Asserted

l50 ns

tH_from_CSn EB_ADDR_[1:0], EB_IO_WEn Hold from

EB_CSn Negated

l50 ns

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

exTernal bus ac characTerisTics

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

Figure 5. External Bus Read Timing

Figure 6. External Bus Write Timing

59012IPR F06

EB_DATA_[7:0] A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8]X X

EB_IO_LE2

EB_IO_LE1

EB_IO_LE0

tLEPW

tH_from_CSn

tSU_to_CSn

tCSn tCSn_OFF

EB_ADDR_[1:0]

tAH tAH tAH

EB_IO_WEn

EB_IO_CS0n

11XX 10 01 0000

59012IPR F05

EB_DATA_[7:0] A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8]X X

EB_IO_LE2

EB_IO_LE1

EB_IO_LE0

tLEPW

tCSn_OFF

tAV_to_DL

tCSn_to_OEn

EB_ADDR_[1:0]

tAH tAH tAH

EB_IO_CS0n

EB_IO_OEn

11XX 10 01 00

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: ESD (electrostatic discharge) sensitive device. ESD protection

devices are used extensively internal to Eterna. However, high electrostatic

discharge can damage or degrade the device. Use proper ESD handling

precautions.

Note 3: Extended storage at high temperature is discouraged, as this

negatively affects the data retention of Eterna’s calibration data. See

FLASH Data Retention section for details.

Note 4: Actual RF range is subject to a number of installation-specific

variables including, but not restricted to ambient temperature, relative

humidity, presence of active interference sources, line-of-sight obstacles,

and near-presence of objects (for example, trees, walls, signage, and so

on) that may induce multipath fading. As a result, range varies.

Note 5: As specified by IEEE Std. 802.15.4-2006: Wireless Medium

Access Control (MAC) and Physical Layer (PHY) specifications for Low-

Rate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee.

org/findstds/standard/802.15.4-2011.html.

Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a

frequency tolerance of better than ±40ppm.

Note 7: Per pin I/O types are provided in the Pin Functions section.

Note 8: VIH maximum voltage input must respect the VSUPPLY maximum

voltage specification.

Note 9: See the SmartMesh IP Manager API Guide for the time indication

notification definition.

Note 10: Network time accuracy is a statistical measure and varies over

the temperature range, reporting rate and the location of the device relative

to the manager in the network. See Typical Performance Characteristics

section for a more detailed description.

Note 11: Code execution from flash banks being written or erased is

suspended until completion of the flash operation.

Note 12: Guaranteed by design. Not production tested.

exTernal bus ac characTerisTics

The l denotes the specifications which apply over the full

operating temperature range, otherwise specifications are at TA = 25°C and VSUPPLY = 3.6V unless otherwise noted. (Note 12)

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Typical perFormance characTerisTics

In mesh networks data can propagate from the manager

to the nodes, downstream, or from the motes to the man-

ager, upstream, via a sequence of transmissions from one

device to the next. As shown in Figure 8, data originating

from mote P1 may propagate to the manager directly or

through P2. As mote P1 may directly communicate with

the manager, mote P1 is referred to as a 1-hop mote. Data

originating from mote D1, must propagate through at least

one other mote, P2 or P1, and as a result is referred to as

a 2-hop mote. The fewest number of hops from a mote to

the manager determines the hop depth.

As described in the Application Time Synchronization section,

Eterna provides two mechanisms for applications to

maintain a time base across a network. The synchroniza-

tion performance plots that follow were generated using

the more precise TIMEn input. Publishing rate is the rate

a mote application sends upstream data. Synchroniza-

tion improves as the publishing rate increases. Baseline

synchronization performance is provided for a network

operating with a publishing rate of zero. Actual performance

for applications in network will improve as publishing

rates increase. All synchronization testing was performed

with the 1-hop mote inside a temperature chamber. Tim-

ing errors due to temperature changes and temperature

differences both between the manager and this mote and

between this mote and its descendents therefore propa-

gated down through the network. The synchronization

of the 3-hop and 5-hop motes to the manager was thus

affected by the temperature ramps even though they were

at room temperature. For 2°C/minute testing the tempera-

ture chamber was cycled between –40°C and 85°C at this

rate for 24 hours. For 8°C/minute testing, the temperature

chamber was rapidly cycled between 85°C and 45°C for

eight hours, followed by rapid cycling between –5°C and

45°C for eight hours, and lastly, rapid cycling between

–40°C and 15°C for eight hours.

Figure 8. Example Network Graph

Figure 7a. Supply Current vs Packet Rate

Figure 7b. Packet Latency vs Reporting Interval

PACKET RATE (PACKETS/s)

SUPPLY CURRENT (mA)

0.8

1.0

1.2

2.0

59012IPR F07a

0.6

0.4

0.2

1.6

1.8

1.4

5 10 15 20 25

REPORTING INTERVAL (s)

MEDIAN LATENCY (s)

1.0

1.5

2.5

59012IPR F07b

0.5

2.0

5 10 15 20 25

5 HOPS

4 HOPS

3 HOPS

2 HOPS

1 Hop

MANAGER

1 HOP

2 HOP

3 HOP

5800IPM F08

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Typical perFormance characTerisTics

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 2°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

1 Hop, 8°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 2°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

3 Hops, 8°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, Room Temperature

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 2°C/Min.

TIMEn Synchronization Error

0 Packet/s Publishing Rate,

5 Hops, 8°C/Min.

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G01

0–30 –20 0 10 20 30

60 µ = 0.0

σ = 0.9

N = 89700

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G02

0–30 –20 0 10 20 30

30 µ = –0.2

σ = 1.7

N = 89699

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G03

0–30 –20 0 10 20 30

14 µ = –0.2

σ = 3.6

N = 89698

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G04

0–30 –20 0 10 20 30

20 µ = 1.5

σ = 3.3

N = 93812

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G05

0–30 –20 0 10 20 30

14 µ = 0.9

σ = 3.9

N = 93846

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G06

0–30 –20 0 10 20 30

7µ = 1.0

σ = 7.7

N = 93845

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G07

0–30 –20 0 10 20 30

12 µ = 3.6

σ = 5.0

N = 88144

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G08

0–30 –20 0 10 20 30

µ = 1.1

σ = 3.8

N = 88179

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G09

0–30 –20 0 10 20 30

µ = 1.0

σ = 7.4

N = 88178

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Typical perFormance characTerisTics

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G10

0–30 –20 0 10 20 30

µ = 0.0

σ = 1.2

N = 22753

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G11

00 –30 –20 0 10 20 30

µ = –0.2

σ = 1.2

N = 17008

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G12

0–30 –20 0 10 20 30

50 µ = –0.2

σ = 1.2

N = 17007

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G13

0–30 –20 0 10 20 30

35 µ = 0.5

σ = 1.9

N = 85860

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G13

0–30 –20 0 10 20 30

45 µ = 0.1

σ = 1.5

N = 85858

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G15

0–30 –20 0 10 20 30

µ = 0.1

σ = 1.5

N = 85855

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G16

0–30 –20 0 10 20 30

µ = 0.2

σ = 1.4

N = 33932

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G17

0–30 –20 0 10 20 30

µ = 0.0

σ = 1.3

N = 33930

SYNCHRONIZATION ERROR (µs)

–40

NORMALIZED FREQUENCY OF OCCURANCE (%)

–10 40

59012IPR G18

0–30 –20 0 10 20 30

µ = –1.0

σ = 1.3

N = 33929

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 2°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

1 Hop, 8°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 2°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

3 Hops, 8°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, Room Temperature

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 2°C/Min.

TIMEn Synchronization Error

1 Packet/s Publishing Rate,

5 Hops, 8°C/Min.

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Typical perFormance characTerisTics

As described in the SmartMesh Network Overview sec-

tion, devices in network spend the vast majority of their

time inactive in their lowest power state (Doze). On a

synchronous schedule a mote will wake to communicate

with another mote. Regularly occurring sequences which

wake, perform a significant function and return to sleep

are considered atomic. These operations are considered

atomic as the sequence of events can not be separated

into smaller events while performing a useful function.

For example, transmission of a packet over the radio is an

atomic operation. Atomic operations may be characterized

in either charge or energy. In a time slot where a mote

successfully sends a packet, an atomic transmit includes

setup prior to sending the message, sending the message,

receiving the acknowledgment and the post processing

needed as a result of the message being sent. Similarly

in a time slot when a mote successfully receives a packet,

an atomic receive includes setup prior to listening, listen-

ing until the start of the packet transition, receiving the

packet, sending the acknowledge and the post processing

required due to the arrival of the packet.

To ensure reliability each mote in the network is provided

multiple time slots for each packet it nominally will send

and forward. The time slots are assigned to communicate

upstream with at least two different motes. When combined

with frequency hopping this provides temporal, spatial

and spectral redundancy. Given this approach a mote will

often listen for a message that it will never receive, since

the time slot is not being used by the transmitting mote.

It has already successfully transmitted the packet. Since

typically three timeslots are scheduled for every one packet

to be sent or forwarded, motes will perform more of these

atomic idle listens than atomic transmit or atomic receive

sequences. Examples of transmit, receive and idle listen

atomic operations are shown below.

LTP5901-IPR/LTP5902-IPR

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For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

Typical perFormance characTerisTics

Figure 9.

LTP5901-IPR/LTP5902-IPR

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For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

pin FuncTions

NO POWER SUPPLY TYPE I/O PULL DESCRIPTION

1 GND Power - - Ground Connection

11 GND Power - - Ground Connection

20 GND Power - - Ground Connection

30 GND Power - - Ground Connection

34 GND Power - - Ground Connection

37 GND Power - - Ground Connection

42 GND Power - - Ground Connection

56 GND Power - - Ground Connection

66 GND Power - - Ground Connection

55 VSUPPLY Power - - Power Supply Input to Eterna

The following table organizes the pins by functional

groups. For those I/O with multiple functions the alternate

functions are shown on the second and third line in their

respective row. The No column provides the pin number.

The second column lists the function. The Type column

lists the I/O type. The I/O column lists the direction of the

signal relative to Eterna. The Pull column shows which

signals have a fixed passive pull-up or pull-down. The

Description column provides a brief signal description.

NO RADIO TYPE I/O PULL DESCRIPTION

64 RADIO_INHIBIT

GPIO15

1 (Note 13) I

I/O

Radio Inhibit

General Purpose Digital I/O

4GPIO17 1 I/O -General Purpose Digital I/O

5GPIO18 1 I/O -General Purpose Digital I/O

6GPIO19 1 I/O -General Purpose Digital I/O

- ANTENNA N/A N/A - Chip Antenna (LT P 5901) or MMCX Connector (LPT5902)

NO ANALOG TYPE I/O PULL DESCRIPTION

7AI_2 Analog I - Analog Input 2

8AI_1 Analog I - Analog Input 1

9AI_3 Analog I - Analog Input 3

10 AI_0 Analog I - Analog Input 0

NO RESET TYPE I/O PULL DESCRIPTION

15 RESETn 1 I UP Reset Input, Active Low

NO JTAG TYPE I/O PULL DESCRIPTION

16 TDI 1 I UP JTAG Test Data In

17 TDO 1 O - JTAG Test Data Out

18 TMS 1 I UP JTAG Test Mode Select

19 TCK 1 I DOWN JTAG Test Clock

Pin functions shown in italics are currently not supported in software.

LTP5901-IPR/LTP5902-IPR

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For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

pin FuncTions

NO SPECIAL PURPOSE TYPE I/O PULL DESCRIPTION

63 TIMEn 1 (Note 13) I - Time Capture Request, Active Low

NO CLI AND EXTERNAL MEMORY TYPE I/O PULL DESCRIPTION

25 EB_DATA_7 1 I/O - External Bus Data Bit 7

26 EB_DATA_6 1 I/O - External Bus Data Bit 6

27 EB_DATA_4 1 I/O - External Bus Data Bit 4

28 EB_DATA_0 1 I/O - External Bus Data Bit 0

31 UARTC0_TX

EB_IO_LE0

2 O

- CLI UART 0 T

ransmit

External Bus I/O Latch Enable 0 for External Address Bits A[9:2]

32 UARTC0_RX

EB_DATA_1

1 I

I/O

- CLI UART 0 Receive

External Bus Data Bit 1

38 EB_IO_LE2 1 O - External Bus I/O Latch Enable 2 for External Address Bits A[25:18]

40 EB_ADDR_1 2 O - External Bus Address Bit 1

41 EB_ADDR_0 2 O - External Bus Address Bit 0

43 EB_DATA_3 1 I/O - External Bus Data Bit 3

44 EB_DATA_2 1 I/O - External Bus Data Bit 2

45 EB_DATA_5 1 I/O - External Bus Data Bit 5

46 EB_IO_CS0n 2 O - External Bus Chip Select 0

47 UARTC1_TX 2 O - CLI UART 1 Transmit

48 UARTC1_RX 1 I - CLI UART 1 Receive

49 EB_IO_WEn 2 O - External Bus Write Enable Strobe

50 EB_IO_OEn 2 O - External Bus Output Enable Strobe

NO IPCS SPI/FLASH PROGRAMMING (NOTE 14) TYPE I/O PULL DESCRIPTION

33 IPCS_MISO 2 O - SPI Flash Emulation (MISO) Master in Slave Out Port

35 IPCS_MOSI 1 I - SPI Flash Emulation (MOSI) Master Out Slave in Port

36 IPCS_SCK 1 I - SPI Flash Emulation (SCK) Serial Clock Port

39 IPCS_SSn 1 I - SPI Flash Emulation Slave Select, Active Low

51 FLASH_P_ENn

EB_IO_LE1

1 I

Flash Program Enable, Active Low

External Bus I/O Latch Enable 1

NO API UART TYPE I/O PULL DESCRIPTION

57 UART_RX_RTSn 1 (Note 13) I - UART Receive (RTS) Request to Send, Active Low

58 UART_RX_CTSn 1 O - UART Receive (CTS) Clear to Send, Active Low

59 UART_RX 1 (Note 13) I - UART Receive

60 UART_TX_RTSn 1 O - UART Transmit (RTS) Request to Send, Active Low

61 UART_TX_CTSn 1 (Note 13) I - UART Transmit (CTS) Clear to Send, Active Low

62 UART_TX 2 O - UART Transmit

Note 13: These inputs are always enabled and must be driven or pulled to

a valid state to avoid leakage.

Note 14: Embedded programming over the IPCS SPI bus is only available

when RESETn is asserted.

Pin functions shown in italics are currently not supported in software.

LTP5901-IPR/LTP5902-IPR

59012iprf

For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

pin FuncTions

VSUPPLY: System and I/O Power Supply. Provides power

to the module. The digital-interface I/O voltages are also

set by this voltage.

ANTENNA: Multiplexed Receiver Input and Transmitter

Output Pin. The impedance presented to the MMCX connec-

tor should be 50Ω, single-ended with respect to ground.

RESETn: The asynchronous reset signal is internally pulled

up. Resetting Eterna will result in the ARM Cortex-M3

rebooting and loss of network connectivity. Use of this

signal for resetting Eterna is not recommended, except

during power-on and in-circuit programming.

RADIO_INHIBIT: RADIO_INHIBIT provides a mechanism

for an external device to temporarily disable radio operation.

Failure to observe the timing requirements defined in the

RADIO_INHIBIT AC Characteristics section, may result

in unreliable netowrk operation. In designs where the

RADIO_INHIBIT function is not needed the input must

either be tied, pulled or actively driven low to avoid excess

leakage.

TMS, TCK, TDI, TDO: JTAG port supporting software

debug and boundary scan.

SLEEPn: The SLEEPn function is not currently supported

in software. The SLEEPn input must either be tied, pulled

or actively driven high to avoid excess leakage.

UART_RX, UART_RX_RTSn, UART_RX_CTSn, UART_TX,

UART_TX_RTSn, UART_TX_CTSn: The API UART interface

includes bi-directional wake up and flow control. Unused

input signals must be driven or pulled to their inactive state.

TIMEn: Strobing the TIMEn input is the most accurate meth-

od to acquire the network time maintained by Eterna. Eterna

latches the network timestamp with sub-microsecond

resolution on the rising edge of the TIMEn signal and

produces a packet on the API serial port containing the

timing information.

UARTC0_RX, UARTC0_TX, UARTC1_RX, UARTC1_TX:

The CLI UART provides a mechanism for monitoring,

configuration and control of Eterna during operation. On

the LT P 5901/2-IPR CLI UART 0 is used when Eterna is not

configured to support external RAM and CLI UART 1 is

used when Eterna is configured to support external RAM.

For a complete description of the supported commands

see the SmartMesh IP Manager CLI Guide.

EB_DATA_0 through EB_DATA_7, EB_ADDR_0, EB_

ADDR_1, EB_IO_LE1 through EB_IO_LE2, EB_IO_CS0n,

EB_IO_WEn, EB_IO_ENn: The external bus provides a

multiplexed address data bus enabling the Cortex-M3

direct access of external byte wide RAM. The additional

RAM is used by network management software enabling

the support of a larger network of motes with higher packet

throughput. To support the addressing needed, each

latch signal, EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 will

strobe to latch 8-bits of address from the EB_DATA[7:0]

bus. EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 correspond

to addres bits [9:2], [17:10] and [25:18] respectively.

EB_ADDR_0 and EB_ADDR_1 correspond to the lower

two bits of address. For systems with 256k bytes or less

EB_IO_LE2 can be ignored. EB_IO_CS0n, EB_IO_WEn and

EB_IO_OEn provide chip select, write enable and output

enable control of the external RAM.

FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO,

IPCS_SSn: The In-circuit programming control system

(IPCS) bus enables in-circuit programming of Eterna’s flash

memory. IPCS_SCK is a clock and should be terminated

appropriately for the driving source to prevent overshoot

and ringing.

LTP5901-IPR/LTP5902-IPR

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For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR

operaTion

The LT P 5901/LT P 5902 is the world’s most energy-efficient

IEEE 802.15.4 compliant platform, enabling battery and

energy harvested applications. With a powerful 32-bit ARM

Cortex-M3, best-in-class radio, flash, RAM and purpose-

built peripherals, Eterna provides a flexible, scalable and

robust networking solution for applications demanding

minimal energy consumption and data reliability in even

the most challenging RF environments.

Shown in Figure 10, Eterna integrates purpose-built pe-

ripherals that excel in both low operating-energy consump-

tion and the ability to rapidly and precisely cycle between

operating and low power states. Items in the gray shaded

region labeled analog core correspond to the analog/RF

components.

Figure 10. Eterna Block Diagram

4-BIT

DAC

VGA

BPF PPF

AGC

LPF

ADC

DAC

10-BIT

ADC

PLL

RSSI

LNA

20MHz

32kHz

32kHz, 20MHz

PTAT

59012IPR F10

BAT

LOAD

LIMITER

VOLTAGE REFERENCE

ANALOG COREDIGITAL CORE

CORE REGULATOR

CLOCK REGULATOR

ANALOG REGULATOR

DC/DC

CONVERTER

PRIMARY

DC/DC

CONVERTER

RELAXATION

OSCILLATOR

PoR

TIMERS

SCHED

SRAM

72kB

FLASH

512kB

FLASH

CONTROLLER

CODE

AES

AUTO

MAC

802.15.4

MOD

802.15.4

FRAMING

DMA

IPCS

SPI

SLAVE

CLI

UART

(2 PIN)

API

UART

(6 PIN)

ADC

CTRL

802.15.4

DEMOD

SYSTEM

PMU/

CLOCK

CONTROL

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POWER SUPPLY

Eterna is powered from a single pin, VSUPPLY, which

powers the I/O cells and is also used to generate internal

supplies. Eterna’s two on-chip DC/DC converters minimize

Eterna’s energy consumption while the device is awake. To

conserve power the DC/DC converters are disabled when

the device is in low power state. Eterna’s integrated power

supply conditioning architecture, including the two inte-

grated DC/DC converters and three integrated low dropout

regulators, provides excellent rejection of supply noise.

Eterna’s operating supply voltage range is high enough

to support direct connection to lithium-thionyl chloride,

Li-SOCl2, sources and wide enough to support battery

operation over a broad temperature range.

SUPPLY MONITORING AND RESET

Eterna integrates a power-on reset (PoR) circuit. As the

RESETn input pin is nominally configured with an internal

pull-up resistor, no connection is required. For a graceful

shutdown, the software and the networking layers should

be cleanly halted via API commands prior to assertion of

the RESETn pin. See the SmartMesh IP Manager API Guide

for details on the disconnect and reset commands. Eterna

includes a soft brown-out monitor that fully protects the

flash from corruption in the event that power is removed

while writing to flash. Integrated flash supervisory func-

tionality, in conjunction with a fault tolerant file system,

yields a robust non-volatile storage solution.

PRECISION TIMING

A major feature of Eterna over competing 802.15.4 prod-

uct offerings is its low power dedicated timing hardware

and timing algorithms. This functionality provides timing

precision two to three orders of magnitude better than

any other low power solution available at the time of

publication. Improved timing accuracy allows motes to

minimize the amount of radio listening time required to

ensure packet reception thereby lowering even further

the power consumed by SmartMesh networks. Eterna’s

patented timing hardware and timing algorithms provide

superior performance over rapid temperature changes,

further differentiating Eterna’s reliability when compared

with other wireless products. In addition, precise timing

enables networks to reduce spectral dead time, increasing

total network throughput.

APPLICATION TIME SYNCHRONIZATION

In addition to coordinating timeslots across the network,

which is transparent to the user, Eterna’s timing manage-

ment is used to support two mechanisms to share network

time. Having an accurate, shared, network-wide time base

enables events to be accurately time stamped or tasks to

be performed in a synchronized fashion across a network.

Eterna will send a time packet through its serial interface

when one of the following occurs:

• Eterna receives an API request to read time

• The TIMEn signal is asserted

The use of TIMEn has the advantage of being more accurate.

The value of the timestamp is captured in hardware relative

to the rising edge of TIMEn. If an API request is used, due

to packet processing, the value of the timestamp may be

captured several milliseconds after receipt of the packet due

to packet processing. See section TIMEn AC Characteristics,

for the time function’s definition and specifications.

TIME REFERENCES

Eterna includes three clock sources: an internal relaxation

oscillator, a low power oscillator designed for a 32.768kHz

crystal, and the radio reference oscillator designed for a

20MHz crystal.

Relaxation Oscillator

The relaxation oscillator is the primary clock source for

Eterna, providing the clock for the CPU, memory subsys-

tems, and all peripherals. The internal relaxation oscillator

is dynamically calibrated to 7.3728MHz. The internal re-

laxation oscillator typically starts up in a few μs, providing

an expedient, low energy method for duty cycling between

active and low power states. Quick start-up from the doze

state, defined in the State Diagram section, allows Eterna to

wake up and receive data over the UART and SPI interfaces

by simply detecting activity on the appropriate signals.

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32.768kHz Crystal

Once Eterna is powered up and the 32.768kHz crystal

source has begun oscillating, the 32.768kHz crystal re-

mains operational while in the active state, and is used as

the timing basis when in doze state. See the State Diagram

section, for a description of Eterna’s operational states.

20MHz Crystal

The 20MHz crystal source provides a frequency reference

for the radio, and is automatically enabled and disabled

by Eterna as needed.

RADIO

Eterna includes the lowest power commercially available

2.4GHz IEEE 802.15.4e radio by a substantial margin.

(Please refer to section Radio Specifications, for power

consumption numbers). Eterna’s integrated power ampli-

fier is calibrated and temperature-compensated to con-

sistently provide power at a limit suitable for worldwide

radio certifications. Additionally, Eterna uniquely includes

a hardware-based autonomous MAC that handles precise

sequencing of peripherals, including the transmitter, the

receiver, and advanced encryption standard (AES) pe-

ripherals. The hardware-based autonomous media access

controller (MAC) minimizes CPU activity, thereby further

decreasing power consumption.

UARTS

The principal network interface is through the application

programming interface (API) UART. A command-line

interface (CLI) is also provided for support of test and

debug functions. Both UARTs sense activity continuously,

consuming virtually no power until data is transferred over

the port and then automatically returning to their lowest

power state after the conclusion of a transfer. The defini-

tion for packet encoding on the API UART interface can

be found in the SmartMesh IP Manager API Guide and the

CLI command definitions can be found in the SmartMesh

IP Manager CLI Guide.

API UART PROTOCOL

The API UART protocol was created with the goal of

supporting a wide range of companion multipoint control

units (MCUs) while reducing power consumption of the

system. The receive half of the API UART protocol includes

two additional signals in addition to UART_RX: UART_RX_

RTSn and UART_RX_CTSn. The transmit half of the API

UART protocol includes two additional signals in addition

to UART_TX: UART_TX_RTSn and UART_TX_CTSn. The

API UART protocol is referred to as Mode 4.

In the figures accompanying the protocol descriptions,

signals driven by the companion processor are drawn

in black and signals driven by Eterna are drawn in blue.

UART Mode 4

UART Mode 4 incorporates level-sensitive flow control

on the TX channel and requires no flow control on the

RX channel, supporting 115200 baud. The use of level-

sensitive flow control signals enables higher data rates

with the option of using a reduced set of the flow control

signals; however, with the companion processor must

negate UART_TX_CTSn prior to the end of the packet and

waiting at least tRX_RTS to RX_CTS between packets, see

the UART AC Characteristics section for complete timing

specifications. Packets are HDLC encoded with one stop

bit and no parity bit. The use of the RX flow control signals

(UART_RX_RTSn and UART_RX_CTSn) for Mode 4 are

optional. The flow control signals for the TX channel are

shown in Figure 11 UART Mode 4 Transmit Flow Control.

Transfers are initiated by Eterna asserting UART_TX_RTSn.

The UART_TX_CTSn signal may be actively driven by the

companion processor when ready to receive a packet

or UART_TX_CTSn may be tied low if the companion

processor is always ready to receive a packet. After

detecting a logic ‘0’ on UART_TX_CTSn Eterna sends the

entire packet. Following the transmission of the final byte

in the packet Eterna negates UART_TX_RTSn and waits for

a minimum period defined in the UART AC Characteristics

section before asserting UART_TX_RTSn again.

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Figure 11. UART Mode 4 Transmit Flow Control

operaTion

For details on the timing of the UART protocol, see the

UART AC Characteristics section.

curity protocols is significant in terms of both engineering

effort and market value in an OEM product. Eterna system

solutions provide a FIPS-197 validated encryption scheme

that includes authentication and encryption at the MAC

and network layers with separate keys for each mote.

This not only yields end-to-end security, but if a mote is

somehow compromised, communication from other motes

is still secure. A mechanism for secure key exchange al-

lows keys to be kept fresh. To prevent physical attacks,

Eterna includes hardware support for electronically locking

devices, thereby preventing access to Eterna’s flash and

RAM memory and thus the keys and code stored therein.

TEMPERATURE SENSOR

Eterna includes a calibrated temperature sensor on chip.

The temperature readings are available locally through

Eterna’s serial API, in addition to being available via the

network manager. The performance characteristics of

the temperature sensor can be found in the Temperature

Sensor Characteristics section.

RADIO INHIBIT

The RADIO_INHIBIT input enables an external controller

to temporarily disable the radio software drivers (for

example, to take a sensor reading that is susceptible to

radio interference). When RADIO_INHIBIT is asserted

the software radio drivers will disallow radio operations

including clear channel assessment, packet transmits,

or packet receipts. If the radio is active in the current

timeslot when RADIO_INHIBIT is asserted the radio will be

diabled after the present operation completes. For details

on the timing associated with RADIO_INHIBIT, see the

RADIO_INHIBIT AC Characteristics section.

FACTORY INSTALLED SOFTWARE

This product is provided with software programmed into

the device. Devices can be configured via either the CLI

or API ports. Configuration commands and settings are

defined in SmartMesh IP Manager API Guide and Smart-

Mesh IP Manager CLI Guide.

CLI UART

The command line interface (CLI) UART port is a two

wire protocol (TX and RX) that operates at a fixed 9600

baud rate with one stop bit and no parity. The CLI UART

interface is intended to support command line instructions

and response activity.

AUTONOMOUS MAC

Eterna was designed as a system solution to provide a

reliable, ultralow power, and secure network. A reliable

network capable of dynamically optimizing operation

over changing environments requires solutions that are

far too complex to completely support through hardware

acceleration alone. As described in the Precision Timing

section, proper time management is essential for optimizing

a solution that is both low power and reliable. To address

these requirements Eterna includes the autonomous MAC,

which incorporates a co-processor for controlling all of

the time-critical radio operations. The autonomous MAC

provides two benefits: first, preventing variable software

latency from affecting network timing and second, greatly

reducing system power consumption by allowing the CPU

to remain inactive during the majority of the radio activity.

The autonomous MAC, provides software-independent

timing control of the radio and radio-related functions,

resulting in superior reliability and exceptionally low power.

SECURITY

Network security is an often overlooked component of a

complete network solution. Proper implementation of se-

59012IPR F11

UART_TX BYTE 0 BYTE 1

UART_TX_CTSn

UART_TX_RTSn

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Figure 12. Eterna State Diagram

FLASH DATA RETENTION

Eterna contains internal flash (non-volatile memory) to

store calibration results, unique ID, configuration settings

and software images. Flash retention is specified over the

operating temperature range. See Electrical Characteristics

and Absolute Maximum Ratings sections.

Non destructive storage above the operating temperature

range of –40°C to 85°C is possible; although, this may

result in a degradation of retention characteristics.

The degradation in flash retention for temperatures >85°C

can be approximated by calculating the dimensionless

acceleration factor using the following equation.

AF =e









•1

TUSE+273 −1

TSTRESS+273























SERIAL FLASH

EMULATION

LOAD FUSE

SETTINGS

RESETn LOW AND

FLASH_P_ENn HIGH

RESETn HIGH

AND

FLASH_P_ENn

HIGH

RESET

DEASSERT

RESETn

CPU AND

PERIPHERALS

INACTIVE

HW OR PMU EVENT

BOOT

START-UP

OPERATION INACTIVE

DOZE DEEP SLEEP

LOW POWER SLEEP

COMMAND

59012IPR F12

ASSERT RESETn

ASSERT RESETnASSERT RESETn

CPU

ACTIVE

CPU

INACTIVE

POWER-ON

RESET

RESETn LOW AND

FLASH_P_ENn LOW

SET RESETn HIGH AND

FLASH_P_ENn HIGH

FOR 125µs, THEN

SET RESETn LOW

VSUPPLY > PoR

ACTIVE

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key advantages of SmartMesh networking solutions is the

network manager is aware of and tracking the success

or failure of every packet transaction, so not only can the

network be optimized, but the solution can be rigorously

tested to produce a system solution with better than

99.999% reliability.

Deterministic Power Management

Deterministic power management balances traffic in the

network by diverting traffic around heavily loaded motes

(for example, motes with high reporting rates). In do-

ing so, it reduces power consumption for these motes

and balances power consumption across the network.

Deterministic power management provides predictable

maintenance schedules to prevent down time and lower

the cost of network ownership. When combined with field

devices using Eterna’s industry-leading low power radio

technology, deterministic power management enables

over a decade of battery life for network motes.

Intelligent Routing

Intelligent routing provides each packet with an optimal

path through the network. The shortest distance between

two points is a straight line, but in RF the quickest path is

not always the one with the fewest hops. Intelligent routing

finds optimal paths by considering the link quality (one

path may lose more packets than another) and the retry

schedule, in addition to the number of hops. The result

is reduced network power consumption, elimination of

in-network collisions, and unmatched network scalability

and reliability.

Configurable Bandwidth Allocation

Smartmesh networks provide configurations that enable

users to make bandwidth and latency versus power trade-

offs both network-wide and on a per device basis. This

flexibly enables solutions that tailored to the application

requirements, such as request/response, fast file trans-

fer, and alerting. Relevant configuration parameters are

described in the SmartMesh IP Users Guide. The design

trade-offs between network performance and current

consumption are supported via the SmartMesh Power

and Performance Estimator.

Where:

AF = acceleration factor

Ea = activation energy = 0.6eV

k=8.625•10–5eV/°K

TUSE = is the specified temperature retention in °C

TSTRESS = actual storage temperature in °C

Example: Calculate the effect on retention when storing

at a temperature of 105°C.

TSTRESS = 105°C

TUSE = 85°C

AF = 2.8

So the overall retention of the flash would be degraded

by a factor of 2.8, reducing data retention from 20 years

at 85°C to 7.1 years at 105°C.

NETWORKING

The LT P 5901-IPR/LT P 5902-IPR network manager pro-

vides the ingress/egress point for at the wired to wireless

mesh network boundary, via the API UART interface. The

complexity of the mesh network management is handled

entirely within the embedded software, which provides

dynamic network optimization, deterministic power man-

agement, intelligent routing, and configurable bandwidth

allocation while achieving carrier class data reliability and

low power operation.

Dynamic Network Optimization

Dynamic network optimization allows Eterna to address the

changing RF requirements in harsh industrial environments

resulting in a network that is continuously self-monitoring

and self-adjusting. The manager performs dynamic network

optimization based upon periodic reports on network health

and link quality that it receives from the network motes.

The manager uses this information to provide performance

statistics to the application layer and proactively solve

problems in the network. Dynamic network optimization

not only maintains network health, but also allows Eterna

to deliver deterministic power management. One of the

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IP Manager Options

The IP manager is offered in three different dash code

options, the -IPRA, -IPRB and -IPRC. The -IPRA option

supports managing networks of 32 motes or less with a

packet throughput of 24 packets per second.The -IPRB

option supports managing networks of 100 motes or

less with a packet throughput of 36 packets per second.

The -IPRC option supports managing networks of 32

motes or less with a packet throughput of 36 packets

per second. The -IPRA option does not support the use

of external SRAM. The -IPRB and -IPRC options require

the use of external SRAM, as described in the LT P 5901

and LT P 5902 Integration Guide. -IPRC managers can be

upgraded to support managing networks of up to 100

motes by purchasing a software license key as described

in the SmartMesh IP Users Guide.

State Diagram

In order to provide capabilities and flexibility in addition

to ultra low power, Eterna operates in various states, as

shown in Figure 10 Eterna State Diagram and described

in this section. State transitions shown in red are not

recommended.

Start-Up

Start-up occurs as a result of either crossing the power-on

reset threshold or asserting RESETn. After the completion

of power-on reset or the falling edge of an internally

synchronized RESETn, Eterna loads its fuse table which,

as described in the previous section, includes setting

I/O direction. In this state, Eterna checks the state of

the FLASH_P_ENn and RESETn and enters the serial

flash emulation mode if both signals are asserted. If the

FLASH_P_ENn pin is not asserted but RESETn is asserted,

Eterna automatically reduces its energy consumption to

a minimum until RESETn is released. Once RESETn is

de-asserted, Eterna goes through a boot sequence, and

then enters the active state.

Serial Flash Emulation

When both RESETn and FLASH_P_ENn are asserted,

Eterna disables normal operation and enters a mode to

emulate the operation of a serial flash. In this mode, its

flash can be programmed.

Operation

Once Eterna has completed start-up, Eterna transitions to

the operational group of states (active/CPU active, active/

CPU inactive, and Doze). There, Eterna cycles between the

various states, automatically selecting the lowest pos-

sible power state while fulfilling the demands of network

operation.

Active State

In the active state, Eterna’s relaxation oscillator is running

and peripherals are enabled as needed. The ARM Cortex-

M3 cycles between CPU-active and CPU-inactive (referred

to in the ARM Cortex-M3 literature as sleep now mode).

Eterna’s extensive use of DMA and intelligent peripherals

that independently move Eterna between active state and

doze state minimizes the time the CPU is active, signifi-

cantly reducing Eterna’s energy consumption.

Doze State

The doze state consumes orders of magnitude less cur-

rent than the active state and is entered when all of the

peripherals and the CPU are inactive. In the Doze state

Eterna’s full state is retained, timing is maintained, and

Eterna is configured to detect, wake, and rapidly respond

to activity on I/Os (such as UART signals and the TIMEn

pin). In the doze state the 32.768kHz oscillator and as-

sociated timers are active.

operaTion

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REGULATORY AND STANDARDS COMPLIANCE

Radio Certification

The LT P 5901 and LT P 5902 have been certified under a

single modular certification, with the module name of

ETERNA2. Following the regulatory requirements provided

in the ETERNA2 Users Guide can enable customers to

ship products in the supported geographies, by simply

completing an unintentional radiator scan of the finished

product(s). The ETERNA2 Users Guide also provides the

technical information needed to enable customers to fur-

ther certify either the modules or products based upon the

modules in geographies that have not or do not support

modular certification.

Compliance to Restriction of Hazardous Substances

(RoHS)

Restriction of hazardous substances 2(RoHS 2) is a

directive that places maximum concentration limits on

the use of certain hazardous substances in electrical and

electronic equipment. Linear Technology is committed to

meeting the requirements of the European Community

directive 2011/65/EU.

This product has been specifically designed to utilize

RoHS-compliant materials and to eliminate or reduce the

use of restricted materials to comply with 2011/65/EU.

applicaTions inFormaTion

The RoHS-compliant design features include:

• RoHS-compliant solder for solder joints

• RoHS-compliant base metal alloys

• RoHS-compliant precious metal plating

• RoHS-compliant cable assemblies and connector

choices

• Halogen-free mold compound

• RoHS-compliant and 245°C re-flow compatible

Note: Customers may elect to use certain types of lead-

free solder alloys in accordance with the European Com-

munity directive 2011/65/EU. Depending on the type of

solder paste chosen, a corresponding process change to

optimize reflow temperatures may be required.

SOLDERING INFORMATION

The LT P 5901 and LT P 5902 are suitable for both eutectic

PbSn and RoHS-6 reflow. The maximum reflow solder-

ing temperature is 260°C. A more detailed description of

layout recommendations, assembly procedures and design

considerations is included in the LT P 5901 and LT P 5902

Hardware Integration Guide.