LTP5901-IPR/LTP5902-IPR SmartMesh IP Network Manager 2.4GHz 802.15.4e Wireless Embedded Manager Description Network Features Complete Radio Transceiver, Embedded Processor, and Networking Software for Forming a Self-Healing Mesh Network n SmartMesh(R) Networks Incorporate: n Time Synchronized Network-Wide Scheduling n Per Transmission Frequency Hopping n Redundant Spatially Diverse Topologies n Network-Wide Reliability and Power Optimization n NIST Certified Security n SmartMesh Networks Deliver: n >99.999% Network Reliability Achieved in the Most Challenging RF Environments n Sub 50A Routing Nodes n Compliant to 6LoWPAN Internet Protocol (IP) and IEEE 802.15.4e Standards n LTP5901/2-IPR Features n n n n Manages Networks of Up to 32 Nodes (LTP5901/2IPRA) or Up to 100 Nodes (LTP5901/2-IPRB) Sub 1mA Average Current Consumption Enables Battery Powered Network Management RF Modular Certification Include USA, Canada, EU, Japan, Taiwan, Korea, India, Australia and New Zealand PCB Assembly with Chip Antenna (LTP5901-IPR) or with MMCX Antenna Connector (LTP5902-IPR) SmartMesh IPTM wireless sensor networks are self managing, low power internet protocol (IP) networks built from wireless nodes called motes. The LTPTM5901-IPR/ LTP5902-IPR is the IP manager product in the Eterna(R)* family of IEEE 802.15.4e printed circuit board assembly solutions, featuring a highly integrated, low power radio design by Dust Networks(R) as well as an ARM Cortex-M3 32-bit microprocessor running Dust's embedded SmartMesh IP networking software. Based on the IETF 6LoWPAN and IEEE-802.15.4e standards, the LTP5901/2-IPR runs SmartMesh IP network management software to monitor and manage network performance and provide a data ingress/egress point via a UART interface. The SmartMesh IP software provided with the LTP5901/2-IPR is fully tested and validated, and is readily configured via a software application programming interface. With Dust's time-synchronized SmartMesh IP networks, all motes in the network may route, source or terminate data, while providing many years of battery powered operation. SmartMesh IP motes deliver a highly flexible network with proven reliability and low power performance in an easy-to-integrate platform. L, LT, LTC, LTM, Linear Technology, Dust, Dust Networks, Eterna, SmartMesh and the Linear logo are registered trademarks and LTP, SmartMesh IP and the Dust Networks logo are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7375594, 7420980, 7529217, 7791419, 7881239, 7898322, 8222965. * Eterna is Dust Networks' low power radio SoC architecture. Typical Application EXPANDED VIEW LTP5901-IPR LTP5901/2-IPM ANTENNA UART IN+ LTC(R)2379-18 SPI SENSOR CONTROLLER UART IN- HOST APPLICATION MOTE 59012IPR TA01 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 1 LTP5901-IPR/LTP5902-IPR Table of Contents Network Features........................................... 1 LTP5901/2-IPR Features................................... 1 Typical Application ......................................... 1 Description.................................................. 1 SmartMesh Network Overview............................ 3 Absolute Maximum Ratings............................... 4 Pin Configuration........................................... 4 Order Information........................................... 5 Recommended Operating Conditions.................... 5 DC Characteristics.......................................... 5 Radio Specifications....................................... 6 Radio Receiver Characteristics........................... 6 Radio Transmitter Characteristics........................ 7 Digital I/O Characteristics................................. 7 Temperature Sensor Characteristics..................... 7 System Characteristics.................................... 8 UART AC Characteristics................................... 8 Time AC Characteristics................................... 9 Radio_INHIBIT AC Characteristics...................... 10 Flash AC Characteristics.................................. 10 Flash SPI Slave AC Characteristics..................... 10 External Bus AC Characteristics......................... 11 Typical Performance Characteristics................... 14 Pin Functions............................................... 19 Operation................................................... 22 Power Supply...........................................................23 Supply Monitoring and Reset..................................23 Precision Timing......................................................23 Application Time Synchronization...........................23 Time References......................................................23 Radio....................................................................... 24 UARTs...................................................................... 24 API UART Protocol.................................................. 24 CLI UART.................................................................25 Autonomous MAC....................................................25 Security...................................................................25 Temperature Sensor................................................25 Radio Inhibit............................................................25 Factory Installed Software.......................................25 Flash Data Retention................................................26 Networking.............................................................. 27 Applications Information................................. 29 Regulatory and Standards Compliance....................29 Soldering Information..............................................29 Related Documentation................................... 29 Package Description...................................... 30 Typical Application........................................ 32 Related Parts............................................... 32 59012iprf 2 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR SmartMesh Network Overview A SmartMesh network consists of a self-forming multi-hop, mesh of nodes, known as motes, which collect and relay data, and a network manager that monitors and manages network performance and security, and exchanges data with a host application. SmartMesh networks communicate using a time slotted channel hopping (TSCH) link layer, pioneered by Dust Networks. In a TSCH network, all motes in the network are synchronized to within less than a millisecond. Time in the network is organized into timeslots, which enables collision-free packet exchange and per-transmission channel-hopping. In a SmartMesh network, every device has one or more parents (e.g. mote 3 has motes 1 and 2 as parents) that provide redundant paths to overcome communications interruption due to interference, physical obstruction or multi-path fading. If a packet transmission fails on one path, the next retransmission may try on a different path and different RF channel. A network begins to form when the network manager instructs its onboard access point (AP) radio to begin sending advertisements--packets that contain information that enables a device to synchronize to the network and request to join. This message exchange is part of the security handshake that establishes encrypted communications between the manager or application, and mote. Once motes have joined the network, they maintain synchronization through time corrections when a packet is acknowledged. to the network manager in packets called health reports. The network manager uses health reports to continually optimize the network to maintain >99.999% data reliability even in the most challenging RF environments. The use of TSCH allows SmartMesh devices to sleep inbetween scheduled communications and draw very little power in this state. Motes are only active in timeslots where they are scheduled to transmit or receive, typically resulting in a duty cycle of < 1%. The optimization software in the network manager coordinates this schedule automatically. When combined with the Eterna low power radio, every mote in a SmartMesh network--even busy routing ones--can run on batteries for years. By default, all motes in a network are capable of routing traffic from other motes, which simplifies installation by avoiding the complexity of having distinct routers vs non-routing end nodes. Motes may be configured as non-routing to further reduce that particular mote's power consumption and to support a wide variety of network topologies. ALL NODES ARE ROUTERS. THEY CAN TRANSMIT AND RECEIVE. THIS NEW NODE CAN JOIN ANYWHERE BECAUSE ALL NODES CAN ROUTE. HOST APPLICATION 59012IPR SNO02 NETWORK MANAGER AP Mote 1 Mote 2 Mote 3 59012IPR SNO01 An ongoing discovery process ensures that the network continually discovers new paths as the RF conditions change. In addition, each mote in the network tracks performance statistics (e.g. quality of used paths, and lists of potential paths) and periodically sends that information At the heart of SmartMesh motes and network managers is the Eterna IEEE 802.15.4e System-on-Chip (SoC), featuring Dust Networks' highly integrated, low power radio design, plus an ARM Cortex-M3 32-bit microprocessor running SmartMesh networking software. The SmartMesh networking software comes fully compiled yet is configurable via a rich set of application programming interfaces (APIs) which allows a host application to interact with the network, e.g. to transfer information to a device, to configure data publishing rates on one or more motes, or to monitor network state or performance metrics. Data publishing can be uniform or different for each device, with motes being able to publish infrequently or faster than once per second as needed. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 3 LTP5901-IPR/LTP5902-IPR Absolute Maximum Ratings (Notes 1, 2) Supply Voltage on VSUPPLY...................................3.76V Input Voltage on AI_0/1/2/3 Inputs.........................1.80V Voltage on Any Digital I/O Pin..... -0.3V to VSUPPLY + 0.3V Input RF Level.......................................................10dBm Storage Temperature Range (Note 3)...... -55C to 105C Pin Configuration Operating Temperature Range LTP5901I/LPT5902I..............................-40C to 85C CAUTION: This part is sensitive to electrostatic discharge (ESD). It is very important that proper ESD precautions be observed when handling the LTP5901/LTP5902-IPR. Pin functions shown in italics are currently not supported in software. GND 1 66 GND RESERVED 2 65 NC NC 3 64 RADIO_INHIBIT GPIO17 4 63 TIMEn GPIO18 5 62 UART_TX GPIO19 6 61 UART_TX_CTSn AI_2 7 60 UART_TX_RTSn AI_1 8 59 UART_RX AI_3 9 58 UART_RX_CTSn AI_0 10 57 UART_RX_RTSn GND 11 56 GND RESERVED 12 55 VSUPPLY NC 13 54 RESERVED NC 14 53 NC RESETn 15 52 NC TDI 16 51 FLASH_P_ENn / EB_IO_LE1 TDO 17 50 EB_IO_OEn TMS 18 49 EB_IO_WEn TCK 19 48 RESERVED / UARTC1_RX GND 20 47 RESERVED / UARTC1_TX DP4 21 46 EB_IO_CS0n RESERVED 22 45 EB_DATA_5 RESERVED 23 44 EB_DATA_2 RESERVED EB_DATA_7 24 43 EB_DATA_3 25 42 GND EB_DATA_6 26 41 EB_ADDR_0 EB_DATA_4 27 40 EB_ADDR_1 EB_DATA_0 28 39 IPCS_SSn NC 29 38 EB_IO_LE2 GND 30 37 GND IPCS_SCK GND IPCS_MOSI 34 35 36 IPCS_MISO UARTCO_TX / EB_IO_LE0 UARTCO_RX / EB_DATA_1 31 32 33 PC PACKAGE 66-LEAD PCB 59012iprf 4 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Order Information LEAD FREE FINISH** PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTP5901IPC-IPRA???#PBF LTP5901IPC-IPRA???#PBF 66-Lead (42mm x 24mm x 5.5mm) PCB with Chip Antenna -40C to 85C LTP5901IPC-IPRB???#PBF LTP5901IPC-IPRB???#PBF 66-Lead (42mm x 24mm x 5.5mm) PCB with Chip Antenna -40C to 85C LTP5901IPC-IPRC???#PBF LTP5901IPC-IPRC???#PBF 66-Lead (42mm x 24mm x 5.5mm) PCB with Chip Antenna -40C to 85C LTP5902IPC-IPRA???#PBF LTP5902IPC-IPRA???#PBF 66-Lead (37.5mm x 24mm x 5.5mm) PCB with MMCX Connector -40C to 85C LTP5902IPC-IPRB???#PBF LTP5902IPC-IPRB???#PBF 66-Lead (37.5mm x 24mm x 5.5mm) PCB with MMCX Connector -40C to 85C LTP5902IPC-IPRC???#PBF LTP5902IPC-IPRC???#PBF 66-Lead (37.5mm x 24mm x 5.5mm) PCB with MMCX Connector -40C to 85C *The temperature grade is identified by a label on the shipping container. **The sofware version is indicated by ???. For specific ordering information, go to: www.linear.com/ltp5901-ipr#orderinfo or www.linear.com/ltp5902-ipr#orderinfo For a description of the dash options see the IP Manager Options section. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ Recommended Operating Conditions The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS VSUPPLY Supply Voltage Including Noise and Load Regulation l Supply Noise 50Hz to 2MHz l 250 mV Operating Relative Humidity Non-Condensing l 10 90 % RH l -8 8 C/min Temperature Ramp Rate While Operating in Network MIN TYP 2.1 MAX UNITS 3.76 V DC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. OPERATION/STATE CONDITIONS Power-On Reset During Power-On Reset, Maximum 750s + VSUPPLY Rise Time from 1V to 1.9V 12 mA Doze RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and State Retained, 32.768kHz Reference Active 1.2 A Deep Sleep RAM on, ARM Cortex-M3, Flash, Radio, and Peripherals Off, All Data and State Retained, 32.768kHz Reference Inactive 0.8 A 20 mA 30 26 mA mA 1.3 mA In-Circuit Programming RESETn and FLASH_P_ENn Asserted, IPCS_SCK at 8MHz Peak Operating Current 8dBm 0dBm System Operating at 14.7MHz, Radio Transmitting, During Flash Write. Maximum Duration 4.33 ms. Active ARM Cortex-M3, RAM and Flash Operating, Radio and All Other Peripherals Off. Clock Frequency of CPU and Peripherals Set to 7.3728MHz, VCORE = 1.2V MIN TYP MAX UNITS Flash Write Single Bank Flash Write 3.7 mA Flash Erase Single Bank Page or Mass Erase 2.5 mA 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 5 LTP5901-IPR/LTP5902-IPR DC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. OPERATION/STATE CONDITIONS MIN Radio Tx 0dBm 8dBm Current with Autonomous MAC Managing Radio Operation, CPU Inactive. Clock Frequency of CPU and Peripherals Set to 7.3728MHz. Radio Rx Current with Autonomous MAC Managing Radio Operation, CPU Inactive. Clock Frequency of CPU and Peripherals Set to 7.3728MHz. TYP MAX UNITS 5.4 9.7 mA mA 4.5 mA Radio Specifications The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. PARAMETER CONDITIONS MIN TYP 2.4000 MAX 2.4835 UNITS GHz Frequency Band l Number of Channels l 15 Channel Separation l 5 MHz l 2405 + 5*(k-11) MHz 250 kbps Channel Center Frequency Where k = 11 to 25, as Defined by IEEE.802.4.15 Raw Data Rate l Antenna Pin ESD Protection HBM Per JEDEC JESD22-A114F (Note 2) 6000 V Range Indoor Outdoor Free Space 100 300 1200 m m m 25C, 50% RH, +2dBi Omni-Directional Antenna, Antenna 2m Above Ground Radio Receiver Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS Receiver Sensitivity Packet Error Rate (PER) = 1% (Note 5) -93 dBm Receiver Sensitivity PER = 50% -95 dBm Saturation Maximum Input Level the Receiver Will Properly Receive Packets 0 dBm Adjacent Channel Rejection (High Side) Desired Signal at -82dBm, Adjacent Modulated Channel 5MHz Above the Desired Signal, PER = 1% (Note 5) 22 dBc Adjacent Channel Rejection (Low Side) Desired Signal at -82dBm, Adjacent Modulated Channel 5MHz Below the Desired Signal, PER = 1% (Note 5) 19 dBc Alternate Channel Rejection (High Side) Desired Signal at -82dBm, Alternate Modulated Channel 10MHz Above the Desired Signal, PER = 1% (Note 5) 40 dBc Alternate Channel Rejection (Low Side) Desired Signal at -82dBm, Alternate Modulated Channel 10MHz Below the Desired Signal, PER = 1% (Note 5) 36 dBc Second Alternate Channel Rejection Desired Signal at -82dBm, Second Alternate Modulated Channel Either 15MHz Above or Below, PER = 1% (Note 5) 42 dBc Co-Channel Rejection Desired Signal at -82dBm, Undesired Signal is an 802.15.4 Modulated Signal at the Same Frequency, PER = 1% -6 dBc LO Feed Through -55 dBm Frequency Error Tolerance (Note 6) 50 ppm Symbol Error Tolerance 50 ppm Received Signal Strength Indicator (RSSI) Input Range -90 to -10 dBm RSSI Accuracy 6 RSSI Resolution 1 dB dB 59012iprf 6 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Radio Transmitter Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. PARAMETER CONDITIONS Output Power High Calibrated Setting Low Calibrated Setting Delivered to a 50 Load Spurious Emissions Conducted Measurement with a 50 Single-Ended Load, 8dBm Output Power. All Measurements Made with Max Hold. 30MHz to 1000MHz 1GHz to 12.75GHz 2.4GHz ISM Upper Band Edge (Peak) 2.4GHz ISM Upper Band Edge (Average) 2.4GHz ISM Lower Band Edge Harmonic Emissions 2nd Harmonic 3rd Harmonic MIN TYP RBW = 120kHz, VBW = 100Hz RBW = 1MHz, VBW = 3MHz RBW = 1MHz, VBW = 3MHz RBW = 1MHz, VBW = 10Hz RBW = 100kHz, VBW = 100kHz MAX UNITS 8 0 dBm dBm < -70 -45 -37 -49 -45 dBm dBm dBm dBm dBc -50 -45 dBm dBm Conducted Measurement Delivered to a 50 Load, Resolution Bandwidth = 1MHz, Video Bandwidth = 1MHz. Digital I/O Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP VIL Low Level Input Voltage VIH High Level Input Voltage (Note 8) l VSUPPLY VOL Low Level Output Voltage Type 1, IOL(MAX) = 1.2mA l l -0.3 - 0.3 VOH High Level Output Voltage Type 1, IOH(MAX) = -0.8mA l VSUPPLY VOL Low Level Output Voltage Type 2, Low Drive, IOL(MAX) = 2.2mA l VOH High Level Output Voltage Type 2, Low Drive, IOH(MAX) = -1.6mA l VSUPPLY VOL Low Level Output Voltage Type 2, High Drive, IOL(MAX) = 4.5mA l VOH High Level Output Voltage Type 2, High Drive, IOH(MAX) = -3.2mA l VSUPPLY Input Leakage Current Input Driven to VSUPPLY or GND - 0.3 - 0.3 - 0.3 Pull-Up/Pull-Down Resistance MAX UNITS 0.6 V VSUPPLY + 0.3 V 0.4 V VSUPPLY + 0.3 V 0.4 V VSUPPLY + 0.3 V 0.4 V VSUPPLY + 0.3 V 50 nA 50 k Temperature Sensor Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. PARAMETER CONDITIONS Offset Temperature Offset Error at 25C MIN Slope Error TYP MAX UNITS 0.25 C 0.033 C/C 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 7 LTP5901-IPR/LTP5902-IPR System Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP Doze to Active State Transmit Doze to Radio Tx or Rx QCCA Charge to Sample RF Channel RSSI Charge Consumed Starting from Doze State and Completing an RSSI Measurement QMAX Largest Atomic Charge Operation Flash Erase, 21ms Max Duration RESETn Pulse Width MAX 5 s 1.2 ms 4 C 200 l 125 l UNITS C s UART AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX Permitted Rx Baud Rate Error Both Application Programming Interface (API) and Command Line Interface (CLI) UARTs l -2 2 Generated Tx Baud Rate Error Both API and CLI UARTs UNITS % l -1 1 % tRX_RTS to RX_CTS Assertion of UART_RX_RTSn to Assertion of UART_RX_CTSn, or Negation of UART_RX_ RTSn to Negation of UART_RX_CTSn l 0 2 ms tCTS_R to RX Assertion of UART_RX_CTSn to Start of Byte l 0 20 ms tEOP to RX_RTS End of Packet (End of the Last Stop Bit) to Negation of UART_RX_RTSn l 0 22 ms l 0 22 ms tBEG_TX_RTS to TX_CTS Assertion of UART_TX_RTSn to Assertion of UART_TX_CTSn tEND_TX_CTS to TX_RTS Negation of UART_TX_CTSn to Negation of UART_TX_RTSn 2 Bit Period tTX_CTS to TX Assertion of UART_TX_CTSn to Start of Byte l 0 2 Bit Period tEOP to TX_RTS End of Packet (End of the Last Stop Bit) to Negation of UART_TX_RTSn l 0 1 Bit Period tRX_INTERBYTE Receive Inter-Byte Delay l tTX to TX_CTS Start of Byte to Negation of UART_TX_CTSn l 100 0 ms s 59012iprf 8 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Uart AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) tEOP TO RX_RTS UART_RX_RTSn tRX_RTS TO RX_CTS UART_RX_CTSn tRX_CTS TO RX UART_RX tRX_RTS TO RX_CTS tRX_INTERBYTE BYTE 0 BYTE 1 tEOP TO TX_RTS UART_TX_RTSn t END_TX_CTS TO TX_RTS tBEG_TX_RTS TO TX_CTS UART_TX_CTSn t END_TX_RTS TO TX_CTS tTX TO TX_CTS tTX_CTS TO TX UART_TX BYTE 0 BYTE 1 59012IPR F01 Figure 1. API UART Timing Time AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) SYMBOL PARAMETER CONDITIONS (Note 7) tSTROBE TIMEn Signal Strobe Width l 125 tRESPONSE Delay from Rising Edge of TIMEn to the Start of Time Packet on API UART l 0 tTIME_HOLD Delay from End of Time Packet on API UART to Falling Edge of Subsequent TIMEn l 0 Timestamp Resolution (Note 9) l 1 s Network-Wide Time Accuracy (Note 10) l 5 s tSTROBE MIN TYP MAX UNITS s 100 ms ns tTIME_HOLD TIMEn tRESPONSE UART_TX TIME INDICATION PAYLOAD 59012IPR F02 Figure 2. Timestamp Timing 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 9 LTP5901-IPR/LTP5902-IPR Radio_INHIBIT AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) SYMBOL PARAMETER tRADIO_OFF Delay from Rising Edge of RADIO_ INHIBIT to Radio Disabled CONDITIONS (Note 7) tRADIO_INHIBIT_STROBE Maximum RADIO_INHIBIT Strobe Width MIN TYP MAX UNITS l 20 ms l 2 s tRADIO_INHIBIT_STROBE RADIO_INHIBIT tRADIO_OFF RADIO STATE ACTIVE/OFF OFF ACTIVE/OFF 59012IPR F03 Figure 3. RADIO_INHIBIT Timing Flash AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) SYMBOL PARAMETER CONDITIONS (Note 7) tWRITE Time to Write a 32-Bit Word (Note 11) l 21 ms tPAGE_ERASE Time to Erase a 2k Byte Page (Note 11) l 21 ms tMASS_ERASE Time to Erase 256k Byte Flash Bank (Note 11) l 21 ms Data Retention MIN 25C 85C 105C TYP MAX 100 20 8 UNITS Years Years Years Flash SPI Slave AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) SYMBOL PARAMETER CONDITIONS (Note 7) MIN TYP MAX tFP_EN_to_RESET Setup from Assertion of FLASH_P_ENn to Assertion of RESETn l 0 ns tFP_ENTER Delay from the Assertion RESETn to the First Falling Edge of IPCS_SSn l 125 s tFP_EXIT Delay from the Completion of the Last Flash SPI Slave Transaction to the Negation of RESETn and FLASH_P_ENn l 10 s tSSS IPCS_SSn Setup to the Leading Edge of IPCS_SCK l 15 ns tSSH IPCS_SSn Hold from Trailing Edge of IPCS_SCK l 15 ns tCK IPCS_SCK Period l 50 ns tDIS IPCS_MOSI Data Setup l 15 ns tDIH IPCS_MOSI Data Hold l 5 ns tDOV IPCS_MISO Data Valid l 3 ns tOFF IPCS_MISO Data Three-State l 0 30 UNITS ns 59012iprf 10 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Flash SPI Slave AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) FLASH_P_ENn tFP_EN_TO_RESET tFP_EXIT tFP_ENTER RESETn tSSS tSSH IPCS_SSn tCK IPCS_SCK tDIS tDIH IPCS_MOSI 59012IPR F04 Figure 4. Flash Programming Interface Timing External Bus AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) SYMBOL PARAMETER CONDITIONS tLEPW EB_IO_LE0, EB_IO_LE1, EB_IO_LE2 Pulse Width tAH EB_DATA_[7:0] Address Hold from the Rising Edge of EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 tAV_to_DL MIN TYP MAX UNITS l 100 ns l 90 ns EB_ADDR_[1:0] Address Valid Until EB_DATA_[7:0] Data Latched l 90 ns tCSn_to_OEn EB_CS0n Asserted Until EB_OEn Asserted l 150 ns tCSn_OFF EB_CS0n Negated Between External Bus Transfers l 100 ns tSU_to_CSn EB_ADDR_[1:0], EB_IO_WEn Setup to EB_CSn Asserted l 50 ns tH_from_CSn EB_ADDR_[1:0], EB_IO_WEn Hold from EB_CSn Negated l 50 ns EB_DATA_[7:0] During Address Phase 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 11 LTP5901-IPR/LTP5902-IPR External Bus AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) tLEPW EB_IO_LE0 tLEPW EB_IO_LE1 tLEPW EB_IO_LE2 tAH EB_DATA_[7:0] X tAH tAH A[25:18] A[17:10] A[9:2] D[31:24] D[23:16] D[7:0] D[15:8] X tAV_to_DL XX EB_ADDR_[1:0] 11 10 01 00 tCSn_OFF EB_IO_CS0n tCSn_to_OEn EB_IO_OEn 59012IPR F05 Figure 5. External Bus Read Timing tLEPW EB_IO_LE0 tLEPW EB_IO_LE1 tLEPW EB_IO_LE2 tAH tAH EB_DATA_[7:0] EB_ADDR_[1:0] X A[25:18] A[17:10] tAH A[9:2] XX D[31:24] D[23:16] D[7:0] D[15:8] X 11 10 00 01 00 tSU_to_CSn tH_from_CSn EB_IO_WEn tCSn tCSn_OFF EB_IO_CS0n 59012IPR F06 Figure 6. External Bus Write Timing 59012iprf 12 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR External Bus AC Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and VSUPPLY = 3.6V unless otherwise noted. (Note 12) Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: ESD (electrostatic discharge) sensitive device. ESD protection devices are used extensively internal to Eterna. However, high electrostatic discharge can damage or degrade the device. Use proper ESD handling precautions. Note 3: Extended storage at high temperature is discouraged, as this negatively affects the data retention of Eterna's calibration data. See FLASH Data Retention section for details. Note 4: Actual RF range is subject to a number of installation-specific variables including, but not restricted to ambient temperature, relative humidity, presence of active interference sources, line-of-sight obstacles, and near-presence of objects (for example, trees, walls, signage, and so on) that may induce multipath fading. As a result, range varies. Note 5: As specified by IEEE Std. 802.15.4-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for LowRate Wireless Personal Area Networks (LR-WPANs) http://standards.ieee. org/findstds/standard/802.15.4-2011.html. Note 6: IEEE Std. 802.15.4-2006 requires transmitters to maintain a frequency tolerance of better than 40ppm. Note 7: Per pin I/O types are provided in the Pin Functions section. Note 8: VIH maximum voltage input must respect the VSUPPLY maximum voltage specification. Note 9: See the SmartMesh IP Manager API Guide for the time indication notification definition. Note 10: Network time accuracy is a statistical measure and varies over the temperature range, reporting rate and the location of the device relative to the manager in the network. See Typical Performance Characteristics section for a more detailed description. Note 11: Code execution from flash banks being written or erased is suspended until completion of the flash operation. Note 12: Guaranteed by design. Not production tested. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 13 LTP5901-IPR/LTP5902-IPR Typical Performance Characteristics As described in the Application Time Synchronization section, Eterna provides two mechanisms for applications to maintain a time base across a network. The synchronization performance plots that follow were generated using the more precise TIMEn input. Publishing rate is the rate a mote application sends upstream data. Synchronization improves as the publishing rate increases. Baseline synchronization performance is provided for a network operating with a publishing rate of zero. Actual performance for applications in network will improve as publishing rates increase. All synchronization testing was performed with the 1-hop mote inside a temperature chamber. Timing errors due to temperature changes and temperature differences both between the manager and this mote and between this mote and its descendents therefore propagated down through the network. The synchronization of the 3-hop and 5-hop motes to the manager was thus affected by the temperature ramps even though they were at room temperature. For 2C/minute testing the temperature chamber was cycled between -40C and 85C at this rate for 24 hours. For 8C/minute testing, the temperature chamber was rapidly cycled between 85C and 45C for eight hours, followed by rapid cycling between -5C and 45C for eight hours, and lastly, rapid cycling between -40C and 15C for eight hours. 2.0 1.8 SUPPLY CURRENT (mA) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 5 30 10 15 20 25 PACKET RATE (PACKETS/s) 59012IPR F07a Figure 7a. Supply Current vs Packet Rate 2.5 5 HOPS 4 HOPS 3 HOPS 2 HOPS 1 Hop 2.0 MEDIAN LATENCY (s) In mesh networks data can propagate from the manager to the nodes, downstream, or from the motes to the manager, upstream, via a sequence of transmissions from one device to the next. As shown in Figure 8, data originating from mote P1 may propagate to the manager directly or through P2. As mote P1 may directly communicate with the manager, mote P1 is referred to as a 1-hop mote. Data originating from mote D1, must propagate through at least one other mote, P2 or P1, and as a result is referred to as a 2-hop mote. The fewest number of hops from a mote to the manager determines the hop depth. 1.5 1.0 0.5 0 0 5 30 10 15 20 25 REPORTING INTERVAL (s) 59012IPR F07b Figure 7b. Packet Latency vs Reporting Interval MANAGER P1 P2 1 HOP P3 2 HOP D1 D2 3 HOP 5800IPM F08 Figure 8. Example Network Graph 59012iprf 14 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Typical Performance Characteristics 30 20 10 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 25 = -0.2 = 1.7 N = 89699 20 15 10 5 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) NORMALIZED FREQUENCY OF OCCURANCE (%) NORMALIZED FREQUENCY OF OCCURANCE (%) 15 10 5 40 14 12 = 0.9 = 3.9 N = 93846 8 6 4 2 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 59012IPR G04 8 6 4 2 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 8 6 4 2 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 59012IPR G07 14 12 40 59012IPR G03 40 7 6 = 1.0 = 7.7 N = 93845 5 4 3 2 1 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 59012IPR G05 NORMALIZED FREQUENCY OF OCCURANCE (%) NORMALIZED FREQUENCY OF OCCURANCE (%) 10 10 40 59012IPR G06 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 3 Hops, 8C/Min. = 3.6 = 5.0 N = 88144 = -0.2 = 3.6 N = 89698 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 5 Hops, 2C/Min. 10 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 1 Hop, 8C/Min. 12 12 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 3 Hops, 2C/Min. = 1.5 = 3.3 N = 93812 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 14 59012IPR G02 59012IPR G01 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 1 Hop, 2C/Min. 20 NORMALIZED FREQUENCY OF OCCURANCE (%) 40 30 NORMALIZED FREQUENCY OF OCCURANCE (%) 50 = 0.0 = 0.9 N = 89700 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 5 Hops, Room Temperature TIMEn Synchronization Error 0 Packet/s Publishing Rate, 5 Hops, 8C/Min. NORMALIZED FREQUENCY OF OCCURANCE (%) 60 TIMEn Synchronization Error 0 Packet/s Publishing Rate, 3 Hops, Room Temperature NORMALIZED FREQUENCY OF OCCURANCE (%) NORMALIZED FREQUENCY OF OCCURANCE (%) TIMEn Synchronization Error 0 Packet/s Publishing Rate, 1 Hop, Room Temperature = 1.1 = 3.8 N = 88179 10 8 6 4 2 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 7 6 = 1.0 = 7.4 N = 88178 5 4 3 2 1 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 59012IPR G08 40 59012IPR G09 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 15 LTP5901-IPR/LTP5902-IPR Typical Performance Characteristics 40 30 20 10 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 50 = -0.2 = 1.2 N = 17008 40 30 20 10 00 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) = 0.5 = 1.9 N = 85860 30 25 20 15 10 5 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 45 40 35 = 0.1 = 1.5 N = 85858 25 20 15 10 5 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 59012IPR G13 = 0.2 = 1.4 N = 33932 40 30 20 10 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 30 20 10 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 35 30 40 59012IPR G16 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 5 Hops, 2C/Min. = 0.1 = 1.5 N = 85855 20 15 10 5 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 59012IPR G13 60 50 40 59012IPR G15 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 5 Hops, 8C/Min. = 0.0 = 1.3 N = 33930 40 30 20 10 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 40 25 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 3 Hops, 8C/Min. NORMALIZED FREQUENCY OF OCCURANCE (%) NORMALIZED FREQUENCY OF OCCURANCE (%) 50 40 = -0.2 = 1.2 N = 17007 59012IPR G12 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 3 Hops, 2C/Min. 30 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 1 Hop, 8C/Min. 60 40 50 59012IPR G11 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 1 Hop, 2C/Min. NORMALIZED FREQUENCY OF OCCURANCE (%) NORMALIZED FREQUENCY OF OCCURANCE (%) 59012IPR G10 35 NORMALIZED FREQUENCY OF OCCURANCE (%) 50 60 NORMALIZED FREQUENCY OF OCCURANCE (%) = 0.0 = 1.2 N = 22753 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 5 Hops, Room Temperature NORMALIZED FREQUENCY OF OCCURANCE (%) 60 TIMEn Synchronization Error 1 Packet/s Publishing Rate, 3 Hops, Room Temperature NORMALIZED FREQUENCY OF OCCURANCE (%) NORMALIZED FREQUENCY OF OCCURANCE (%) TIMEn Synchronization Error 1 Packet/s Publishing Rate, 1 Hop, Room Temperature 40 50 40 = -1.0 = 1.3 N = 33929 30 20 10 0 10 20 30 -40 -30 -20 -10 0 SYNCHRONIZATION ERROR (s) 59012IPR G17 40 59012IPR G18 59012iprf 16 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Typical Performance Characteristics As described in the SmartMesh Network Overview section, devices in network spend the vast majority of their time inactive in their lowest power state (Doze). On a synchronous schedule a mote will wake to communicate with another mote. Regularly occurring sequences which wake, perform a significant function and return to sleep are considered atomic. These operations are considered atomic as the sequence of events can not be separated into smaller events while performing a useful function. For example, transmission of a packet over the radio is an atomic operation. Atomic operations may be characterized in either charge or energy. In a time slot where a mote successfully sends a packet, an atomic transmit includes setup prior to sending the message, sending the message, receiving the acknowledgment and the post processing needed as a result of the message being sent. Similarly in a time slot when a mote successfully receives a packet, an atomic receive includes setup prior to listening, listen- ing until the start of the packet transition, receiving the packet, sending the acknowledge and the post processing required due to the arrival of the packet. To ensure reliability each mote in the network is provided multiple time slots for each packet it nominally will send and forward. The time slots are assigned to communicate upstream with at least two different motes. When combined with frequency hopping this provides temporal, spatial and spectral redundancy. Given this approach a mote will often listen for a message that it will never receive, since the time slot is not being used by the transmitting mote. It has already successfully transmitted the packet. Since typically three timeslots are scheduled for every one packet to be sent or forwarded, motes will perform more of these atomic idle listens than atomic transmit or atomic receive sequences. Examples of transmit, receive and idle listen atomic operations are shown below. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 17 LTP5901-IPR/LTP5902-IPR Typical Performance Characteristics Figure 9. 18 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 59012iprf LTP5901-IPR/LTP5902-IPR Pin Functions Pin functions shown in italics are currently not supported in software. The following table organizes the pins by functional groups. For those I/O with multiple functions the alternate functions are shown on the second and third line in their respective row. The No column provides the pin number. The second column lists the function. The Type column NO POWER SUPPLY lists the I/O type. The I/O column lists the direction of the signal relative to Eterna. The Pull column shows which signals have a fixed passive pull-up or pull-down. The Description column provides a brief signal description. TYPE I/O GND Power - - Ground Connection 11 GND Power - - Ground Connection 20 GND Power - - Ground Connection 30 GND Power - - Ground Connection 34 GND Power - - Ground Connection 37 GND Power - - Ground Connection 42 GND Power - - Ground Connection 56 GND Power - - Ground Connection 66 GND Power - - Ground Connection 55 VSUPPLY Power - - Power Supply Input to Eterna 1 NO RADIO 64 RADIO_INHIBIT GPIO15 PULL DESCRIPTION TYPE I/O 1 (Note 13) I I/O PULL DESCRIPTION - Radio Inhibit General Purpose Digital I/O 4 GPIO17 1 I/O - General Purpose Digital I/O 5 GPIO18 1 I/O - General Purpose Digital I/O 6 GPIO19 - ANTENNA NO ANALOG 1 I/O - General Purpose Digital I/O N/A N/A - Chip Antenna (LTP5901) or MMCX Connector (LPT5902) TYPE I/O 7 AI_2 Analog I PULL DESCRIPTION - Analog Input 2 8 AI_1 Analog I - Analog Input 1 9 AI_3 Analog I - Analog Input 3 10 AI_0 Analog I - Analog Input 0 NO RESET TYPE I/O 15 RESETn 1 I NO JTAG TYPE I/O 16 TDI 1 I UP JTAG Test Data In 17 TDO 1 O - JTAG Test Data Out 18 TMS 1 I UP 19 TCK 1 I PULL DESCRIPTION UP Reset Input, Active Low PULL DESCRIPTION JTAG Test Mode Select DOWN JTAG Test Clock 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 19 LTP5901-IPR/LTP5902-IPR Pin Functions Pin functions shown in italics are currently not supported in software. NO SPECIAL PURPOSE TYPE I/O 1 (Note 13) I TYPE I/O 25 EB_DATA_7 1 I/O - External Bus Data Bit 7 26 EB_DATA_6 1 I/O - External Bus Data Bit 6 27 EB_DATA_4 1 I/O - External Bus Data Bit 4 28 EB_DATA_0 1 I/O - External Bus Data Bit 0 31 UARTC0_TX EB_IO_LE0 2 O O - CLI UART 0 Transmit External Bus I/O Latch Enable 0 for External Address Bits A[9:2] 32 UARTC0_RX EB_DATA_1 1 I I/O - CLI UART 0 Receive External Bus Data Bit 1 38 EB_IO_LE2 1 O - External Bus I/O Latch Enable 2 for External Address Bits A[25:18] 40 EB_ADDR_1 2 O - External Bus Address Bit 1 41 EB_ADDR_0 2 O - External Bus Address Bit 0 43 EB_DATA_3 1 I/O - External Bus Data Bit 3 44 EB_DATA_2 1 I/O - External Bus Data Bit 2 45 EB_DATA_5 1 I/O - External Bus Data Bit 5 46 EB_IO_CS0n 2 O - External Bus Chip Select 0 47 UARTC1_TX 2 O - CLI UART 1 Transmit 48 UARTC1_RX 1 I - CLI UART 1 Receive 49 EB_IO_WEn 2 O - External Bus Write Enable Strobe 50 EB_IO_OEn 2 O - External Bus Output Enable Strobe NO IPCS SPI/FLASH PROGRAMMING (NOTE 14) 63 TIMEn NO CLI AND EXTERNAL MEMORY PULL DESCRIPTION - Time Capture Request, Active Low PULL DESCRIPTION TYPE I/O 33 IPCS_MISO 2 O - SPI Flash Emulation (MISO) Master in Slave Out Port 35 IPCS_MOSI 1 I - SPI Flash Emulation (MOSI) Master Out Slave in Port 36 IPCS_SCK 1 I - SPI Flash Emulation (SCK) Serial Clock Port 39 IPCS_SSn 1 I - SPI Flash Emulation Slave Select, Active Low 51 FLASH_P_ENn EB_IO_LE1 1 I O UP UP TYPE I/O 1 (Note 13) I - UART Receive (RTS) Request to Send, Active Low NO API UART 57 UART_RX_RTSn 58 UART_RX_CTSn PULL DESCRIPTION Flash Program Enable, Active Low External Bus I/O Latch Enable 1 PULL DESCRIPTION 1 O - UART Receive (CTS) Clear to Send, Active Low 1 (Note 13) I - UART Receive 60 UART_TX_RTSn 1 O - UART Transmit (RTS) Request to Send, Active Low 61 UART_TX_CTSn 1 (Note 13) I - UART Transmit (CTS) Clear to Send, Active Low 2 O - UART Transmit 59 UART_RX 62 UART_TX Note 13: These inputs are always enabled and must be driven or pulled to a valid state to avoid leakage. Note 14: Embedded programming over the IPCS SPI bus is only available when RESETn is asserted. 59012iprf 20 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Pin Functions VSUPPLY: System and I/O Power Supply. Provides power to the module. The digital-interface I/O voltages are also set by this voltage. resolution on the rising edge of the TIMEn signal and produces a packet on the API serial port containing the timing information. ANTENNA: Multiplexed Receiver Input and Transmitter Output Pin. The impedance presented to the MMCX connector should be 50, single-ended with respect to ground. UARTC0_RX, UARTC0_TX, UARTC1_RX, UARTC1_TX: The CLI UART provides a mechanism for monitoring, configuration and control of Eterna during operation. On the LTP5901/2-IPR CLI UART 0 is used when Eterna is not configured to support external RAM and CLI UART 1 is used when Eterna is configured to support external RAM. For a complete description of the supported commands see the SmartMesh IP Manager CLI Guide. RESETn: The asynchronous reset signal is internally pulled up. Resetting Eterna will result in the ARM Cortex-M3 rebooting and loss of network connectivity. Use of this signal for resetting Eterna is not recommended, except during power-on and in-circuit programming. RADIO_INHIBIT: RADIO_INHIBIT provides a mechanism for an external device to temporarily disable radio operation. Failure to observe the timing requirements defined in the RADIO_INHIBIT AC Characteristics section, may result in unreliable netowrk operation. In designs where the RADIO_INHIBIT function is not needed the input must either be tied, pulled or actively driven low to avoid excess leakage. TMS, TCK, TDI, TDO: JTAG port supporting software debug and boundary scan. SLEEPn: The SLEEPn function is not currently supported in software. The SLEEPn input must either be tied, pulled or actively driven high to avoid excess leakage. UART_RX, UART_RX_RTSn, UART_RX_CTSn, UART_TX, UART_TX_RTSn, UART_TX_CTSn: The API UART interface includes bi-directional wake up and flow control. Unused input signals must be driven or pulled to their inactive state. TIMEn: Strobing the TIMEn input is the most accurate method to acquire the network time maintained by Eterna. Eterna latches the network timestamp with sub-microsecond EB_DATA_0 through EB_DATA_7, EB_ADDR_0, EB_ ADDR_1, EB_IO_LE1 through EB_IO_LE2, EB_IO_CS0n, EB_IO_WEn, EB_IO_ENn: The external bus provides a multiplexed address data bus enabling the Cortex-M3 direct access of external byte wide RAM. The additional RAM is used by network management software enabling the support of a larger network of motes with higher packet throughput. To support the addressing needed, each latch signal, EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 will strobe to latch 8-bits of address from the EB_DATA[7:0] bus. EB_IO_LE0, EB_IO_LE1, and EB_IO_LE2 correspond to addres bits [9:2], [17:10] and [25:18] respectively. EB_ADDR_0 and EB_ADDR_1 correspond to the lower two bits of address. For systems with 256k bytes or less EB_IO_LE2 can be ignored. EB_IO_CS0n, EB_IO_WEn and EB_IO_OEn provide chip select, write enable and output enable control of the external RAM. FLASH_P_ENn, IPCS_SSn, IPCS_SCK, IPCS_MISO, IPCS_SSn: The In-circuit programming control system (IPCS) bus enables in-circuit programming of Eterna's flash memory. IPCS_SCK is a clock and should be terminated appropriately for the driving source to prevent overshoot and ringing. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 21 LTP5901-IPR/LTP5902-IPR Operation The LTP5901/LTP5902 is the world's most energy-efficient IEEE 802.15.4 compliant platform, enabling battery and energy harvested applications. With a powerful 32-bit ARM Cortex-M3, best-in-class radio, flash, RAM and purposebuilt peripherals, Eterna provides a flexible, scalable and robust networking solution for applications demanding minimal energy consumption and data reliability in even the most challenging RF environments. Shown in Figure 10, Eterna integrates purpose-built peripherals that excel in both low operating-energy consumption and the ability to rapidly and precisely cycle between operating and low power states. Items in the gray shaded region labeled analog core correspond to the analog/RF components. 32kHz DIGITAL CORE ANALOG CORE 32kHz, 20MHz TIMERS SCHED VOLTAGE REFERENCE PRIMARY DC/DC CONVERTER SRAM 72kB CORE REGULATOR CLOCK REGULATOR PMU/ CLOCK CONTROL FLASH 512kB RELAXATION OSCILLATOR ANALOG REGULATOR PA DC/DC CONVERTER PoR FLASH CONTROLLER 802.15.4 MOD AES CODE LPF DAC PA 802.15.4 FRAMING DMA AUTO MAC SYSTEM 802.15.4 DEMOD 20MHz PLL ADC LIMITER BPF PPF LNA AGC RSSI IPCS SPI SLAVE CLI UART (2 PIN) API UART (6 PIN) ADC CTRL 10-BIT ADC BAT LOAD VGA PTAT 4-BIT DAC 59012IPR F10 Figure 10. Eterna Block Diagram 59012iprf 22 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Operation Power Supply Eterna is powered from a single pin, VSUPPLY, which powers the I/O cells and is also used to generate internal supplies. Eterna's two on-chip DC/DC converters minimize Eterna's energy consumption while the device is awake. To conserve power the DC/DC converters are disabled when the device is in low power state. Eterna's integrated power supply conditioning architecture, including the two integrated DC/DC converters and three integrated low dropout regulators, provides excellent rejection of supply noise. Eterna's operating supply voltage range is high enough to support direct connection to lithium-thionyl chloride, Li-SOCl2, sources and wide enough to support battery operation over a broad temperature range. with other wireless products. In addition, precise timing enables networks to reduce spectral dead time, increasing total network throughput. Application Time Synchronization In addition to coordinating timeslots across the network, which is transparent to the user, Eterna's timing management is used to support two mechanisms to share network time. Having an accurate, shared, network-wide time base enables events to be accurately time stamped or tasks to be performed in a synchronized fashion across a network. Eterna will send a time packet through its serial interface when one of the following occurs: * Eterna receives an API request to read time Supply Monitoring and Reset * The TIMEn signal is asserted Eterna integrates a power-on reset (PoR) circuit. As the RESETn input pin is nominally configured with an internal pull-up resistor, no connection is required. For a graceful shutdown, the software and the networking layers should be cleanly halted via API commands prior to assertion of the RESETn pin. See the SmartMesh IP Manager API Guide for details on the disconnect and reset commands. Eterna includes a soft brown-out monitor that fully protects the flash from corruption in the event that power is removed while writing to flash. Integrated flash supervisory functionality, in conjunction with a fault tolerant file system, yields a robust non-volatile storage solution. The use of TIMEn has the advantage of being more accurate. The value of the timestamp is captured in hardware relative to the rising edge of TIMEn. If an API request is used, due to packet processing, the value of the timestamp may be captured several milliseconds after receipt of the packet due to packet processing. See section TIMEn AC Characteristics, for the time function's definition and specifications. Precision Timing A major feature of Eterna over competing 802.15.4 product offerings is its low power dedicated timing hardware and timing algorithms. This functionality provides timing precision two to three orders of magnitude better than any other low power solution available at the time of publication. Improved timing accuracy allows motes to minimize the amount of radio listening time required to ensure packet reception thereby lowering even further the power consumed by SmartMesh networks. Eterna's patented timing hardware and timing algorithms provide superior performance over rapid temperature changes, further differentiating Eterna's reliability when compared Time References Eterna includes three clock sources: an internal relaxation oscillator, a low power oscillator designed for a 32.768kHz crystal, and the radio reference oscillator designed for a 20MHz crystal. Relaxation Oscillator The relaxation oscillator is the primary clock source for Eterna, providing the clock for the CPU, memory subsystems, and all peripherals. The internal relaxation oscillator is dynamically calibrated to 7.3728MHz. The internal relaxation oscillator typically starts up in a few s, providing an expedient, low energy method for duty cycling between active and low power states. Quick start-up from the doze state, defined in the State Diagram section, allows Eterna to wake up and receive data over the UART and SPI interfaces by simply detecting activity on the appropriate signals. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 23 LTP5901-IPR/LTP5902-IPR Operation 32.768kHz Crystal API UART Protocol Once Eterna is powered up and the 32.768kHz crystal source has begun oscillating, the 32.768kHz crystal remains operational while in the active state, and is used as the timing basis when in doze state. See the State Diagram section, for a description of Eterna's operational states. The API UART protocol was created with the goal of supporting a wide range of companion multipoint control units (MCUs) while reducing power consumption of the system. The receive half of the API UART protocol includes two additional signals in addition to UART_RX: UART_RX_ RTSn and UART_RX_CTSn. The transmit half of the API UART protocol includes two additional signals in addition to UART_TX: UART_TX_RTSn and UART_TX_CTSn. The API UART protocol is referred to as Mode 4. 20MHz Crystal The 20MHz crystal source provides a frequency reference for the radio, and is automatically enabled and disabled by Eterna as needed. Radio Eterna includes the lowest power commercially available 2.4GHz IEEE 802.15.4e radio by a substantial margin. (Please refer to section Radio Specifications, for power consumption numbers). Eterna's integrated power amplifier is calibrated and temperature-compensated to consistently provide power at a limit suitable for worldwide radio certifications. Additionally, Eterna uniquely includes a hardware-based autonomous MAC that handles precise sequencing of peripherals, including the transmitter, the receiver, and advanced encryption standard (AES) peripherals. The hardware-based autonomous media access controller (MAC) minimizes CPU activity, thereby further decreasing power consumption. UARTs The principal network interface is through the application programming interface (API) UART. A command-line interface (CLI) is also provided for support of test and debug functions. Both UARTs sense activity continuously, consuming virtually no power until data is transferred over the port and then automatically returning to their lowest power state after the conclusion of a transfer. The definition for packet encoding on the API UART interface can be found in the SmartMesh IP Manager API Guide and the CLI command definitions can be found in the SmartMesh IP Manager CLI Guide. In the figures accompanying the protocol descriptions, signals driven by the companion processor are drawn in black and signals driven by Eterna are drawn in blue. UART Mode 4 UART Mode 4 incorporates level-sensitive flow control on the TX channel and requires no flow control on the RX channel, supporting 115200 baud. The use of levelsensitive flow control signals enables higher data rates with the option of using a reduced set of the flow control signals; however, with the companion processor must negate UART_TX_CTSn prior to the end of the packet and waiting at least tRX_RTS to RX_CTS between packets, see the UART AC Characteristics section for complete timing specifications. Packets are HDLC encoded with one stop bit and no parity bit. The use of the RX flow control signals (UART_RX_RTSn and UART_RX_CTSn) for Mode 4 are optional. The flow control signals for the TX channel are shown in Figure 11 UART Mode 4 Transmit Flow Control. Transfers are initiated by Eterna asserting UART_TX_RTSn. The UART_TX_CTSn signal may be actively driven by the companion processor when ready to receive a packet or UART_TX_CTSn may be tied low if the companion processor is always ready to receive a packet. After detecting a logic `0' on UART_TX_CTSn Eterna sends the entire packet. Following the transmission of the final byte in the packet Eterna negates UART_TX_RTSn and waits for a minimum period defined in the UART AC Characteristics section before asserting UART_TX_RTSn again. 59012iprf 24 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Operation For details on the timing of the UART protocol, see the UART AC Characteristics section. UART_TX_RTSn UART_TX_CTSn UART_TX BYTE 0 BYTE 1 59012IPR F11 Figure 11. UART Mode 4 Transmit Flow Control CLI UART The command line interface (CLI) UART port is a two wire protocol (TX and RX) that operates at a fixed 9600 baud rate with one stop bit and no parity. The CLI UART interface is intended to support command line instructions and response activity. Autonomous MAC Eterna was designed as a system solution to provide a reliable, ultralow power, and secure network. A reliable network capable of dynamically optimizing operation over changing environments requires solutions that are far too complex to completely support through hardware acceleration alone. As described in the Precision Timing section, proper time management is essential for optimizing a solution that is both low power and reliable. To address these requirements Eterna includes the autonomous MAC, which incorporates a co-processor for controlling all of the time-critical radio operations. The autonomous MAC provides two benefits: first, preventing variable software latency from affecting network timing and second, greatly reducing system power consumption by allowing the CPU to remain inactive during the majority of the radio activity. The autonomous MAC, provides software-independent timing control of the radio and radio-related functions, resulting in superior reliability and exceptionally low power. Security Network security is an often overlooked component of a complete network solution. Proper implementation of se- curity protocols is significant in terms of both engineering effort and market value in an OEM product. Eterna system solutions provide a FIPS-197 validated encryption scheme that includes authentication and encryption at the MAC and network layers with separate keys for each mote. This not only yields end-to-end security, but if a mote is somehow compromised, communication from other motes is still secure. A mechanism for secure key exchange allows keys to be kept fresh. To prevent physical attacks, Eterna includes hardware support for electronically locking devices, thereby preventing access to Eterna's flash and RAM memory and thus the keys and code stored therein. Temperature Sensor Eterna includes a calibrated temperature sensor on chip. The temperature readings are available locally through Eterna's serial API, in addition to being available via the network manager. The performance characteristics of the temperature sensor can be found in the Temperature Sensor Characteristics section. Radio Inhibit The RADIO_INHIBIT input enables an external controller to temporarily disable the radio software drivers (for example, to take a sensor reading that is susceptible to radio interference). When RADIO_INHIBIT is asserted the software radio drivers will disallow radio operations including clear channel assessment, packet transmits, or packet receipts. If the radio is active in the current timeslot when RADIO_INHIBIT is asserted the radio will be diabled after the present operation completes. For details on the timing associated with RADIO_INHIBIT, see the RADIO_INHIBIT AC Characteristics section. Factory Installed Software This product is provided with software programmed into the device. Devices can be configured via either the CLI or API ports. Configuration commands and settings are defined in SmartMesh IP Manager API Guide and SmartMesh IP Manager CLI Guide. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 25 LTP5901-IPR/LTP5902-IPR Operation Flash Data Retention Eterna contains internal flash (non-volatile memory) to store calibration results, unique ID, configuration settings and software images. Flash retention is specified over the operating temperature range. See Electrical Characteristics and Absolute Maximum Ratings sections. The degradation in flash retention for temperatures >85C can be approximated by calculating the dimensionless acceleration factor using the following equation. AF = e Ea 1 1 * - k T T +273 +273 STRESS USE Non destructive storage above the operating temperature range of -40C to 85C is possible; although, this may result in a degradation of retention characteristics. POWER-ON RESET VSUPPLY > PoR RESETn LOW AND FLASH_P_ENn LOW LOAD FUSE SETTINGS RESETn LOW AND FLASH_P_ENn HIGH SET RESETn HIGH AND FLASH_P_ENn HIGH FOR 125s, THEN SET RESETn LOW SERIAL FLASH EMULATION RESETn HIGH AND FLASH_P_ENn HIGH RESET DEASSERT RESETn BOOT START-UP ASSERT RESETn DOZE ASSERT RESETn CPU AND PERIPHERALS INACTIVE HW OR PMU EVENT OPERATION ASSERT RESETn CPU ACTIVE ACTIVE CPU INACTIVE DEEP SLEEP LOW POWER SLEEP COMMAND INACTIVE 59012IPR F12 Figure 12. Eterna State Diagram 59012iprf 26 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Operation Where: AF = acceleration factor Ea = activation energy = 0.6eV k = 8.625 * 10-5eV/K TUSE = is the specified temperature retention in C TSTRESS = actual storage temperature in C Example: Calculate the effect on retention when storing at a temperature of 105C. TSTRESS = 105C TUSE = 85C AF = 2.8 So the overall retention of the flash would be degraded by a factor of 2.8, reducing data retention from 20 years at 85C to 7.1 years at 105C. Networking The LTP5901-IPR/LTP5902-IPR network manager provides the ingress/egress point for at the wired to wireless mesh network boundary, via the API UART interface. The complexity of the mesh network management is handled entirely within the embedded software, which provides dynamic network optimization, deterministic power management, intelligent routing, and configurable bandwidth allocation while achieving carrier class data reliability and low power operation. Dynamic Network Optimization Dynamic network optimization allows Eterna to address the changing RF requirements in harsh industrial environments resulting in a network that is continuously self-monitoring and self-adjusting. The manager performs dynamic network optimization based upon periodic reports on network health and link quality that it receives from the network motes. The manager uses this information to provide performance statistics to the application layer and proactively solve problems in the network. Dynamic network optimization not only maintains network health, but also allows Eterna to deliver deterministic power management. One of the key advantages of SmartMesh networking solutions is the network manager is aware of and tracking the success or failure of every packet transaction, so not only can the network be optimized, but the solution can be rigorously tested to produce a system solution with better than 99.999% reliability. Deterministic Power Management Deterministic power management balances traffic in the network by diverting traffic around heavily loaded motes (for example, motes with high reporting rates). In doing so, it reduces power consumption for these motes and balances power consumption across the network. Deterministic power management provides predictable maintenance schedules to prevent down time and lower the cost of network ownership. When combined with field devices using Eterna's industry-leading low power radio technology, deterministic power management enables over a decade of battery life for network motes. Intelligent Routing Intelligent routing provides each packet with an optimal path through the network. The shortest distance between two points is a straight line, but in RF the quickest path is not always the one with the fewest hops. Intelligent routing finds optimal paths by considering the link quality (one path may lose more packets than another) and the retry schedule, in addition to the number of hops. The result is reduced network power consumption, elimination of in-network collisions, and unmatched network scalability and reliability. Configurable Bandwidth Allocation Smartmesh networks provide configurations that enable users to make bandwidth and latency versus power tradeoffs both network-wide and on a per device basis. This flexibly enables solutions that tailored to the application requirements, such as request/response, fast file transfer, and alerting. Relevant configuration parameters are described in the SmartMesh IP Users Guide. The design trade-offs between network performance and current consumption are supported via the SmartMesh Power and Performance Estimator. 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 27 LTP5901-IPR/LTP5902-IPR Operation IP Manager Options Serial Flash Emulation The IP manager is offered in three different dash code options, the -IPRA, -IPRB and -IPRC. The -IPRA option supports managing networks of 32 motes or less with a packet throughput of 24 packets per second.The -IPRB option supports managing networks of 100 motes or less with a packet throughput of 36 packets per second. The -IPRC option supports managing networks of 32 motes or less with a packet throughput of 36 packets per second. The -IPRA option does not support the use of external SRAM. The -IPRB and -IPRC options require the use of external SRAM, as described in the LTP5901 and LTP5902 Integration Guide. -IPRC managers can be upgraded to support managing networks of up to 100 motes by purchasing a software license key as described in the SmartMesh IP Users Guide. When both RESETn and FLASH_P_ENn are asserted, Eterna disables normal operation and enters a mode to emulate the operation of a serial flash. In this mode, its flash can be programmed. Operation Once Eterna has completed start-up, Eterna transitions to the operational group of states (active/CPU active, active/ CPU inactive, and Doze). There, Eterna cycles between the various states, automatically selecting the lowest possible power state while fulfilling the demands of network operation. Active State In order to provide capabilities and flexibility in addition to ultra low power, Eterna operates in various states, as shown in Figure 10 Eterna State Diagram and described in this section. State transitions shown in red are not recommended. In the active state, Eterna's relaxation oscillator is running and peripherals are enabled as needed. The ARM CortexM3 cycles between CPU-active and CPU-inactive (referred to in the ARM Cortex-M3 literature as sleep now mode). Eterna's extensive use of DMA and intelligent peripherals that independently move Eterna between active state and doze state minimizes the time the CPU is active, significantly reducing Eterna's energy consumption. Start-Up Doze State State Diagram Start-up occurs as a result of either crossing the power-on reset threshold or asserting RESETn. After the completion of power-on reset or the falling edge of an internally synchronized RESETn, Eterna loads its fuse table which, as described in the previous section, includes setting I/O direction. In this state, Eterna checks the state of the FLASH_P_ENn and RESETn and enters the serial flash emulation mode if both signals are asserted. If the FLASH_P_ENn pin is not asserted but RESETn is asserted, Eterna automatically reduces its energy consumption to a minimum until RESETn is released. Once RESETn is de-asserted, Eterna goes through a boot sequence, and then enters the active state. The doze state consumes orders of magnitude less current than the active state and is entered when all of the peripherals and the CPU are inactive. In the Doze state Eterna's full state is retained, timing is maintained, and Eterna is configured to detect, wake, and rapidly respond to activity on I/Os (such as UART signals and the TIMEn pin). In the doze state the 32.768kHz oscillator and associated timers are active. 59012iprf 28 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Applications Information Regulatory and Standards Compliance The RoHS-compliant design features include: Radio Certification * RoHS-compliant solder for solder joints The LTP5901 and LTP5902 have been certified under a single modular certification, with the module name of ETERNA2. Following the regulatory requirements provided in the ETERNA2 Users Guide can enable customers to ship products in the supported geographies, by simply completing an unintentional radiator scan of the finished product(s). The ETERNA2 Users Guide also provides the technical information needed to enable customers to further certify either the modules or products based upon the modules in geographies that have not or do not support modular certification. Compliance to Restriction of Hazardous Substances (RoHS) Restriction of hazardous substances 2(RoHS 2) is a directive that places maximum concentration limits on the use of certain hazardous substances in electrical and electronic equipment. Linear Technology is committed to meeting the requirements of the European Community directive 2011/65/EU. This product has been specifically designed to utilize RoHS-compliant materials and to eliminate or reduce the use of restricted materials to comply with 2011/65/EU. * RoHS-compliant base metal alloys * RoHS-compliant precious metal plating * RoHS-compliant cable assemblies and connector choices * Halogen-free mold compound * RoHS-compliant and 245C re-flow compatible Note: Customers may elect to use certain types of leadfree solder alloys in accordance with the European Community directive 2011/65/EU. Depending on the type of solder paste chosen, a corresponding process change to optimize reflow temperatures may be required. Soldering Information The LTP5901 and LTP5902 are suitable for both eutectic PbSn and RoHS-6 reflow. The maximum reflow soldering temperature is 260C. A more detailed description of layout recommendations, assembly procedures and design considerations is included in the LTP5901 and LTP5902 Hardware Integration Guide. Related Documentation TITLE LOCATION DESCRIPTION SmartMesh IP Users Guide http://www.linear.com/docs/41880 Theory of operation for SmartMesh IP networks and motes SmartMesh IP Manager API Guide http://www.linear.com/docs/41883 Definitions of the applications interface commands available over the API UART SmartMesh IP Manager CLI Guide http://www.linear.com/docs/41882 Definitions of the command line interface commands available over the CLI UART LTP5901 and LTP5902 Hardware Integration Guide http://www.linear.com/docs/41877 Recommended practices for designing with the LTP5901 and LTP5902 ETERNA2 Users Guide http://www.linear.com/docs/42916 The ETERNA2 module user's guide covering certification requirements for certified geographies and support documentation enabling customer certification in additional geographies for the LTP5901 and LTP5902 SmartMesh IP Tools Guide http://www.linear.com/docs/42453 The user's guide for all IP related tools, and specifically the definition for the on-chip Application Protocol (OAP) 59012iprf For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR 29 LTP5901-IPR/LTP5902-IPR Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. .100 2.54 .039 1.00 .945 24.00 .039 1.00 1.57 40.00 .039 1.00 1.213 30.80 1.122 28.50 1.102 28.00 1.063 27.00 1.031 26.20 R.010 TYP 0.25 1.654 42.00 .039 TYP 1.00 .079 2.00 4X .039 1.00 .035 0.90 0 0.00 .039 1.00 .87 22.00 .728 18.50 .630 16.00 .591 15.00 .551 14.00 .444 11.28 .394 10.00 .344 8.74 .236 6.00 .197 5.00 .157 4.00 0 0.00 .039 1.00 .08 2.00 .08 2.00 59012IPR F12 Figure 12. LTP5901 Mechanical Drawing 59012iprf 30 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LTP5901-IPR/LTP5902-IPR Package Description Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. .100 2.54 .177 4.50 .039 1.00 .945 24.00 .039 1.00 .029 0.73 1.40 35.50 1.272 32.30 .039 1.00 1.213 30.80 1.122 28.50 1.102 28.00 1.063 27.00 1.031 26.20 R.010 TYP 0.25 1.476 37.50 .039 TYP 1.00 4X .035 0.90 .079 2.00 .039 1.00 0 0.00 .039 1.00 .866 22.00 .728 18.50 .630 16.00 .591 15.00 .551 14.00 .444 11.28 .394 10.00 .344 8.73 .236 6.00 .197 5.00 .157 4.00 .071 1.80 0 0.00 .039 1.00 .078 2.0 .079 2.01 59012IPR F13 Figure 13. LTP5902 Mechanical Drawing 59012iprf Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representainformation of www.linear.com/LTP5901-IPR www.linear.com/LTP5902-IPR tionFor thatmore the interconnection its circuits as described herein willornot infringe on existing patent rights. 31 LTP5901-IPR/LTP5902-IPR Typical Application Power over Ethernet Network Manager SMSC 8710A (10/100 PHY) ATMEL SAM4E LTP5902-IPR ANTENNA TXP TXM MII RXP MII PWM TIMEn UART UART RXM RJ45 1 2 3 6 TX+ 14 1 12 3 TX- 13 2 RX+ 10 5 11 4 9 6 RX- COILCRAFT ETHI - 230LD 4 5 7 0.1F 100V 8 SMAJ58A TVS LT4265 (PoE PD INTERFACE CONTROLLER) LT8300 (ISOLATED FLYBACK CONVERTER) 3.3V 59012IPR TA02 Related Parts PART NUMBER DESCRIPTION COMMENTS LTC5800-IPRA IP Wireless Mesh 32 Mote Manager Manages Networks of Up to 32 SmartMesh IP Nodes. LTC5800-IPRB IP Wireless Mesh 100 Mote Manager Manages Networks of Up to 100 SmartMesh IP Nodes. LTP5901-IPM IP Wireless Mesh Mote PCB Module with Chip Antenna Includes Modular Radio Certification in the United States, Canada, Europe, Japan, South Korea, Taiwan, India, Australia and New Zealand LTP5902-IPM IP Wireless Mesh Mote PCB Module with MMCX Antenna Connector Includes Modular Radio Certification in the United States, Canada, Europe, Japan, South Korea, Taiwan, India, Australia and New Zealand LTC2379-18 18-Bit,1.6Msps/1Msps/500ksps/ 250ksps Serial, Low Power ADC 2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, DGC LTC3388-1/ LTC3388-3 20V High Efficiency Nanopower Step-Down Regulator 860nA IQ in Sleep, 2.7V to 20V Input, VOUT: 1.2V to 5.0V, Enable and Standby Pins LTC3588-1 Piezoelectric Energy Generator with Integrated High Efficiency Buck Converter VIN: 2.7V to 20V; VOUT(MIN): Fixed to 1.8V, 2.5V, 3.3V, 3.6V; IQ = 0.95A; 3mm x 3mm DFN-10 and MSOP-10E Packages LTC3108-1 Ultralow Voltage Step-Up Converter and VIN: 0.02V to 1V; VOUT = 2.5V, 3V, 3.7V, 4.5V Fixed; IQ = 6A; 3mm x 4mm DFN-12 and Power Manager SSOP-16 Packages LTC3459 Micropower Synchronous Boost Converter VIN: 1.5V to 5.5V; VOUT(MAX) = 10V; IQ = 10A; 2mm x 2mm DFN, 2mm x 3mm DFN or SOT-23 Package LTC4265 IEEE 802.3at High Power PD Interface Controller with 2-Event Classification 2-Event Classification Recognition, 100mA Inrush Current, Single-Class Programming Resistor, Full Compliance to 802.3at LT8300 100V Micropower Isolated Flyback Converter with 150V/260mA Switch 6V VIN 100V, No Opto Flyback , 5-Lead TSOT-23 Package 59012iprf 32 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTP5901-IPR or www.linear.com/LTP5902-IPR LT 0614 * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2014