PIC16LC74B-PTL16 - Microchip Technology

 1999 Microchip Technology Inc. Preliminary DS30026A-page 1

PIC16LC74B-16/PTL16 Microcontroller Core

Features:

• High-performance RISC CPU

• Spe cially tested

-16MHz @ 3V

• Only 35 single word instructions to learn

• All single cycle instructions except for program

branches which are two cycle

• Operating speed: DC - 16 MHz clock input

DC - 250 ns instruction cycle

• 4K x 14 words of Program Memory,

192 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC

oscillator for reliable operation

• Pr ogrammable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM

technology

• Wide operating voltage range: 2.5V to 5.5V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Automotive

temperature ranges

• Low-power consumption:

- < 5 mA @ 5V, 4 MHz

- 23 µA typical @ 3V, 32 kHz

-< 3 µA typical standby current

Pin Di agram:

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler

can be incremented during sleep via exter nal

crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period

• Capture, Compare, PWM module(s)

- Capture is 16 bit, max. resolution is 15.6 ns

- Compare is 16 bit, max. resolution is 250 ns

- PWM max. resolution is 10 bit

• 8-bit m ul tic ha nne l anal og-t o-digital converter

• Synchronous Seri al Port (SSP) with SPI

and I2C

• Universal Synchronous Asynchronous Receiver

Transmitter (USART/SCI)

• Parallel Slave Port (PSP), 8-bits wide, with

ex ternal RD, WR and CS contro l s

• Brown-out detection circuitry for Brown-out Reset

(BOR) Pin Diagrams

RC0/T1OSO/T1CKI

OSC2/CLKOUT

OSC1/CLKIN

VSS

VDD

RE2/CS/AN7

RE1/WR/AN6

RE0/RD/AN5

RA5/SS/AN4

RA4/T0CKI

RC7/RX/DT

RD4/PSP4

RD5/PSP5

RD6/PSP6

RD7/PSP7

VSS

VDD

RB0/INT

RB1

RB2

RB3

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR/VPP

RB7

RB6

RB5

RB4

NC 44

TQFP

PIC16LC74B-16/PTL16

8-Bit CMOS Microcontrollers with A/D Converter

PIC16LC74B-16/PTL16

DS30026A-page 2 Preliminary  1999 Microchip Technology Inc.

Table of Contents

1.0 General Description.................................................................................................................................................3

2.0 Electric al Characte ris tic s.............. ...... ..... ............................ ...... ............................ ...... .............................................5

3.0 DC and AC Characteristics Graphs and Tables.....................................................................................................27

4.0 Packaging Information ...........................................................................................................................................29

Index .............................................................................................................................................................................33

On-Line Support............................................................................................................................................................35

Reader Response .........................................................................................................................................................36

Product Identification System........................................................................................................................................37

To Our Valued Customers

Most Current Data Sheet

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umen t DS30000.

Errata

An err ata sheet ma y e xist for current de vi ces, describing minor op erationa l diff erenc es (from the data s heet) and rec-

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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Corrections to this Data Sheet

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We appreciate your assistance in making this a better document.

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 3

1.0 GENERAL DESCRIPTION

This data sheet covers the PIC16LC74B-16/PTL16

dev ice. The fu nctional ch aracteristics of this de vice are

identical to the PIC16LC74B. For electr ical specifica-

tions, see the electrical specifications contained within

this document. For all other information about this

device, see the PIC16C63A/65B/73B/74B data sheet

(DS30605).

PIC16LC74B-16/PTL16

DS30026A-page 4 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 5

2.0 ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (†)

Ambient temperature under bias.............................................................................................................-55°C to +125 °C

Storage temperature.............................................................................................................................. -65°C to +150°C

Voltag e on any pin with respect to VSS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5 V

Voltage on MCLR with respect to VSS (Note 2).......................................................................................... 0V to +13.25V

Voltage on RA4 with respect to Vss............................................................................................................... 0V to +8 .5V

Total power dissipation (Note 1)................................................................................................................................1.0W

Maximum current out of VSS pin ...........................................................................................................................300 mA

Maximum current into VDD pin..............................................................................................................................250 mA

Input clamp current, IIK (VI < 0 or VI > VDD)......................................................................................................................±20 mA

Output clamp current, IOK (VO < 0 or VO > VDD)..............................................................................................................±20 mA

Maximu m out put current sunk by an y I/O pin....................................... ............................ ...... .................................25 mA

Maximu m out put current sourced by an y I/O pin ................ ............................ ............................ ............................25 mA

Maximum current sunk by PORTA, PORTB, and PORTE (combined)..................................................................200 mA

Maximum current sourced by PORTA, PORTB, and PORTE (combined) ............................................................200 mA

Maximum current sunk by PORTC and PORTD (combined)................................................................................200 mA

Maximum current sourced by PORTC and PORTD (combined)...........................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

Note 2: Voltage sp i kes below VSS at the MCLR/VPP pin, in duc in g c urren ts greater than 8 0 m A , may cause latch-up .

Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather

than pulling this pin directly to VSS.

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

de vice . This is a st ress ratin g only and fun ctional op eration of the de vice , at those or any othe r condition s abov e those

indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

PIC16LC74B-16/PTL16

DS30026A-page 6 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-1: PIC16LC74B-16/PTL16 VOLTAGE-FREQUENCY GRAPH

Frequency (MHz)

Voltage (VDD)

6.0 V

5.5 V

4.5 V

4.0 V

2.0 V

16 MHz

5.0 V

3.5 V

3.0 V

2.5 V

4 MHz 8 MHz

Fmax = (24 MHz/V)(VDD.APP.MIN - 2.5V) + 4 MHz

Note: VDD.APP.MIN is the minimum VDD of the PICmicro® device in the application.

Fmax is no greater than 16 MHz.

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 7

2.1 DC Characteristics: PIC16LC74B-16/PTL-04 (Commercial)

DC CHARACTERISTICS Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

Param

No. Sym Characteristic Min Typ† Max Units Conditions

D001 VDD Supply Voltage 2.5

VBOR*-

-5.5

5.5 V

VRC, LP, XT, HS osc modes (DC - 4 MHz)

BOR enabled (Note 7)

D002* VDR RAM Data Retention

Voltage (Note 1) -TBD- V

D003 VPOR VDD Start Voltage to

ens ure in ternal

Power-on Reset signal

-V

SS -V

D004*

D004A* SVDD VDD Rise Rate to

ens ure in ternal

Power-on Reset signal

0.05

TBD -

-V/mS

V/mS PWRT enabled (PWRTE bit clear)

PWRT disabled (PWRTE bit set)

D005 VBOR Brown-out Reset

voltage trip point 3.65 - 4.35 V BODEN bit set

D010

D010A

IDD Supply Current

(Not e 2, 5) -

2.0

3.0

22.5

3.8

6.0

µA

XT, RC osc modes

FOSC = 4 MHz, VDD = 3.0V (Note 4)

HS oscillator mode

Fosc = 16MHz, VDD = 3.0V

LP osc mode

FOSC = 32 kHz, VDD = 3.0V, WDT disabled

D021 IPD Power-down Current

(Not e 3, 5) -0.95µAVDD = 3.0V, WDT disabled, 0°C to +70°C

D022*

D022A* ∆IWDT

∆IBOR

Module Differen tial

Current (Note 6)

Watchdog Timer

Brown-out Reset -

-6.0

350 20

425 µA

µAWDTE bit set, VDD = 4.0V

BODEN bit set, VDD = 5.0V

* These parameters are characterized but not tested.

† Data in "Typ" colu mn is at 3V, 25°C unle ss o therwis e sta ted. Thes e par amete rs are f or desig n guid an ce on ly

and are not tested.

Note1: This is the limit to which VDD can be lowered without losing RAM data.

2: The supp ly curre nt is ma inly a fu nction of the ope ratin g v olta ge and freq uency. Other f acto rs suc h as I/O p in

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an

impact on the current consumption.

The test conditions for all IDD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD.

MCLR = VDD; WDT enabled/disabled as specified.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS.

4: F or RC osc mode , current thr ough Re xt i s not inc luded. Th e current throug h the re sistor ca n be esti mated b y

the formula Ir = VDD/2Rext (mA) with Rext in kOhm.

5: Timer1 oscillator (when enabled) adds approximately 20 µA to the spec ification. This value is from charac-

terization and is for design guidance only. This is not tested.

6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base IDD or IPD measurement.

7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.

PIC16LC74B-16/PTL16

DS30026A-page 8 Preliminary  1999 Microchip Technology Inc.

2.2 DC Characteristics: PIC16LC74B-16/PTL-04 (Commercial)

DC CHARACTERI STICS Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

Operating voltage VDD range as described in DC spec Section 2.1

Param

No. Sym Characteristic Min Typ† Max Units Conditions

Input Low Voltage

VIL I/O ports

D030

D030A with TTL buffer VSS

VSS -

-0.15VDD

0.8V V

VFor entire VDD range

4.5V ≤ VDD ≤ 5.5 V

D031 with Schmitt Trigger buffer VSS -0.2VDD V

D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V

D033 OSC1 (in XT, HS and LP

modes) Vss - 0.3VDD VNote1

Input High Voltage

VIH I/O ports -

D040 with TTL buffer 2.0 - VDD V4.5V ≤ VDD ≤ 5.5V

D040A 0.25VDD

+ 0.8V -VDD V For entire VDD range

D041 with Schmitt Trigger buffer 0.8VDD -VDD V For entire VDD range

D042 MCLR 0.8VDD -VDD V

D042A OSC1 (XT, HS and LP modes) 0.7VDD -VDD VNote1

D043 OSC1 (in RC mode) 0.9VDD -VDD V

Input Leakage Current (Notes

2, 3)

D060 IIL I/O ports - - ±1µAVss ≤ VPIN ≤ VDD,

Pin at hi-impedance

D061 MCLR, RA4/T0CKI - - ±5µAVss ≤ VPIN ≤ VDD

D063 OSC1 - - ±5µAVss ≤ VPIN ≤ VDD,

XT, HS and LP osc modes

D070 IPURB PORT B weak pull-up current 50 250 400 µAVDD = 5V, VPIN = VSS

Output Low Voltage

D080 VOL I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

--0.6VIOL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

D083 OSC2/CLKOUT (RC osc

mode) --0.6VIOL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

--0.6VI

OL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C

Output High Voltage

D090 VOH I/O ports (Note 3) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These pa rameters are for design guidance only

and are not tested.

Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

device be driven with extern al clock in RC mo de.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 9

VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

D092 OSC2/CLKOUT (RC osc

mode) VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D150* VOD Open-Drain High Voltage - - 8.5 V RA4 pin

Capacitive Loading Specs

on Output Pins

D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when

external clock is used to drive

OSC1.

D101 CIO All I/O pins and OSC2 (in RC

mode) --50pF

D102 Cb SCL, SDA in I2C mode - - 400 pF

2.2 DC Characteristics: PIC16LC74B-16/PTL-04 (Commercial) (Cont.’d)

DC CHARACTERIS TICS Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

Operating voltage VDD range as described in DC spec Section 2.1

Param

No. Sym Characteristic Min Typ† Max Units Conditions

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These pa rameters are for design guidance only

and are not tested.

Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

device be driven with extern al clock in RC mo de.

2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current may be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

PIC16LC74B-16/PTL16

DS30026A-page 10 Preliminary  1999 Microchip Technology Inc.

2.3 AC (Timing) Characteristics

2.3.1 TIMING PARAMETER SYMBOLOGY

The timing parameter symbols have been created

using one of the following formats:

1. TppS2ppS 3. TCC:ST (I2C specifications only)

2. TppS 4. Ts (I2C specifications only)

TFFrequency TTime

Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1

ck CLKOUT rd RD

cs CS rw RD or WR

di SDI sc SCK

do SDO ss SS

dt Data in t0 T0CKI

io I/O port t1 T1CKI

mc MCLR wr WR

Uppe rcase letters and their meanings:

SFFall PPeriod

HHigh RRise

I Invalid (Hi-impedance) V Valid

L Low Z Hi-impedance

I2C only

AA output access High High

BUF Bus fre e Low Low

TCC:ST (I2C specifications only)

HD Hold SU Setup

DAT DATA input hold STO STOP condition

STA START condition

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 11

2.3.2 TIMING CONDITIONS

The temperature and voltages specified in Table 2-1

apply to all timing specifications unless otherwise

noted. Figure 2-2 specifies the load conditions for the

timing specification s .

TABLE 2-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

FIGURE 2-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0°C ≤ TA ≤+70°C for commercial

Operating voltage VDD range as described in DC spec Section 2.1.

LC parts operate for commercial/industrial temp’s only.

VDD/2

VSS

RL=464Ω

CL= 50 pF for all pins except OSC2/CLKOUT

but including D and E outputs as ports

15 pF for OSC2 output

Load condition 1 Load condition 2

PIC16LC74B-16/PTL16

DS30026A-page 12 Preliminary  1999 Microchip Technology Inc.

2.3.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 2-3: EXTERNAL CLOCK TIMING

TABLE 2-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Param

No. Sym Characteristic Min

(Note 2) Typ† Max

(Note 3) Units Conditions

1A Fosc External CLKIN Frequency

(Note 1) DC — 4 MHz RC and XT osc modes

DC — 4 MHz HS osc mode ( -04)

DC — 20 MHz HS osc mode (-20)

DC — 200 kHz LP osc mode

Oscillator Frequency

(Note 1) DC — 4 MHz RC osc m od e

0.1 — 4 MHz XT osc mode

4 — 20 MHz HS osc mode

5 — 200 kHz LP osc mode

1ToscExternal CLKIN Period

(Note 3) 250 — — ns RC and XT osc modes

250 — — ns HS osc mode (-04)

50 — — ns HS osc mode (-20)

5——µsLP osc mode

Oscillator Period

(Note 3) 250 — — ns RC osc mode

250 — 10,000 ns XT osc mode

250 — 250 ns HS osc mode (-04)

50 — 250 ns HS osc mode (-20)

5——µsLP osc mode

CY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC

3* TosL,

TosH Ext ernal Clock in (OSC1) High

or Low Time 100 — — ns XT oscilla tor

2.5 — — µs LP oscillator

15 — — ns HS oscillator

4* TosR,

TosF Ext ernal Clock in (OSC1) Ris e

or Fall Time — — 25 ns XT oscil la tor

— — 50 ns LP oscillator

— — 15 ns HS oscillator

* These parameters are characterized but not tested.

† Data in " Typ" column is at 5V, 25°C unless otherwi se stat ed. Thes e para met ers are f o r design guidan ce only

and are not tested.

Note1: Instruction cycle period (TCY) equa ls four times the input oscillator time-base p eriod. All s pec ifi ed values are

based on characte rization data f or that pa rticular oscillator typ e under stand ard operati ng conditi ons with the

de vic e e x e cuting code . Exce edi ng thes e specifi ed li mits may result in an uns tab le osc illat or oper ati on and/o r

higher than expected current consumption.

2: All devices are tested to operate at "min ." values with an external clock applied to the OSC1/CLKIN pin.

3: When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices.

344

Q4 Q1 Q2 Q3 Q4 Q1

OSC1

CLKOUT

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 13

FIGURE 2-4: CLKOUT AND I/O TIMING

TABLE 2-3: CLKOUT AND I/O TIMING REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1

11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1

12* TckR C LKOUT rise time — 35 100 ns Note 1

13* TckF CLKOUT fall time — 35 100 ns Note 1

14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5T CY + 20 ns Note 1

15* TioV2ckH Port in valid before CLKOUT ↑ Tosc + 200 — — ns Note 1

16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1

17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns

18A* TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid (I/O in hold time) 200 — — ns

19* TioV2osH Port input valid to O S C1↑ (I/O in setup time) 0 — — ns

20A* TioR Port output rise time — — 80 ns

21A* TioF Port output fall t ime — — 80 ns

22††* Tinp INT pin high or low time TCY ——ns

23††* Trbp RB7:RB4 change INT high or low time TCY ——ns

* These parameters are characterized but not tested.

† Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchronous events not related to any internal clock edge.

Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x TOSC.

Note: Refer to Figure 2.1 for load conditions.

OSC1

CLKOUT

I/O Pin

(input)

I/O Pin

(output)

Q4 Q1 Q2 Q3

13 14

20, 21

19 18

old value new value

PIC16LC74B-16/PTL16

DS30026A-page 14 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 2-6: BROWN-OUT RESET TIMING

TABLE 2-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

AND BROWN-OUT RESET REQUIREMENTS

Pa rameter

No. Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 2 ——

µsVDD = 5V, -40°C to +125°C

31* Twdt W atchdog Timer Time-out P eriod

(No Prescaler) 71833ms

VDD = 5V, -40°C to +125°C

32 Tost Oscillation St art-up Timer Per iod — 1024 TOSC ——

TOSC = OSC1 period

33* Tpwrt Po wer-up Timer Period 28 72 132 ms VDD = 5V, -40°C to +125°C

34 TIOZ I/O Hi-impedance from MCLR

Low or WDT reset ——2.1

µs

35 TBOR Brown-out Reset Pulse Width 100 — — µsVDD ≤ BVDD (D005)

* These parameters are characterized but not tested.

† Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

Note: Refer to Figure 2-2 for load c onditions.

VDD BVDD

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 15

FIGURE 2-7: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

TABLE 2-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

40* Tt0H T0CKI High Pulse Widt h No Prescaler 0.5TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 1 0 — — ns

41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet

parameter 42

With Prescaler 1 0 — — ns

42* Tt0P T0C K I Peri od No Prescaler TCY + 40 — — ns

With Prescaler Greater of:

20 or T CY + 40

— — ns N = prescale value

(2, 4,.. ., 25 6 )

45* Tt1H T 1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

parameter 47

Synchronous, Prescaler = 2,4,8 25 — — ns

Asynchronous 50 — — ns

46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet

parameter 47

Synchronous, Prescaler = 2,4,8 25 — — ns

Asynchronous 50 — — ns

47* Tt1P T1CKI input period Synchronous Greater of:

50 OR TCY + 40

N = presca le value

(1, 2, 4, 8)

Asynchronous 100 — — ns

Ft1 Timer1 oscillator input frequency range

(oscillator enabled by setting bit T1OSCEN) DC — 200 kHz

48 TCKEZtmr1 Delay fro m external clock edge to timer increment 2Tosc — 7Tosc —

* These parameters are characterized but not tested.

† Dat a in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 2-2 for load conditions.

T0CKI

T1OSO/T1CKI

TMR0 o r

TMR1

PIC16LC74B-16/PTL16

DS30026A-page 16 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-8: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

TABLE 2-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

50* TccL CCP1 and CCP2

input low t ime No Prescaler 0.5TCY + 20 ——ns

With Prescaler 2 0 — — ns

51* TccH CCP1 and CCP2

input high time No Prescaler 0.5TCY + 20 — — ns

With Prescaler 2 0 — — ns

52* TccP CCP1 and CCP2 input period 3TCY + 40

N— — ns N = prescale value

(1,4 or 16)

53* TccR CCP1 and CCP2 output rise time — 25 45 ns

54* TccF CCP1 and CCP2 output fall time — 25 45 ns

* These parameters are character ized but not tested.

† Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to F igure 2-2 for load conditions.

CCPx

(Capture Mode)

50 51

CCPx

53 54

(Compare or PWM Mode)

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 17

FIGURE 2-9: PARALLEL SLAVE P ORT TIMING (PIC16LC74B-16/PTL16)

TABLE 2-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16LC74B-16/PTL16)

Parameter

No. Sym Characteristic Min Typ† Max Units Conditions

62* TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20 ——ns

63* TwrH2dtI WR↑ or CS↑ to data–in invalid (hold time) 35 — — ns

64 TrdL2dtV RD↓ and CS↓ to data–out valid — — 80 ns

65* TrdH2dtI RD↑ or CS↑ to data–out inval id 10 — 30 ns

* These parameters are characterized but not tested.

† Data in "Typ" column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 2-2 for load conditions.

RE2/CS

RE0/RD

RE1/WR

RD7:RD0

PIC16LC74B-16/PTL16

DS30026A-page 18 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

TABLE 2-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0)

Param.

No. Symbol Characteristic Min Typ† Max Units Conditions

70 TssL2scH,

TssL2scL SS↓ to SCK↓ or SCK↑ inp ut TCY ——ns

71 TscH SCK input high time

(slave mode) Continuous 1.25TCY + 30 — — ns

71A Single Byte 40 — — ns Note 1

72 TscL SCK input low tim e

(slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns Note 1

73 TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns

73A TB2BLast clock edge of Byte1 to the 1st clock

edge of Byte2 1.5TCY + 40 — — ns Note 1

74 TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO data output rise time — 20 45 ns

76 TdoF SDO data output fall time — 10 25 ns

78 TscR SCK ou tput rise time (master mode) — 20 45 ns

79 TscF SCK output fall time (master mode) — 10 25 ns

80 TscH2doV,

TscL2doV SDO data output valid after SCK edge — — 100 ns

† Data in “Typ” column is at 3V, 25°C unle ss oth erwis e s tate d. Th es e pa ra meters are f or de si gn gu idance only

and are not tested.

Note1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76

MSb LSb

BIT6 - - - - - -1

MSb IN LSb IN

BIT6 - - - -1

Note: Refer to Figure 2-2 for load conditions.

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 19

FIGURE 2-11: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

TABLE 2-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)

Param.

No. Symbol Characteristic Min Typ† Max Units Conditions

71 TscH SCK input high time

(slave mode) Continuous 1.25TCY + 30 ——ns

71A Single Byte 40 — — ns Note 1

72 TscL SCK input low tim e

(slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns Note 1

73 TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK

edge 100 — — ns

73A TB2BLast clock edge of Byte1 to the 1st clock

edge of Byte2 1.5TCY + 40 — — ns Note 1

74 TscH2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO data output rise time 20 45 ns

76 TdoF SDO data output fall time — 10 25 ns

78 TscR SCK output rise time (master mode) 20 45 ns

79 TscF SCK output fall time (master mode) — 10 25 ns

80 TscH2doV,

TscL2doV SDO data output valid after SCK edge — 100 ns

81 TdoV2scH,

TdoV2scL SDO data output setup to SCK edge TCY ——ns

† Data in “Typ” column is at 3V, 25°C unl ess ot herwi se sta ted. The se par amet ers are for design guidan ce only

and are not tested.

Note1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

75, 76

MSb

MSb IN

BIT6 - - - - - -1

LSb IN

BIT6 - - - -1

LSb

Note: Refer to Figure 2.1 for load conditions.

PIC16LC74B-16/PTL16

DS30026A-page 20 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

TABLE 2-10: EXAMPLE SPI MODE REQUIREMENTS (SLA VE MODE TIMING (CKE = 0)

Param.

No. Symbol Characteristic Min Typ† Max Units Conditions

70 TssL2scH,

TssL2scL SS↓ to SCK↓ or SCK↑ inp ut TCY ——ns

71 TscH SCK input high time

(slave mode) Continuous 1.25TCY + 30 — — ns

71A Single Byte 40 — — ns Note 1

72 TscL SCK input low tim e

(slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns Note 1

73 TdiV2scH,

TdiV2scL Setup time of SDI data input to SCK edge 100 — — ns

73A TB2BLast clock edge of Byte1 to the 1st clock

edge of Byte2 1.5TCY + 40 — — ns Note 1

74 TscH 2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO data output rise time 20 45 ns

76 TdoF SDO data output fall time — 10 25 ns

77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns

78 TscR SCK output rise time (master mode) 20 45 ns

79 TscF SCK output fall time (master mode) — 10 25 ns

80 TscH2doV,

TscL2doV SDO data output valid after SCK edge — 100 ns

83 TscH2ssH,

TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — — ns

† Data i n “Typ” colum n i s at 3V, 25°C un les s othe rwis e s tate d. These param et ers are for desig n gu id anc e o nly

and are not tested.

Note1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

73 74

75, 76 77

SDI

MSb LSb

BIT6 - - - - - -1

MSb IN BIT6 - - - -1 LSb IN

Note: Refer to Figure 2-2 for load conditions.

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 21

FIGURE 2-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

TABLE 2-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)

Param.

No. Symbol Characteristic Min Typ† Max Units Conditions

70 TssL2scH,

TssL2scL SS↓ to SCK↓ or SCK↑ input TCY ——ns

71 TscH SCK input high time

(slave mode) Continuous 1.25TCY + 30 — — ns

71A Single Byte 40 — — ns Note 1

72 TscL SCK input low tim e

(slave mode) Continuous 1.25TCY + 30 — — ns

72A Single Byte 40 — — ns Note 1

73A TB2BLast cloc k edge of Byte 1 to the 1st cl oc k

edge of Byte2 1.5TCY + 40 — — ns Note 1

74 TscH 2diL,

TscL2diL Hold time of SDI data input to SCK edge 100 — — ns

75 TdoR SDO data output rise time 20 45 ns

76 TdoF SDO data output fall time — 10 25 ns

77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns

78 TscR SCK output rise time (master mode) — 20 45 ns

79 TscF SCK output fall time (master mode) — 10 25 ns

80 TscH2doV,

TscL2doV SDO data output valid after SCK edge — — 100 ns

82 TssL2doV SDO data output valid after SS↓ edge — — 100 ns

83 TscH2ssH,

TscL2ssH SS ↑ after SCK edge 1.5TCY + 40 — — ns

† Data i n “Typ” column is at 3V, 25°C unl ess othe rwise state d. These paramet ers are f o r design guidance only

and are not tested.

Note1: Specification 73A is only required if specifications 71A and 72A are used.

SCK

(CKP = 0)

SCK

(CKP = 1)

SDO

SDI

71 72

SDI

75, 76

MSb BIT 6 - - - - - -1 LSb

MSb IN BIT6 - - - -1 LSb IN

Note: Refer to Figure 2- 2 for load conditions.

PIC16LC74B-16/PTL16

DS30026A-page 22 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-14: I2C BUS START/STOP BITS TIMING

TABLE 2-12: I2C BUS START/STOP BITS REQUIREMENTS

Parameter

No. Sym Characteristic Min Typ Max Units Conditions

90* TSU:STA START condition 100 kHz mode 4700 —— ns Only relev ant for repeated START

condition

Setup time 400 kHz mode 600 — —

91* THD:STA START condition 100 kHz mode 4000 — — ns After this period the first clock

pulse is generated

Hold time 400 kHz mode 600 — —

92* TSU:STO STOP condition 100 kHz mode 4700 — — ns

Setup time 400 kHz mode 600 — —

93 THD:STO STOP condition 100 kHz mode 4000 — — ns

Hold time 400 kHz mode 600 — —

* These parameters are characterized but not tested.

Note: Refer to Figure 2-2 for load conditions.

SCL

SDA

START

Condition STOP

Condition

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 23

FIGURE 2-15: I2C BUS DATA TIMING

TABLE 2-13: I2C BUS DATA REQUIREMENTS

Parameter

No. Sym Characteristic Min Max Units Conditions

100* THIGH Clock high time 100 kHz mode 4. 0 —µs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 0.6 — µs Device must operate at a

minimum of 10 MHz

SSP Module 1 . 5TCY —

101* TLOW Clock low time 100 k Hz mode 4.7 — µs Device must operate at a

minimum of 1.5 MHz

400 kHz mode 1.3 — µs Device must operate at a

minimum of 10 MHz

SSP Module 1 . 5TCY —

102* TRSDA and SCL rise

time 100 kHz mode — 1000 ns

400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from

10-400 pF

103* TFSDA and SCL fall time 100 kHz mode — 300 ns

400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from

10-400 pF

90* TSU:STA START condition

setup time 100 kHz mode 4.7 — µs Only relevant for repeated

START condition

400 kHz mode 0.6 — µs

91* THD:STA START condition hold

time 100 kHz mode 4.0 — µs After this period the first clock

pulse is generated

400 kHz mode 0.6 — µs

106* THD:DAT Data input hold ti me 100 kHz mode 0 — ns

400 kHz mode 0 0.9 µs

107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2

400 kHz mode 100 — ns

92* TSU:STO STOP condition setup

time 100 kHz mode 4.7 — µs

400 kHz mode 0.6 — µs

109* TAA Output valid from

clock 100 kHz mode — 3500 ns Note 1

400 kHz mode — — ns

110* TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free

bef ore a new transmission can

start

400 kHz mode 1.3 — µs

Cb Bus capacitive loading — 400 pF

* These parameters are characterized but not tested.

Note 1: As a trans mit ter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of

the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement

Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stret ch the LOW period of

the SCL signal. If such a device does stretch the LO W period of the SCL signal, it must output the next data bit to the SD A

line TR max.+tsu; DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C b us specification) before the SCL line

is released.

Note: Refer to Figure 2-2 for load conditions.

91 92

100 101

103

106 107

109 109 110

102

SCL

SDA

Out

PIC16LC74B-16/PTL16

DS30026A-page 24 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-16: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

TABLE 2-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

FIGURE 2-17: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

TABLE 2-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

120* TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock high to data out valid — — 100 ns

121* Tckrf Clock out rise time and fall time (Master Mode) — — 50 ns

122* Tdtrf Data out rise time and fall time — — 50 ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

P arameter

No. Sym Characteristic Min Typ† Max Units Conditions

125* TdtV2ckL SYNC RCV (MASTER & SLAVE)

Data setup before CK ↓ (DT setup time) 15 ——ns

126* TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 2-2 for load conditions.

121 121

120 122

RC6/TX/CK

RC7/RX/DT

Note: Refer to Figure 2-2 for load conditions.

125

126

RC6/TX/CK

RC7/RX/DT

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 25

T ABLE 2-16: A/D CONVERTER CHARACTERISTICS: PIC16LC74B-16/PTL16-04 (COMMERCIAL)

Param

No. Sym Characteristic Min Typ† Max Units Conditions

A01 NRResolution — — 8 bits bit VREF = VDD

A02 EABS Total Absolute error ——< ± 1 LSb VREF = VDD

VSS ≤ VAIN ≤ VREF

A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD

VSS ≤ VAIN ≤ VREF

A04 EDL Different ial linearity error — — < ± 1 LSb VREF = VDD

VSS ≤ VAIN ≤ VREF

A05 EFS Full scale error — — < ± 1 LSb VREF = VDD

VSS ≤ VAIN ≤ VREF

A06 EOFF Of fset error — — < ± 1 LSb VREF = VDD

VSS ≤ VAIN ≤ VREF

A10 — Monotonicity (Note 3) — guar anteed — — VSS ≤ VAIN ≤ VREF

A20 VREF Reference voltage 2.5V — VDD + 0.3 V

A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V

A30 ZAIN Recommended impedance of

analog voltage source — — 10.0 kΩ

A40 IAD A/D conversion current (VDD)—90—

µA Average current consump-

tion when A/D is on.

(Note 1)

A50 IREF VREF input current (Note 2) 10

—

1000

µA

During VAIN acquisition.

Based on differential of

VHOLD to VAIN to charge

CHOLD

During A/D Conversion

cycle

* These parameters are characterized but not tested.

†Data in “Typ” column is at 3V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes

any such leakage from the A/D module.

2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

3: The A/D conversion result never decreases with an increase in the input voltage and has no missing codes.

PIC16LC74B-16/PTL16

DS30026A-page 26 Preliminary  1999 Microchip Technology Inc.

FIGURE 2-18: A/D CONVERSION TIMING

TABLE 2-17: A/D CONVERSION REQUIREMENTS

Param

No. Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period 2.0 ——

µsT

OSC based, VREF full range

3.0 6.0 9.0 µs A/D RC Mode

131 TCNV Conv ersion time (not including S/H time)

(Note 1) 11

Note 2 —

16 11

—TAD

µsV

DD = 3.0V, Temp. = 100°C,

Rs = 10KΩ

132 TACQ Acquisition time 5* — — µs The minimum time is the amplifier

settling time. This may be used if

the "new" input voltage has not

changed by more than 1 LSb (i.e.,

20.0 mV @ 5.12V) from the last

sampled voltage (as stated on

CHOLD).

134 TGO Q4 to A/D clock start — TOSC/2 — — If the A/D clock source is selected

as RC, a time of TCY is added

before the A/D clock starts. This

allows the SLEEP instruction to be

executed.

135 TSWC Switching from convert → sample time 1.5 § — — TAD

* These parameters are characterized but not tested.

† Data in “Typ” colum n is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: ADRES register may be read on the following TCY cycle.

2: See A/D section for minimum requirements.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLIN G STOPPED

DONE

NEW_DATA

(TOSC/2) (1)

7 6543210

Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This

allows the SLEEP instruction to be executed.

1 TCY

134

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 27

3.0 DC AND AC

CHARACTERISTICS GRAPHS

AND TABLES

Graphs and Tables not available at this time.

PIC16LC74B-16/PTL16

DS30026A-page 28 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 29

4.0 PACKAGING INF ORMATIO N

4.1 Package Marking Information

Legend: MM...M Microch ip part number informat ion

XX...X Customer specific information*

AA Year code (last 2 digits of calendar year)

BB Week code (week of January 1 is week ‘01’)

C Facility code of the plant at which wafer is manufactured

O = Outside Vendor

C = 5” Line

S = 6” Line

H = 8” Line

D Mask revis ion number

E Assembly code of the plant or country of origin in which

part was assembled

Note: In the event the full Mi crochip part number ca nno t be marked on one line , it will

be carried over to the next line thus limiting the number of available cha racters

for customer specific information.

*Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask

rev#, and assembly code. For OTP marking beyond this, certain price adders apply. Please check with

your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price.

44-Lead TQFP

XXXXXXXXXX

AABBCDE

MMMMMMMM

XXXXXXXXXX

Example

PIC16LC74B-16/PTL16/PT

9911HAT

PIC16LC74B-16/PTL16

DS30026A-page 30 Preliminary  1999 Microchip Technology Inc.

44-Lead Plastic Thin Quad Flatpac k (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP)

*Contr ol li ng Parameter

Notes:

Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-026

Drawing No. C04-076

1.140.890.64.045.035.025CHPin 1 Corner Chamfer

1.00.039

(F)

Footprint (Reference)

(F)

A1 A2

#leads=n1

D1 D

βL

Units INCHES MILLIMETERS*

Dimension Limits MIN NOM MAX MIN NOM MAX

Number of Pins n44 44

Pitch p.031 0.80

Overall Height A .039 .043 .047 1.00 1.10 1.20

Molded Package Thickness A2 .037 .039 .041 0.95 1.00 1.05

Standoff A1 .002 .004 .006 0.05 0.10 0.15

Foot Length L .01 8 .024 .030 0.45 0.60 0.75

Foot Angle φ03.5 7 03.5 7

Overall Width E .463 .472 .482 11.75 12.00 12.25

Overall Length D .463 .472 .482 11.75 12.00 12.25

Molded Package Width E1 .390 .394 .398 9.90 10.00 10.10

Molded Package Length D1 .390 .394 .398 9.90 10.00 10.10

Pins per Side n1 11 11

Lead Thickness c.004 .006 .008 0.09 0.15 0.20

Lead Width B .012 .015 .017 0.30 0.38 0.44

Mold Draft Angle Top α51015 51015

Mold Draft Angle Bottom β51015 51015

CH x 45°

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 31

APPENDIX A: REVISION HISTORY

Version Date Revision Description

A 6/99 Th is is a ne w d ata sheet provi ding the electrical s pecificati ons f or the 3 V, 16 MHz

device. For all other information, see the PIC16C63A/65B/73B/74B data sheet

(DS30605).

PIC16LC74B-16/PTL16

DS30026A-page 32 Preliminary  1999 Microchip Technology Inc.

NOTES:

 1999 Microchip Technology Inc. Preliminary DS30026A-page 33
PIC16LC74B-16/PTL16
INDEX 
A
A/D Converter Characteristics  ..........................................25
Timing Dia g r a m .............. ................... .......... ...............26
Absolute Maximum Ratings .................................................5
B
Brown-out Reset (BOR)
Timing Dia g r a m .............. ................... .......... ...............14
C
Capture/Compare/PWM (CCP)
Timing Dia g r a m .............. ................... .......... ...............16
D
DC Characteristics ...............................................................8
E
Electrical Characteristics  ......................................................5
Errata ................................................................................... 2
G
General Description  ................. .... .. ....... .... .. .... .. ....... .... .. .... ..3
I
I2C (SSP Module)
Timing Diagram, Data ................................................23
Timing Diagram, Start/Stop Bits .................................22
P
Packaging ..........................................................................29
Parallel Slave Port (PSP)
Timing Dia g r a m .............. ................... .......... ...............17
Power-on Reset (POR)
Timing Dia g r a m .............. ................... .......... ...............14
Product Identific ation System  ............................................37
R
Reset
Timing Dia g r a m .............. ................... .......... ...............14
Revision History .................................................................31
T
Timer0
Timing Dia g r a m .............. ................... .......... ...............15
Timer1
Timing Dia g r a m .............. ................... .......... ...............15
Timing Diagrams and Specifications ..................................12
A/D Conversion ........ .......... ................... ........... ..........26
Brown-out Reset (BOR) .............................................14
Capture/Compare/PWM (CCP) ..................................16
CLKOUT and I/O ........................................................13
External Clock ............................................................12
I2C Bus Data ..............................................................23
I2C Bus Start/Stop Bits ...............................................22
Oscillator Start-up Timer (OST) .................................14
Parallel Slave Port (PSP) ...........................................17
Power-up  Tim e r ( PWRT)   ........................ ........... ........14
Reset ..........................................................................14
Timer0 and Timer1 .....................................................15
USART Synchro nous Receive ( Master/ Slave)  .........24
USART SynchronousTransmission ( Master/Slave) ..24
Watchdog Timer (WDT) .............................................14
U
USART
Synchronous Master Mode
Timing Diagram, Synchronous Receive ............ 24
Timing Diagram, Synchronous Transmission .... 24
W
Watchdog Timer (WDT)
Timing Dia g ram ............................................. ............ 14
WWW, On-Line Support ...................................................... 2

PIC16LC74B-16/PTL16

DS30026A-page 34 Preliminary  1999 Microchip Technology Inc.

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 35

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides

system users a listing of the latest versions of all of

Microchip’s development systems software products.

Plus, this line provides information on how customers

can receive any currently available upgrade kits.The

Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and

1-602-786-7302 for the rest of the world.

Trademarks: The Microchip name, logo , PIC, PICmicro,

PICSTA RT, PICMASTER and PRO MAT E are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

Flex

ROM, MPLAB and

fuzzy-

LAB are trademarks and SQTP is a service mark of Micro-

chip in the U.S.A.

All other trademarks mentioned herein are the property of

their respective companies.

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip

World Wide Web (WWW) site.

The we b site is used b y Mic rochi p as a mean s to mak e

files and information easily available to customers. To

vie w the site , the user must ha v e access to the Internet

and a web browser, such as Netscape or Microsoft

Explorer. Files are also available for FTP download

from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your

favorite Internet browser to attach to:

www.microchip.com

The file transfer site is available by using an FTP ser-

vice to connect to:

ftp://ftp.microchip.com

The web site and file transfer site provide a variety of

services. Users may download files for the latest

Development Tools, Data Sheets, Application Notes,

User’s Guides, Ar ticles and Sample Programs. A vari -

ety of Microchip specific business information is also

available, including listings of Microchip sales offices,

distributors and factory representatives. Other data

available for considerat ion is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked

Questions

• Design Tips

•Device Errata

• Job Post ing s

• Mi c roch ip Consultant Program Member Listing

• Links to other useful web sites related to

Microchip Products

• Conferences for products, Development Sys-

tems, technical information and more

• Listing of seminars and events

981103

PIC16LC74B-16/PTL16

DS30026A-page 36 Preliminary  1998 Microchip Technology Inc.

READER RESPONSE

It is our i ntention to pro vi de you with the bes t d ocu me nta tio n possible to e ns ure s uc ce ssful use of y our Mic r oc hi p pro d-

uct. If you wish to provide your comments on organization, clarity, subject matter , and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To: Technical Publications Manager

RE: Reader Response Total Pages Sent

From: Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional):

Would you like a reply? Y N

Device: Literature Number:

Questions:

FAX: (______) _______ __ - _____ ___ _

DS30026A

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 37

PRODUC T IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factor y or the listed sales office.

* JW Dev ices are UV erasable and can be programmed to any device configuration. JW Dev ic es meet the electrical requirement of

each oscillator type (including LC devices).

PART NO. -XX X/XX L16

PatternPackageTemperature

Range

Frequency

Range

Device

Device PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V to 5.5V

Frequency Range 04 = 4 MHz

16 = 16 MHz

20 = 20 MHz

Temperature Range blank = 0°C to 70°C (Commercial)

Package PT = TQFP (Thin Quad Flatpack)

Pattern QTP, SQTP, Code or Special Requirements

L16 = 3V, 16 MHz

Examples:

a) PIC16LC74B-16/PTL16 = Commercial temp.,

TQFP pa ckage, 16 MHz, l ow voltage VDD limits,

QTP pattern #301.

Note 1: LC = Low Voltage CMOS

2: T = in tape and reel - PLCC, QFP, TQFP

packages only.

PIC16LC74B-16/PTL16

DS30026A-page 38 Preliminary  1999 Microchip Technology Inc.

NOTES:

PIC16LC74B-16/PTL16

 1999 Microchip Technology Inc. Preliminary DS30026A-page 39

NOTES:

Information cont ai ned in this publication regarding device applicat i ons and the li ke is i ntended for suggestion only and m ay be superseded by updates . No repr ese nta tion or warranty is giv en and no liability is assumed

by Microchip Technology Incor porated with res pect to the accurac y or use of such informa tion, or inf ringement of pat ents or other int ellectual property rights aris ing from such use or otherwise. Use of Microchip’ s products

as critical c om ponents in life support sys tems is not authorized exc ept wi th express written approval by Microchip. No lic enses are conveyed , im pl icitly or otherwise, unde r any intelle ct ual property rights. The Micr ochip

logo and name are registered trademarks of Micr och ip Technology Inc. in the U. S.A. and ot her countries . A l l righ ts reserved. All other tr adem arks mentioned herein are the property of their respective companies.

 1999 Microchip Technology Inc.

AMERICAS

Corporate Office

Microchip Technology Inc.

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-786-7200 Fax: 480-786-7277

Technical Support: 480-786-7627

Web Address: http://www.microchip.com

Atlanta

Microchip Technology Inc.

500 Sugar Mill Road, Suite 200B

Atlanta, GA 30350

Tel: 770-640-0034 Fax: 770-640-0307

Boston

Microchip Technology Inc.

5 Mount Royal Avenue

Marlborough, MA 01752

Tel: 508-480-9990 Fax: 508-480-8575

Chicago

Microchip Technology Inc.

333 Pierce Road, Suite 180

Itasca, IL 60143

Tel: 630-285-0071 Fax: 630-285-0075

Dallas

Microchip Technology Inc.

4570 Westgrove Drive, Suite 160

Addison, TX 75248

Tel: 972-818-7423 Fax: 972-818-2924

Dayton

Microchip Technology Inc.

Two Prestige Place, Suite 150

Miamisburg, OH 45342

Tel: 937-291-1654 Fax: 937-291-9175

Detroit

Microchip Technology Inc.

Tri-Atria Office Building

32255 Northwestern Highway, Suite 190

Farmington Hills, MI 48334

Tel: 248-538-2250 Fax: 248-538-2260

Los Angeles

Microchip Technology Inc.

18201 Von Karman, Suite 1090

Irvine, CA 92612

Tel: 949-263-1888 Fax: 949-263-1338

New York

Microchip Technology Inc.

150 Motor Parkway, Suite 202

Hauppauge, NY 11788

Tel: 631-273-5305 Fax: 631-273-5335

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408-436-7950 Fax: 408-436-7955

AMERICAS (continued)

Toronto

Microchip Technology Inc.

5925 Airport Road, Suite 200

Mississauga, Ontario L4V 1W1, Canada

Tel: 905-405-6279 Fax: 905-405-6253

ASIA/PACIFIC

Hong Kong

Microchip Asia Pacific

Unit 2101, Tower 2

Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2-401-1200 Fax: 852-2-401-3431

Beijing

Microchip Technology, Beijing

Unit 915, 6 Chaoyangmen Bei Dajie

Dong Erhuan Road, Dongcheng District

New China Hong Kong Manhattan Building

Beijing 100027 PRC

Tel: 86-10-85282100 Fax: 86-10-85282104

India

Microchip Technology Inc.

India Liaison Office

No. 6, Legacy, Convent Road

Bangalore 560 025, India

Tel: 91-80-229-0061 Fax: 91-80-229-0062

Japan

Microchip Technology Intl. Inc.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-Ku, Yokohama-shi

Kanagawa 222-0033 Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microchip Technology Korea

168-1, Youngbo Bldg. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Korea

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip Technology

RM 406 Shanghai Golden Bridge Bldg.

2077 Yan’an Road West, Hong Qiao District

Shanghai, PRC 200335

Tel: 86-21-6275-5700 Fax: 86 21-6275-5060

ASIA/PACIFIC (continued)

Singapore

Microchip Technology Singapore Pte Ltd.

200 Middle Road

#07-02 Prime Centre

Singapore 188980

Tel: 65-334-8870 Fax: 65-334-8850

Taiwan, R.O.C

Microchip Technology Taiwan

10F-1C 207

Tung Hua North Road

Tai pe i , Ta i wa n, RO C

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berkshire, England RG41 5TU

Tel: 44 118 921 5858 Fax: 44-118 921-5835

Denmark

Microchip Technology Denmark ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

France

Arizona Microchip Technology SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Etage

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH

Gustav-Heinemann-Ring 125

D-81739 München, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Arizona Microchip Technology SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

11/15/99

WORLDWIDE SALES AND SERVICE

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and Tempe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code hopping

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.