AS1138 -- 30W PoE PD and DC-DC Controller GENERAL DESCRIPTION FEATURES The AS1138 is a single-chip, highly integrated CMOS solution for Power over Ethernet (PoE) Powered Devices requiring input power of up to 30Watts. Applications include Voice over IP (VoIP) Phones, Wireless LAN Access Point, Security Cameras, WiMAX Terminals, Point-of-Sales Terminals, RFID Readers, Thin Clients and Notebook computers. The AS1138 integrates input surge protection, a PD controller and a low-emission DC-DC controller. The AS1138 implements all of the physical layer Powered Device (PD) functionality, as required by IEEE(R) 802.3af-2005 and IEEE(R) 802.3at-2009 standards. This includes 2-event classification, Type 2 PSE detection indicator (ATDET), PD detection, under-voltage lock out (UVLO), and HotSwap FET integration. The AS1138 has been architected to address both EM emission concerns and surge/over-voltage protection in PoE applications. The chip implements many design features that minimize transmission of system common-mode noise onto the Unshielded Twisted Pair (UTP). On-chip integration of surge protection provides faster response to surge events and limits stray surge current from passing through sensitive circuits, such as the Ethernet PHY. The device is designed to provide safe, lowimpedance discharge paths directly to the earth ground, resulting in superior reliability and circuit protection. Full support of both IEEE(R) Std. 802.3af-2005 and IEEE(R) Std. 802.3at-2009 power requirements "2-Event" classification for 802.3at higher power PDs Robust Type 2 PSE detector with proprietary digital filtering for line noise to eliminate false positives IEC 61000-4-2/3/4/5/6 requirements for EMC Compliance Integrated Surge Protection for 15kV/8kV System level ESD Compliance Integrated DC-DC controller for exceptional EMI performance Programmable DC current limit up to 720mA for 30W applications Seamless support for local power, down to 9.5V Implemented in robust 100V automotive process Low Rds-on Hot-Swap FET (typical 0.8) Integrated Short-Circuit Protection Over temperature protection Industrial temperature range, -40 to +85C 5x5 mm, 20 lead QFN Package, RoHS compliant TYPICAL APPLICATIONS Pan, tilt and zoom (PTZ), security and web cameras Voice over IP (VoIP) phones Wireless LAN access points, WiMAX terminals Point-of-sale (PoS) terminals, RFID terminals Thin clients and notebook computers Fiber-to-the-home (FTTH) terminals SIMPLIFIED APPLICATION DIAGRAM Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com AS1138 TABLE OF CONTENTS GENERAL DESCRIPTION .............................................................................................................................................................. 1 TYPICAL APPLICATIONS ............................................................................................................................................................... 1 SIMPLIFIED APPLICATION DIAGRAM .......................................................................................................................................... 1 FEATURES ..................................................................................................................................................................................... 1 FIGURES ......................................................................................................................................................................................... 3 TABLES ........................................................................................................................................................................................... 3 PIN DIAGRAM ................................................................................................................................................................................. 4 PACKAGE THERMAL CHARACTERISTICS .................................................................................................................................. 7 TYPICAL PERFORMANCE CHARACTERISTICS .......................................................................................................................... 8 FUNCTIONAL DESCRIPTION ...................................................................................................................................................... 15 OVERVIEW OF POE ..................................................................................................................................................................... 15 AS1138 POE DESIGN................................................................................................................................................................... 15 POWER FEED ALTERNATIVES FOR 10/100/1000 ETHERNET SYSTEMS ............................................................................... 16 AS1138 OVERVIEW ...................................................................................................................................................................... 17 RECTIFICATION AND PROTECTION .......................................................................................................................................... 18 PD CONTROLLER ........................................................................................................................................................................ 18 MODES OF OPERATION ............................................................................................................................................................. 18 RESET ........................................................................................................................................................................................... 18 DETECTION MODE ...................................................................................................................................................................... 18 CLASSIFICATION MODE ............................................................................................................................................................. 18 IDLE MODE ................................................................................................................................................................................... 19 ON STATE ..................................................................................................................................................................................... 19 LOCAL POWER MODE (LVMODE) .............................................................................................................................................. 19 PD CONTROLLER POWER AND THERMAL PROTECTION ....................................................................................................... 21 UNDER VOLTAGE LOCK OUT (UVLO) ........................................................................................................................................ 21 INRUSH CURRENT LIMIT / CURRENT SENSE ........................................................................................................................... 21 THERMAL LIMIT / PROTECTION ................................................................................................................................................. 21 POE POWER-ON STARTUP WAVEFORM .................................................................................................................................. 22 ATDET PIN .................................................................................................................................................................................... 23 DC-DC CONTROLLER .................................................................................................................................................................. 24 OVERVIEW ................................................................................................................................................................................... 24 PROGRAMMABLE PWM FREQUENCY ....................................................................................................................................... 24 CURRENT-LIMIT/CURRENT SENSE ........................................................................................................................................... 24 LOW LOAD CURRENT OPERATION ........................................................................................................................................... 24 COMPENSATION AND FEEDBACK ............................................................................................................................................. 24 SOFT-START ................................................................................................................................................................................ 24 DC-DC CONVERTER TOPOLOGIES ........................................................................................................................................... 25 ISOLATED TOPOLOGIES ............................................................................................................................................................ 25 NON-ISOLATED TOPOLOGIES ................................................................................................................................................... 25 APPLICATION CIRCUITS ............................................................................................................................................................. 26 THERMAL DE-RATING AND BOARD LAYOUT CONSIDERATIONS .......................................................................................... 27 PHYSICAL DIMENSIONS ............................................................................................................................................................. 28 CONTACT INFORMATION ........................................................................................................................................................... 29 IMPORTANT NOTICES ................................................................................................................................................................. 29 LEGAL NOTICE............................................................................................................................................................................. 29 REFERENCE DESIGN POLICY .................................................................................................................................................... 29 LIFE SUPPORT POLICY............................................................................................................................................................... 29 SUBSTANCE COMPLIANCE ........................................................................................................................................................ 30 Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 2 AS1138 FIGURES Figure 1 - AS1138 Pin Diagram ....................................................................................................................................................... 4 Temperature ......................................................................................... 8 Figure 2 - Feedback Error Amplifier VREF vs. Junction Figure 3 - VDD5 vs. Junction Temperature ..................................................................................................................................... 8 Figure 4 - VDD5 vs. VIN ................................................................................................................................................................... 8 Figure 5 - DC Current Limit vs. Junction Temperature .................................................................................................................... 8 Figure 6 - RDSON vs. Temperature @ 350mA, 48V........................................................................................................................... 9 Figure 7 - OSC vs. Temperature ..................................................................................................................................................... 9 Figure 8 - 48V VDD Load Regulation vs. Temperature ..................................................................................................................... 9 Figure 9 - Inrush Current vs. Temperature ...................................................................................................................................... 9 Figure 10 - 48V VDD NDRV vs. Temperature ................................................................................................................................. 10 Figure 11 - Comp Source vs. Temperature ................................................................................................................................... 10 Figure 12 - Comp Sink vs. Temperature ........................................................................................................................................ 10 Figure 13 - Example of VDD48I / VDD48O / Converter Output ..................................................................................................... 10 Figure 14 - PI Input Voltage and Current / ATDET ........................................................................................................................ 11 Figure 15 - 3.3V 30W DC-DC Efficiency vs. Load ......................................................................................................................... 11 Figure 16 - 3.3V 30W End-End Efficiency vs. Load ....................................................................................................................... 11 Figure 17 - 3.3V 30W Load Regulation.......................................................................................................................................... 12 Figure 18 - 3.3V 30W Line Regulation ........................................................................................................................................... 12 Figure 19 - 5V 30W DC-DC Efficiency vs. Load ........................................................................................................................... 12 Figure 20 - 5V 30W End-End Efficiency vs. Load .......................................................................................................................... 12 Figure 21 - 5V 30W Load Regulation............................................................................................................................................. 13 Figure 22 - 5V 30W Line Regulation .............................................................................................................................................. 13 Figure 23 - 12V 30W DC-DC Efficiency vs. Load .......................................................................................................................... 13 Figure 24 - 12V 30W End-End Efficiency vs. Load ........................................................................................................................ 13 Figure 25 - 12V 30W Load Regulation........................................................................................................................................... 14 Figure 26 - 12V 30W Line Regulation ............................................................................................................................................ 14 Figure 27 - IEEE(R) Std. 802.3at-2009 Power Feeding Schemes for 10/100 Systems ................................................................... 16 Figure 28 - AS1138 Top-Level Block Diagram .............................................................................................................................. 17 Figure 29 - 802.3at Typical Power-On Waveform .......................................................................................................................... 22 Figure 30 - LVMODE Implementation ............................................................................................................................................ 19 Figure 31 - PoE PD Controller with a High-Efficiency Isolated Synchronous Flyback DC-DC Converter ...................................... 26 Figure 32 - PoE PD Controller with a Non-Isolated BUCK DC-DC converter ................................................................................ 26 Figure 33 - AS1138 PCB Footprint (Top View) .............................................................................................................................. 27 Figure 34 - Physical Dimensions ................................................................................................................................................... 28 TABLES Table 1 - Pin Assignments ............................................................................................................................................................... 4 Table 2 - Absolute Maximum Ratings ............................................................................................................................................. 5 Table 3 - Normal Operating Conditions ........................................................................................................................................... 5 Table 4 - Electrical Characteristics .................................................................................................................................................. 6 Table 5- Package Thermal Characteristics ...................................................................................................................................... 7 Table 6 - PoE Requirements ......................................................................................................................................................... 15 Table 7 - Classification Settings .................................................................................................................................................... 19 Table 8- ATDET Truth Table ......................................................................................................................................................... 23 Table 9 - LVMODE Configuration .................................................................................................................................................. 20 Table 10 - PWM Switching Frequency Selection ........................................................................................................................... 24 Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 3 AS1138 PIN ASSIGNMENTS AND DESCRIPTIONS Figure 1 - AS1138 Pin Diagram Table 1 - Pin Assignments Pin I/O Name 1 2 3 4 P P nc VDD48O nc VDD48I 5 6 7 8 9 A A A O A GND GND GND VDD5 RCURR 10 11 A A RCLASS LVMODE 12 13 14 15 16 A A A A O FB COMP CSS CS NDRV 17 18 19 O I O VBN FSEL ATDET 20 - nc Paddle P GND Description No Connect Switched 48V supply output No Connect 48 V positive bus pin, fed by the output of the external diode bridge. This bus requires the connection of a detection signature capacitor and resistor. Refer to Detection Mode section. Must be connected to paddle ground (GND) Must be connected to paddle ground (GND) Must be connected to paddle ground (GND) Internal 5 volts bus decoupling point Current limit pin. Connection to paddle ground sets the current limit to ILIM-AF (for 13W applications). Open circuit sets the current limit to ILIM-AT (for 30W applications). Classification resistor connection Local Voltage Mode. When pulled high, LVMODE opens the internal FET switch and keeps the DC-DC controller active. This is a current-mode input pin. It should be pulled to GND when not in use. DC-DC Controller feedback point DC-DC Controller error amplifier compensation network connection DC-DC Controller soft-start capacitor connection point (required). DC-DC Controller peak-current sense input (low side) DC-DC Controller N-MOSFET gate drive DC-DC Controller low-side supply decoupling Frequency Select. This pin sets the switching frequency of the DC-DC converter. IEEE(R) 802.3at-2009 PSE detects. High level output indicates availability of higher system power, either via connection to a Type 2 PSE, or via a local power supply. No Connect Local analog ground. This is the negative output from the external diode bridge and is not isolated from the line input. Key: I = Input O = Output A = Analog signal P = Power Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 4 AS1138 Table 2 - Absolute Maximum Ratings Max Value1 Description Units High-voltage pins (4--VDD48I; 2--VDD48O) under Transient conditions4 100 Volts High-voltage pins (4--VDD48I; 2--VDD48O) Steady-state with internal Surge Clamp 80 Volts Low-voltage pins (8--VDD5; 9-RCURR; 10-- RCLASS; 11--LVMODE; 12--FB; 13--COMP; 14--CSS; 15--CS; 16--NDRV; 17--VBN; 18-- FSEL; 19--ATDET) 6 Volts ESD Ratings Human body model 2 ESD charged device model 2 kV 500 V ESD machine model 200 V System level (contact/air) at RJ-453 8/15 kV Storage temperature 165 C Junction temperature 150 C Temperature 1 Absolute maximum ratings are limits beyond which damage to the device may occur. The human body model is as described in JESD22-A114. 3 System ESD testing done per IEC61000-4-2. 4 Transient conditions like system startup and other noise conditions. Device must not be exposed to sustained over-voltage condition at this level. See section on Rectification and Protection for further details on Integrated Surge Protection. 2 Table 3 - Normal Operating Conditions Unless otherwise noted, specifications are for Vin = 48V. Description VIN-AF (Type 1 PD) VIN-AT (Type 2 PD) Operating temperature range, 1 Min Typical1 37V 42.5V -40C 48V 48V Max 57V 57V +85C Typical specification; not 100% tested. Performance guaranteed by design and/or other correlation methods. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 5 AS1138 Table 4 - Electrical Characteristics Description Min Typical1 PD (all PD voltage limits specified at the RJ45 interface) Inrush current limit (af) - Type 1 50 150 PD Inrush current limit (at) - Type 2 100 295 PD Operating current - Type 1 Operating current - Type 2 Max Units 200 mA For VDD48O 16V during startup 350 mA For VDD48O 16V during startup 350 mA 720 mA Pin 9 (RCURR) pulled to GND; device configured for 13W operation Pin 9 (RCURR) left open; device configured for 30W operation Pin 9 (RCURR) pulled to GND; device configured for 13W operation Pin 9 (RCURR) left open; device configured for 30W operation measured at 350mA input PoE current limit - Type 1 (ILIM-AF) 350 400 500 mA PoE Current limit - Type 2 (ILIM-AT) 720 800 925 mA 0.8 1 2.7 13 14.5 24 6.9 13 4 V V V V V V mA V V V V V V Switch on resistance, RDS-ON Min Detection Signature voltage Max Detection Signature voltage Classification lower threshold Classification upper threshold Min Mark Event voltage Max Mark Event voltage Mark Event current Classification-Mark hysteresis Classification reset voltage ATDET high (VOH) ATDET low (VOL) UVLO threshold, VIN_RISING UVLO threshold, VIN_FALLING DC-DC Controller 10.1 11 20.5 12.5 12.5 22 10 0.25 12.5 1 2.81 4.7 0.0 37 30 4.9 0.02 38 32 6.9 5.1 0.1 42 34 80 200 315 100 225 350 120 250 385 450 500 550 FOSC temperature coefficient NDRV ROUT NDRV voltage 0.12 1.2 4.7 3 Gate drive dynamic response NDRV TR, TF Max. NDRV duty cycle Min. NDRV duty cycle VBN 2.2 2 80 6 4.7 FOSC (SMPS) switching frequency Error amplifier reference voltage VPK, peak current sense threshold voltage at CS Soft start ramp time COMP source current COMP sink current 1.45 500 10 1.5 600 1.55 700 2 80 80 kHz %/C nS nS % % V Comments During Classification, the AS1138 sinks current as defined Table 3. When the input voltage is less than VMARK_TH Min (IEEE(R) 802.3at-2009) during the Classification signature, a Type 2 PD must draw Mark Event current. Under 2mA output 2ma input current Rosc=178k Rosc=100k Rosc=53.6k Rosc=36.8k DC-DC Controller operating frequency, selected by using Rosc (1%) resistor on FSEL pin Output drive resistance NDRV voltage follows VBN power supply voltage 10% - 90% with CLOAD = 1 nF V mV Measured at 350kHz Measured at 350kHz Internal supply voltage; sets VOH of NDRV. Compared to input of the FB pin IPEAK=VPK/RSENSE ms A A Conditions: CSS=100nF FB = 0V, COMP=0V FB = 5V, COMP=5V Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 6 AS1138 Open loop voltage gain (Error amplifier) Small signal unity-gain bandwidth FB leakage (source or sink) Local Power Mode LVMODE threshold low (IIL) LVMODE threshold high (IIH) Local power operating voltage range 80 dB 5 MHz 1 A 20 60 9.5 57 A A V COMP connected to FB. Local power voltage is specified between VDD48O and GND, using LVMODE feature. Note that power transformer must be capable of handling that full voltage range Thermal Protection Thermal shutdown temperature 165 C Thermal shutdown hysteresis 40 C Current reduction temperature threshold Thermal current reduction Thermal current reduction hysteresis 145 C 50 20 % C Power Dissipation Power dissipation, Type 1, PDISS Power dissipation, Type 2, PDISS Max. on-die operating temperature 1 0.3 0.8 0.5 1.3 140 W W C Above this Temp., the AS1138 is disabled. Temperature change required to restore full operation after thermal shutdown Temperature at which thermal current reduction is applied Temperature change required to restore full operation after thermal current reduction Measured at 13W input Measured at 30W input Maximum recommended operating temperature for normal operation Typical specification is not 100% tested. Performance guaranteed by design and/or other correlation methods. PACKAGE THERMAL CHARACTERISTICS Table 5 - Package Thermal Characteristics Min Typical1 Thermal Resistance, 31 Junction to Ambient, JA Thermal Resistance, 3.4 Junction to Case, JC 1 Max Units C/W Comments 20 lead QFN package C/W 20 lead QFN package Typical specification is not 100% tested. Performance guaranteed by design and/or other correlation methods. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 7 AS1138 TYPICAL PERFORMANCE CHARACTERISTICS Figure 2 - Feedback Error Amplifier VREF vs. Junction Temperature Figure 4 - VDD5 vs. VIN 1.75 1.70 1.65 Vref (V) 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 0 50 100 150 Junction Temperature (Degrees C) Figure 3 - VDD5 vs. Junction Temperature Figure 5 - DC Current Limit vs. Junction Temperature Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 8 AS1138 Figure 6 - RDSON vs. Temperature @ 350mA, 48V Figure 8 - 48V VDD Load Regulation vs. Temperature Load Regulation (%) 0.90 Rdson (Ohms) 0.80 0.70 0.60 0.50 -60 -40 -20 0 20 40 60 80 100 Ambient Temperature (Degrees C) Figure 9 - Inrush Current vs. Temperature Frequency (KHz) Figure 7 - OSC vs. Temperature Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 9 AS1138 Figure 10 - 48V VDD NDRV vs. Temperature Figure 12 - Comp Sink vs. Temperature Figure 11 - Comp Source vs. Temperature Figure 13 - Example of VDD48I / VDD48O / Converter Output Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 10 AS1138 Figure 14 - PI Input Voltage and Current / ATDET Figure 16 - 3.3V 30W End-End Efficiency vs. Load % Eff. Figure 15 - 3.3V 30W DC-DC Efficiency vs. Load Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 11 AS1138 Figure 17 - 3.3V 30W Load Regulation Figure 19 - 5V 30W DC-DC Efficiency vs. Load Figure 20 - 5V 30W End-End Efficiency vs. Load Figure 18 - 3.3V 30W Line Regulation Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 12 AS1138 Figure 21 - 5V 30W Load Regulation Figure 23 - 12V 30W DC-DC Efficiency vs. Load Figure 24 - 12V 30W End-End Efficiency vs. Load Figure 22 - 5V 30W Line Regulation Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 13 AS1138 Figure 25 - 12V 30W Load Regulation Figure 26 - 12V 30W Line Regulation 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 48V 41V 57V 44V -0.6 -0.8 -1 0 0.5 1 1.5 2 2.5 Load (Amps) Akros Silicon, Inc. 262 Santa Ana Court, Sunnyvale, CA 94085 USA 408.746.9000 www.AkrosSilicon.com 14 AS1138 valid PD attached (for user and non-PoE device safety). FUNCTIONAL DESCRIPTION To design PoE systems according to standards, the following constraints apply: Overview of PoE Power over Ethernet (PoE) offers an economical alternative for powering end network appliances, such as IP telephones, wireless access points, security and web cameras, and other powered devices (PDs). PoE standards IEEE(R) Std. 802.3af and 802.3at are intended to unify the delivery method of usable power over Ethernet cables to remotely powered client devices. These standards define a method for detecting and querying PDs and then supplying a range of current levels based on the power class the device belongs to. By employing this method, designers can create systems that predict and minimize power usage, allowing the maximum number of devices to be supported on a powered Ethernet network. Table 6 - PoE Requirements Requirement Maximum Type 1 PD input power Maximum Type 2 PD input power 25.5W 44-57V Output voltage from Type 2 PSE 50-57V Minimum operating current limit, Type 1 @ PSE min output voltage 350mA Minimum operating current limit, Type 2 @ PSE min output voltage 600mA 12.5 Input voltage at Type 1 PD interface 37V-57V Input voltage at Type 2 PD interface 42.5V-57V AS1138 POE Design To help designers meet these requirements, the AS1138 is a fully integrated PoE PD controller for Type1 and Type2 PD implementations. The AS1138 meets all system requirements for the IEEE(R) 802.3 standard for Ethernet and all power management requirements for IEEE(R) standard 802.3at-2009. The PSE uses the following 802.3af sequence to detect a connected PD, determine how much power it requires and then initiate supply current to the device: Value 12.95W Output voltage from Type 1 PSE Line resistance, Type 2 operation The power source that provides current through the Ethernet cables to remote devices is referred to as the Power Sourcing Equipment (PSE). The powered device (PD) on the other end of the Ethernet cable negotiates for and receives the agreed-upon power. IEEE(R) Std. 802.3af limits PSE power delivery to <13W at the PD input (Type 1 PD). IEEE(R) 802.3at allows for >13W power levels (Type 2 PD). IEEE(R) Reset -- Power is withdrawn from the PD if the applied voltage falls below a specified level. Signature Detection, -- The PSE detects and evaluates whether the PD is a valid PoE device. Classification -- The PSE reads the power requirement of the PD. The Classification level identifies how much power the PD will require from the Ethernet line. This permits optimum use of the total power available from the PSE. Classification is considered optional by IEEE(R) standard 802.3af-2005 but IEEE(R) standard 802.3at-2009 requires Type 2 PSE to classify the PD for mutual identification. On -- Operational state, during which the PSE provides the allocated power level to the PD. The AS1138 acts as an interface to the PSE, performing all detection, classification, and inrush current limiting control necessary for compliance with the PoE standards. An internal MOSFET and control circuit limits the inrush and steady-state current drawn from the Ethernet line. External diode bridges protect against polarity reversal, to provide alternative A and B detection. The AS1138 also passes the 8kV Contact Discharge and 15kV Air Discharge requirements, tested per IEC 61000-42. EMI compliance of AS1138-based designs has been verified for CISP22 and FCC Class-B radiated and conducted emissions. This sequence occurs as a progressively rising voltage level from the PSE. It is designed to prevent high voltages from being present on an Ethernet line that does not have a Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 15 AS1138 current along the twisted pair cable used for the 10/100/1000 Ethernet signal via center taps on the Ethernet transformers. On the line side of the transformers for the PD, power is delivered through pins 1 and 2 and returned through pins 3 and 6. In Alternative B, a PSE powers the end station by feeding power through pins 4, 5, 7and 8. In a 10/100/1000 system, this is done through the center taps of the Ethernet transformer. In a 10/100 system, power is applied directly to the spare cable pairs without using transformers. POWER FEED ALTERNATIVES FOR 10/100/1000 ETHERNET SYSTEMS The Power Sourcing Equipment (PSE) supplies power to a single PD per node. A PSE located in the Data Terminal Equipment or Repeater is called an endpoint PSE, while a PSE located between MDIs is called a Mid-span PSE. Figure 27 illustrates the power feed options allowed in the 802.3at-2009 standard for 10/100/1000 Ethernet systems. In Alternative A, a PSE powers the end station by feeding Figure 27 - IEEE(R) Std. 802.3at-2009 Power Feeding Schemes for 10/100 Systems The IEEE(R) Std. 802.3at-2009 standard is intended to be fully compliant with all existing non-powered Ethernet systems. As a result, the PSE is required to detect via a well-defined procedure whether or not the connected device is PD compliant and classify (optional in legacy 802.3af-2005 applications) the needed power prior to supplying it to the device. Maximum allowed voltage is 57V to stay within SELV (Safety Extra Low Voltage) limits. Akros Silicon, Inc. 262 Santa Ana Court, Sunnyvale, CA 94085 USA 408.746.9000 www.AkrosSilicon.com 16 AS1138 AS1138 OVERVIEW The AS1138 is a fully integrated PD that provides the functionality required for Power-over-Ethernet (PoE) applications. The optimized architecture reduces external component cost in a small footprint while delivering high performance. Figure 28 - AS1138 Top-Level Block Diagram VDD48I VDD48O ISense2 Power Good Logic + - Power Good Reference LVMODE Mode Control RCURR pmos VBN Therm al Sense VDD48O ATDET PWM Latch St art S Q R Q NDRV St op PoE Control Logic DCM Detect (35%) Oscillator enable DCM Reference + - FSEL 12V GND COMP + - 2R 22V VDD48I 41V 32V IClass 1.20V Reference + - + FB + - R Slope Compensation 1.5V Reference VBN + - ISS CSS + - VDD48I SPDT RCLASS + Class Enable CS 4.8V Reference - VDD5 VBN VDD5/VBN Regulator Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 17 AS1138 RECTIFICATION AND PROTECTION As the supply voltage from the PSE increases from 0V, the AS1138 transitions through the modes of operation in this sequence: To protect against polarity reversal, an external diode bridge is required. In conjunction with the external diode bridge, the AS1138 provides over-voltage and transient protection on the line side of the Hot-Swap FET. The AS1138 is implemented in a robust 100V process technology. By integrating robust input protection circuitry, Akros Silicon has produced a solution that provides much faster response to surge events. The design also limits stray surge current from passing through sensitive circuits, such as the Ethernet PHY device and enables lowimpedance safe discharge paths directly to earth ground. The protection circuit has been carefully designed to ensure that during these surge events, where currents can reach as high as 30A, voltages do not exceed critical breakdown and spark gap limits, protecting the PD from damage by the event. This enables system designers to achieve 15kV/8kV Air/Contact Discharge system ESD performance. If no PSE or local power supply is present, line voltage will be zero, which will hold the AS1138 in the Reset state. The AS1138 does not affect the Ethernet link function. Reset When the voltage supplied to the AS1138 drops below the minimum valid detection voltage (i.e. <2.7V), the chip will enter the Reset state. While in Reset, the power supply to the PD is disconnected, the AS1138 consumes very little power and the device reverts to the pre-detection status. Detection Mode During the detection sequence, the PSE applies a voltage to the PD to read its detection signature. The reading of the signature determines if a PD is present. PD Controller The AS1138 PD Control Interface is designed to provide full PD functionality for IEEE(R) 802.3af and 802.3at compliant systems, with programmable support for standard PD control functions. During detection, the PSE applies two sequential voltages, 1V or more apart, within the detection voltage range of 2.7V to 10.1V. It extracts a detection signature resistance value from the incremental I-V slope. Valid I-V slope resistance values are between 23.75k and 26.25k. The PD Controller provides the following major functions: A resistance/capacitance connection path for the detection signature. Classification current for power classification. Full 30Watt PD supply capability Power management and thermal protection override, including UVLO (Under Voltage Lock Out). ATDET signal output when connected to a Type 2 PSE that can deliver more than 13Watts. 2-Event Physical Layer classification. Maintain Power Signature feature. With the AS1138, detection signature resistance is generated by an external resistor connected between VDD48I and GND. Typically this is a 26.7k, 1% resistor. With this value of RSIGNATURE, the PSE normally detects a total effective signature resistance of approximately 25k, which is centered within the 802.3af/at specification range of 23.75k to 26.25k. Valid PD detection also requires a valid detection signature capacitance of 0.05 to 0.12uF at 2.7 to 10.1V, and 1.9V maximum offset voltage, per the IEEE(R) 802.3af/at standard, measured at the PD input connector. AS1138 detection signature capacitance is generated by an external 0.1uF capacitor connected between VDD48I and GND. The offset voltage is mainly provided by the external diode bridge voltage drop. Modes of Operation The AS1138 has five operating modes: 1. 2. 3. 4. 5. Reset -- all blocks are disabled. Detection -- the external PD detection signature resistance / capacitance components are applied across the input. Classification -- PD indicates power requirements to the PSE via a Single-Event Classification for 802.3af or a 2-Event Physical Layer Classification for 802.3at. Idle -- this state is entered after Classification, and remains until full-power input voltage is applied. On -- The PD is enabled, and supplies power to the DC-DC controller and the local application circuitry. Classification Mode Each class represents a power allocation range for a PD to assist the PSE in managing power distribution. IEEE(R) Std. 802.3at defines classes of power levels for PDs, listed in Table 3. The AS1138 supports 2-Event Physical Layer classification, per IEEE(R) Std. 802.3at, as shown in Figure 30. The AS1138 identifies the PSE as either Type 1 or Type 2. If the 2-Event method is detected by the PD controller during the classification stage, it asserts the ATDET pin Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 18 AS1138 Table 7 - Classification Settings High, indicating connection to a Type 2 PSE. If the PD controller detects only single-event classification, it identifies the PSE to be Type 1 and the ATDET pin is asserted low. In real applications, noise or transient ringing on the line during classification phase can lead to false 2-event classification or Type 2 PSE detection. To prevent such false positives, the AS1138 integrates a proprietary digital filter to filter out noise events as long as 100uS during the classification phase, ensuring a very reliable AT Detection. Power (W) ICLASS (mA) RCLASS (k) 0 0.44-12.95 0-4 mA Pull-up (0-100k) to VDD5 pin 1 0.44-3.84 9-12 mA 280k, 1% 2 3.84-6.49 17-20 mA 143k, 1% 3 6.49-12.95 26-30 mA 90.9k, 1% 4 12.96-25.5 36-44 mA 63.4k, 1% Idle Mode After the classification process, the PD enters Idle mode while it waits for On-state power delivery from the PSE. PD Current usage is limited to monitoring circuitry to detect the On-state voltage threshold. If a PSE is Type 1, to classify the AS1138, the Type 1 PSE presents a voltage between 14.5V and 20.5V to the PD and determines its class by measuring the resulting PD load current. If a PSE is Type 2, in order to classify the AS1138 as the Type 2 PD, AS1138 has to be set as Class 4 (classification setting shown in Table 3), so that AS1138 returns a Class 4 signature. On State In the On state, the AS1138 is supplying power across the Ethernet line(s) to the PD. At a voltage at or below 42V, the PD turns on and full power is available via the AS1138 DCDC Controller. The AS1138 allows the user to program the classification current via an external resistor connected to the RCLASS pin. Current, power levels and programming resistor values for each class are shown in Table 3. Note that for Class 0, Rclass pin needs to be Pulled Up to VDD5 pin. This can be a direct short to VDD5 or using a resistor up to 100k. Local Power Mode (LVMODE) The LVMODE pin can be used in applications where the PD appliance is designed to draw power from either the Ethernet cable or an external DC local power adapter. The LVMODE pin is a current-mode input pin, with low and high thresholds as defined in the parametric tables (see Error! Reference source not found.). The LVMODE is asserted when the input current exceeds the IIH threshold, and is deasserted when the input current is below the IIL threshold. If LVMODE operation is not desired, the LVMODE pin should be connected to GND. Use the following equation to determine the typical classification current: I CLASS [ mA] = 2.0 + Class 2360 RCLASS [ k ] Tolerance = Maximum of 1.8mA or 9% RCLASS > 63.4k Figure 30 below shows a simplified internal implementation and external application circuit required to use the LVMODE feature. When power is applied at the local adapter input, the AS1138 enters Local Voltage Mode. This opens the internal Hot-Swap FET switch while the DC-DC converter is in operation. Once the classification process is done, the PD removes the classification current to conserve power. Note: During the classification of a Type 2 PD, the PSE outputs a sequence of voltage signals (Class 1, Mark 1, Class 2, Mark 2, and Class 3) within the specific timing requirement. The PD has to respond within the limit range of voltage/current/impedance for each event according to section 33.3.5 PD Classifications of 802.3at standard. In this configuration, local power always takes priority, even in presence of PoE power, irrespective of their relative voltages. If local power is removed, the device will exit Local Voltage Mode operation and PoE power will be used, if available. Figure 29 - LVMODE Implementation Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 19 AS1138 Local power is inserted at the VDD48O node through an external diode (D2). Use of a low reverse-leakage diode is recommended (<350uA, at worst case temperature). This ensures that when there is no local power, PoE voltage at the VDD48O node will not falsely pull up the LVMODE pin due to high reverse leakage through the diode. Please see Table 5 for part number information. An appropriate ratio of R2 and R1 resistors should be used to ensure proper operation across all supply voltages. Table 5 lists appropriate choices of R2 and R1 resistors to work with a variety of popular local adapter DC voltages. Though a common value of R2 and R1 can be used across the whole range of local supply voltages from 9.5V to 57V, using different value pairs, per the table below, will minimize power consumption. The maximum input voltage at the LVMODE pin should not exceed 6V, so a Zener diode (D1) is recommended to limit transient voltage excursions at the pin. Since the input current at the LVMODE pin defines its state, it is not recommended to drive other circuits or components directly from the LVMODE node (such as an LED) that might draw current. LEDs or current-absorbing components may be driven directly from the Local Supply pin. The AS1138 internal DC-DC controller is designed to operate with input voltages of 9.5V-57V, to allow applications to take advantage of the LVMODE feature. Besides configuring the device for operation from a local power source, the external power transformer must also be designed to ensure proper operation across the complete input range. Table 8 - LVMODE Configuration Local Voltage Range Recommended Local Adapters R2 R1 9.5V-57V 12V, 18V 2.74k 4.02k 20V-57V 24V, 30V 11.3k 4.02k 32.4V-57V 36V, 48V 20k 4.02k Diode D1: 5.6V Zener, BZT56V Diode D2: S3B (100V/3A, worst-case reverse leakage <250uA), use of a low reverse-leakage diode with worst-case reverse leakage under high temperature <350uA is recommended. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 20 AS1138 The AS1138 contains line Under-Voltage Lock Out (UVLO) circuitry to determine when to power on the PD. If the PSE supply voltage at PD PI is equal or greater than UVLO VIN_RISING, the AS1138 PD will power on and run; if the PSE supply voltage at PD PI drops below UVLO VIN_FALLING, the AS1138 PD will power off. The PD circuit controls power flow to the DC-DC controller, to protect the PD from erratic operation or damage. power MOSFET. The power MOSFET can also be shut off completely by either the PD Controller, the Thermal Limit Protection circuitry or the insertion of a local power adapter that causes the LVMODE pin to be pulled high (via a resistor divider). During the PD startup sequence, VDS across the Hot-Swap FET is momentarily high as the VDD48O output capacitance is charged up, as illustrated in Figure 14. During this state, the Hot-Swap FET experiences a high instantaneous power drop and heating. Therefore, it is recommended that during this startup sequence, the incoming current should only be utilized for the charging of the VDD48O node, to minimize the startup time and associated power drop across the FET. The primary PWM controller is designed to accommodate for VDD48O startup before drawing power from the line. However, if the application requires direct use of the VDD48O node for other functions, the startup of those circuits should be delayed until the VDD48O node has reached its full voltage level. Inrush Current Limit / Current Sense Thermal Limit / Protection Inrush limiting maintains the cable voltage above the turnoff threshold as the input capacitor charges. This also prevents the PSE from going into current limit mode. The Current Limit/Current Sense circuitry also minimizes the PD on-chip temperature peaks by limiting both inrush and operating current. The AS1138 provides thermal protection for itself by monitoring die temperature and reducing maximum current or disconnecting power as needed to prevent its pre-set thermal limits from being exceeded. Two-stage thermal current limiting is implemented, which reduces the operating current limit by 50% when the die temperature reaches 145C, and disables the power MOSFET switch above 165C. Normal current limits in both cases are reapplied when the die temperature returns below 125C. PD CONTROLLER POWER THERMAL PROTECTION AND The AS1138 provides the following PD controller power and thermal protection: Under Voltage Lock Out (UVLO) Inrush Current Limit with integrated current sense Thermal Limit / Protection Under Voltage Lock Out (UVLO) Current is monitored with an integrated sense circuit that regulates the gate voltage on an integrated low-leakage Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 21 AS1138 POE POWER-ON STARTUP WAVEFORM Figure 29 represents the power-on sequence for PoE operation. The waveform reflects typical voltages present at the PD during signature, classification and power-on. Figure 30 - 802.3at Typical Power-On Waveform 1. Voltages V1 and V2 are applied by the PSE to extract a signature value. 2. The PSE takes current/impedance readings during Class/Mark Events to determine the class of the PD. At this time, the PD presents a load current determined by the resistance connected to the RCLASS pin. 3. After the PSE measures the PD load current, if it is a high-power PSE, it presents a mark voltage (6.9-10V), followed by a second classification voltage. The PD responds by presenting a load current as determined by the resistor on the RCLASS pin. After the PSE measures the PD load current the second time and determines that is can deliver the requested power, it moves into the On state by raising the voltage to approximately 42V. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 22 AS1138 ATDET PIN down event. ATDET pin remains low if it identifies the PSE partner to be Type 1 during the Classification phase. The ATDET output pin provides an indicator when 2-event classification is detected by being linked to a Type 2 PSE, or through the use of a local power supply that uses the LVMODE feature. This indicates system has more than 13W of available power. This pin can be used by the PD system controller to self-configure the application device based on available power. If LVMODE is asserted when supplying local power, the ATDET pin is forced high, irrespective of the PD mode. Please see Table 4 below for ATDET output definitions under various powering modes. Table 9- ATDET Truth Table ATDET signal status If there is no local power present, ATDET will stay low during PD Reset, Detection and Classification phases. The ATDET pin will be set high once the PD recognizes the completion of the 2-Event Physical Layer Classification, as initiated by a Type 2 PSE. The pin will remain high and will only be reset low by the occurrence of a Reset or a power- PSE Type 1 Type 2 LVMODE = Low Low High LVMODE = High High High Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 23 AS1138 DC-DC CONTROLLER Compensation and Feedback Overview For isolated applications, loop compensation and output voltage feedback is generally provided by an opto-isolator circuit, and the Feedback pin (FB) is tied to ground. In these applications, the COMP pin is pulled up to approximately 4.8V by an internal current source. This pull-up can be the termination for an opto-isolator, or, an additional resistor can be used in parallel. The DC-DC architecture is a current-mode controller configurable with external components to fly-back, forward or buck topologies. Both non-isolated and isolated topologies are supported. As part of a full system-level solution to control EMI, Akros has focused significant attention on reducing switching noise in the integrated power converters through unique methods of shaping FET driver waveforms. Ground bounce is also reduced by minimizing dV/dt switching noise. The integrated DC-DC controller operates from a switched input voltage (VDD48O) and includes a programmable soft start and current limiting. Once input power is applied and enable signals are asserted, the DC-DC controller starts up. The controller provides a gate control signal, NDRV, to the external switching MOSFET and uses an external resistor to sense primary current in the transformer. It also provides for an 80% maximum duty cycle, programmable PWM switching frequency and a true voltage-output error amplifier. Programmable PWM Frequency The FSEL pin allows the DC-DC converter switching frequency to be set externally. Placing a resistor between FSEL and GND sets the internal oscillator's frequency Table 6 identifies the resistor values for some commonly-used switching frequencies. Table 10 - PWM Switching Frequency Selection Switching Frequency (kHz) FSEL Resistor (k, 1%) 100 (kHz) 178k 225 (kHz) 100k 350 (kHz) 53.6k 500 (kHz) 36.8k For non-isolated applications, a resistive divider network, connected directly to the FB pin, senses the output voltage. The internal error amplifier is connected to a 1.5V reference voltage and the control loop will servo the FB pin to this voltage. A capacitive/resistive network connected to the COMP pin provides loop compensation. Soft-Start A capacitor is required on the CSS pin, and is used to provide a controlled application power supply startup. Upon device power on, the capacitor on the CSS pin is slowly charged by the AS1138. In isolated designs this charging soft start voltage level limits the maximum voltage "seen" on the CS pin to: VCS_MAX VCSS -1 And since peak current detection is: IPK = VCS/RCS the maximum Flyback output current ramps with VCS, providing a soft start. For example, a 12V output flyback design with a max duty cycle of 45% and a CSS cap of 330nF will have a soft start of ~8ms. For non-isolated designs, the soft start time (TSS) in seconds for a given capacitor (CCSS) is defined by the formula: Current-Limit/Current Sense The DC/DC controller provides cycle-by-cycle current limit monitoring, via the CS input, to ensure that transformer current limits are not exceeded. A short-circuit event is declared if the CS sensed current limit is triggered on 32 consecutive PWM clock cycles. Once a short-circuit event has been declared, the PWM will shut off for 256 cycles before a restart is attempted. This process will repeat indefinitely until the output short is removed. Tss = 1.5CCSS 10 A For example, in a non-isolated design, a 100nF capacitor creates a soft start time of ~15ms. Low Load Current Operation The internal circuitry detects a low output power condition and puts the DC-DC Controller into a discontinuous current operation (DCM) mode. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 24 AS1138 DC-DC CONVERTER TOPOLOGIES Non-Isolated Topologies Isolated Topologies The Buck mode is used in non-isolated applications. This application uses inductor for energy storage, instead of a transformer. See Figure 32. The DC-DC controller can be configured in several different isolated topologies. The Flyback mode is chosen when a minimum number of external components is desired, or there is a large step-down and the output voltage is < 7V. The Forward mode is chosen when lower switching noise is desired. Either of these isolated topologies can be designed for synchronous or non-synchronous operation, based on system requirements. A typical Isolated Synchronous Flyback design is shown in Figure 31. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 25 AS1138 APPLICATION CIRCUITS Figure 31 - PoE PD Controller with a High-Efficiency Isolated Synchronous Flyback DC-DC Converter Note: This is a simplified conceptual schematic. Please refer to the reference design documentation for detailed design and component information. Full PoE implementation will require two input diode bridges. For simplicity, only one is shown here. Figure 32 - PoE PD Controller with a Non-Isolated BUCK DC-DC converter Note: This is a simplified conceptual schematic. Please refer to the reference design documentation for detailed design and component information. Full PoE implementation will require two input diode bridges. For simplicity, only one is shown here. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 26 AS1138 THERMAL DE-RATING AND LAYOUT CONSIDERATIONS If the PCB landing pattern is properly designed, the QFN package should exhibit a thermal resistance of JA=31C/W. For adequate heat dissipation, the board layout must include a ground pad which provides both the ground connection and dissipates the heat energy produced in the chip. Thermal vias are used to draw heat away from the PD package and to transfer it to the backside of the system PCB. BOARD The AS1138 is capable of operating to an industrial temperature range of 85 C in ambient air, without forced cooling. A thermal pad on the underside of the package dissipates the heat generated by the PD die. In 30W applications, designers must consider thermal dissipation as an integral part of their system architecture and plan to remove heat via this pad. The recommended PCB layout for the AS1138 is shown in Figure 33 below: Figure 33 - AS1138 PCB Footprint (Top View) Pin 20 0.3 mm Pin 1 Thermal Vias 0.31 mm dia. 1.27 mm pitch 9 places 0.5 mm 0.65 mm 3.80 mm 0.4 mm 3.80 mm Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 27 AS1138 PHYSICAL DIMENSIONS 20 Pin QFN Package, 5mm X 5mm Figure 34 - Physical Dimensions Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 28 AS1138 Contact Information Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250 San Jose, CA 95119 USA Tel: (408) 746 9000 Fax: (408) 746-9391 Email inquiries: marcom@akrossilicon.com Website: http://www.akrossilicon.com Important Notices Legal notice Copyright (c) 2014 Akros SiliconTM. All rights reserved. Other names, brands and trademarks are the property of others. Akros SiliconTM assumes no responsibility or liability for information contained in this document. Akros reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. The information contained herein is believed to be accurate and reliable at the time of printing. Reference design policy This document is provided as a design reference and Akros Silicon assumes no responsibility or liability for the information contained in this document. Akros reserves the right to make corrections, modifications, enhancements, improvements and other changes to this reference design documentation without notice. Reference designs are created using Akros Silicon's published specifications as well as the published specifications of other device manufacturers. This information may not be current at the time the reference design is built. Akros Silicon and/or its licensors do not warrant the accuracy or completeness of the specifications or any information contained therein. Akros does not warrant that the designs are production worthy. Customer should completely validate and test the design implementation to confirm the system functionality for the end use application. Akros Silicon provides its customers with limited product warranties, according to the standard Akros Silicon terms and conditions. For the most current product information visit us at www.AkrosSilicon.com Life support policy LIFE SUPPORT: AKROS' PRODUCTS ARE NOT DESIGNED, INTENDED, OR AUTHORIZED FOR USE AS COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS. NO WARRANTY, EXPRESS OR IMPLIED, IS MADE FOR THIS USE. AUTHORIZATION FOR SUCH USE SHALL NOT BE GIVEN BY AKROS, AND THE PRODUCTS SHALL NOT BE USED IN SUCH DEVICES OR SYSTEMS, EXCEPT UPON THE WRITTEN APPROVAL OF THE PRESIDENT OF AKROS FOLLOWING A DETERMINATION BY AKROS THAT SUCH USE IS FEASIBLE. SUCH APPROVAL MAY BE WITHHELD FOR ANY OR NO REASON. "Life support devices or systems" are devices or systems which (1) are intended for surgical implant into the human body, (2) support or sustain human life, or (3) monitor critical bodily functions including, but not limited to, cardiac, respirator, and neurological functions, and whose failure to perform can be reasonably expected to result in a significant bodily injury to the user. A "critical component" is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 29 AS1138 SUBSTANCE COMPLIANCE With respect to any representation by Akros Silicon that its products are compliant with RoHS, Akros Silicon complies with the Restriction of the use of Hazardous Substances Standard ("RoHS"), which is more formally known as Directive 2002/95/EC of the European Parliament and of the Council of 27 January 2003 on the restriction of the use of certain hazardous substances in electrical and electronic equipment. To the best of our knowledge the information is true and correct as of the date of the original publication of the information. Akros Silicon bears no responsibility to update such statements. Revision: Version 1.9 Release Date: June 3, 2015 Akros Silicon, Inc. 6399 San Ignacio Avenue, Suite 250, San Jose, CA 95119 USA 408.746.9000 www.AkrosSilicon.com 30