06 Spartan-3 FPGA Family: Introduction and Ordering Information R DS099-1 (v1.4) January 17, 2005 0 0 Preliminary Product Specification Introduction - The SpartanTM-3 family of Field-Programmable Gate Arrays is specifically designed to meet the needs of high volume, cost-sensitive consumer electronic applications. The eight-member family offers densities ranging from 50,000 to five million system gates, as shown in Table 1. The Spartan-3 family builds on the success of the earlier Spartan-IIE family by increasing the amount of logic resources, the capacity of internal RAM, the total number of I/Os, and the overall level of performance as well as by improving clock management functions. Numerous enhancements derive from state-of-the-art VirtexTM-II technology. These Spartan-3 enhancements, combined with advanced process technology, deliver more functionality and bandwidth per dollar than was previously possible, setting new standards in the programmable logic industry. Because of their exceptionally low cost, Spartan-3 FPGAs are ideally suited to a wide range of consumer electronics applications, including broadband access, home networking, display/projection and digital television equipment. The Spartan-3 family is a superior alternative to mask programmed ASICs. FPGAs avoid the high initial cost, the lengthy development cycles, and the inherent inflexibility of conventional ASICs. Also, FPGA programmability permits design upgrades in the field with no hardware replacement necessary, an impossibility with ASICs. Features * * * * * * * * * Very low cost, high-performance logic solution for high-volume, consumer-oriented applications - Densities as high as 74,880 logic cells Table 1: Summary of Spartan-3 FPGA Attributes Device * CLB Array (One CLB = Four Slices) System Equivalent Gates Logic Cells Rows Columns Total CLBs Three power rails: for core (1.2V), I/Os (1.2V to 3.3V), and auxiliary purposes (2.5V) SelectIOTM signaling - Up to 784 I/O pins - 622 Mb/s data transfer rate per I/O - 18 single-ended signal standards - 6 differential I/O standards including LVDS, RSDS - Termination by Digitally Controlled Impedance - Signal swing ranging from 1.14V to 3.45V - Double Data Rate (DDR) support Logic resources - Abundant logic cells with shift register capability - Wide multiplexers - Fast look-ahead carry logic - Dedicated 18 x 18 multipliers - JTAG logic compatible with IEEE 1149.1/1532 SelectRAMTM hierarchical memory - Up to 1,872 Kbits of total block RAM - Up to 520 Kbits of total distributed RAM Digital Clock Manager (up to four DCMs) - Clock skew elimination - Frequency synthesis - High resolution phase shifting Eight global clock lines and abundant routing Fully supported by Xilinx ISE development system - Synthesis, mapping, placement and routing MicroBlazeTM processor, PCI, and other cores Pb-free packaging options Low-power Spartan-3L Family and Automotive Spartan-3 XA Family options Distributed RAM (bits1) Block RAM (bits1) Dedicated Multipliers DCMs Maximum User I/O Maximum Differential I/O Pairs 56 XC3S502 50K 1,728 16 12 192 12K 72K 4 2 124 XC3S2002 200K 4,320 24 20 480 30K 216K 12 4 173 76 XC3S4002 400K 8,064 32 28 896 56K 288K 16 4 264 116 XC3S10002, 3 1M 17,280 48 40 1,920 120K 432K 24 4 391 175 XC3S15003 1.5M 29,952 64 52 3,328 208K 576K 32 4 487 221 XC3S2000 2M 46,080 80 64 5,120 320K 720K 40 4 565 270 XC3S40003 4M 62,208 96 72 6,912 432K 1,728K 96 4 712 312 XC3S5000 5M 74,880 104 80 8,320 520K 1,872K 104 4 784 344 Notes: 1. By convention, one Kb is equivalent to 1,024 bits. 2. These devices are available in Xilinx Automotive versions as described in DS314: Spartan-3 Automotive XA FPGA Family. 3. XC3S1000, XC3S1500, and XC3S4000 are also available in lower static power versions as described in DS313: Spartan-3L Low Power FPGA Family. (c) 2005 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS099-1 (v1.4) January 17, 2005 Preliminary Product Specification www.xilinx.com 1 R Spartan-3 FPGA Family: Introduction and Ordering Information Architectural Overview The Spartan-3 family architecture consists of five fundamental programmable functional elements: * * * * * Configurable Logic Blocks (CLBs) contain RAM-based Look-Up Tables (LUTs) to implement logic and storage elements that can be used as flip-flops or latches. CLBs can be programmed to perform a wide variety of logical functions as well as to store data. Input/Output Blocks (IOBs) control the flow of data between the I/O pins and the internal logic of the device. Each IOB supports bidirectional data flow plus 3-state operation. Twenty-four different signal standards, including seven high-performance differential standards, are available as shown in Table 2. Double Data-Rate (DDR) registers are included. The Digitally Controlled Impedance (DCI) feature provides automatic on-chip terminations, simplifying board designs. Block RAM provides data storage in the form of 18-Kbit dual-port blocks. Multiplier blocks accept two 18-bit binary numbers as inputs and calculate the product. Digital Clock Manager (DCM) blocks provide self-calibrating, fully digital solutions for distributing, delaying, multiplying, dividing, and phase shifting clock signals. These elements are organized as shown in Figure 1. A ring of IOBs surrounds a regular array of CLBs. The XC3S50 has a single column of block RAM embedded in the array. Those devices ranging from the XC3S200 to the XC3S2000 have two columns of block RAM. The XC3S4000 and XC3S5000 devices have four RAM columns. Each column is made up of several 18K-bit RAM blocks; each block is associated with a dedicated multiplier. The DCMs are positioned at the ends of the outer block RAM columns. The Spartan-3 family features a rich network of traces and switches that interconnect all five functional elements, transmitting signals among them. Each functional element has an associated switch matrix that permits multiple connections to the routing. DS099-1_01_032703 Notes: 1. The two additional block RAM columns of the XC3S4000 and XC3S5000 devices are shown with dashed lines. The XC3S50 has only the block RAM column on the far left. Figure 1: Spartan-3 Family Architecture 2 6 www.xilinx.com DS099-1 (v1.4) January 17, 2005 Preliminary Product Specification R Spartan-3 FPGA Family: Introduction and Ordering Information Configuration Spartan-3 FPGAs are programmed by loading configuration data into robust static memory cells that collectively control all functional elements and routing resources. Before powering on the FPGA, configuration data is stored externally in a PROM or some other nonvolatile medium either on or off the board. After applying power, the configuration data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel, Master Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel modes use an 8-bit wide SelectMAPTM port. The recommended memory for storing the configuration data is the low-cost Xilinx Platform Flash PROM family, which includes the XCF00S PROMs for serial configuration and the higher density XCF00P PROMs for parallel or serial configuration. I/O Capabilities The SelectIO feature of Spartan-3 devices supports 18 single-ended standards and 6 differential standards as listed in Table 2. Many standards support the DCI feature, which uses integrated terminations to eliminate unwanted signal reflections. Table 3 shows the number of user I/Os as well as the number of differential I/O pairs available for each device/package combination. Table 2: Signal Standards Supported by the Spartan-3 Family Standard Category Description VCCO (V) Class N/A Terminated Symbol DCI Option Single-Ended GTL Gunning Transceiver Logic GTL Yes GTLP Yes I HSTL_I Yes III HSTL_III Yes I HSTL_I_18 Yes II HSTL_II_18 Yes III HSTL_III_18 Yes 1.2 N/A LVCMOS12 No 1.5 N/A LVCMOS15 Yes 1.8 N/A LVCMOS18 Yes 2.5 N/A LVCMOS25 Yes 3.3 N/A LVCMOS33 Yes LVTTL No Plus HSTL High-Speed Transceiver Logic 1.5 1.8 LVCMOS Low-Voltage CMOS LVTTL Low-Voltage Transistor-Transistor Logic 3.3 N/A PCI Peripheral Component Interconnect 3.0 33 MHz PCI33_3 No SSTL Stub Series Terminated Logic 1.8 N/A (6.7 mA) SSTL18_I Yes N/A (13.4 mA) SSTL18_II No I SSTL2_I Yes II SSTL2_II Yes LDT_25 No LVDS_25 Yes BLVDS_25 No LVDSEXT_25 Yes 2.5 Differential LDT (ULVDS) Lightning Data Transport (HyperTransportTM) LVDS Low-Voltage Differential Signaling 2.5 N/A Standard Bus Extended Mode LVPECL Low-Voltage Positive Emitter-Coupled Logic 2.5 N/A LVPECL_25 No RSDS Reduced-Swing Differential Signaling 2.5 N/A RSDS_25 No DS099-1 (v1.4) January 17, 2005 Preliminary Product Specification www.xilinx.com 3 R Spartan-3 FPGA Family: Introduction and Ordering Information Table 3: Spartan-3 I/O Chart Available User I/Os and Differential (Diff) I/O Pairs VQ100 VQG100 Device CP132 CPG132 TQ144 TQG144 PQ208 PQG208 FG320 FT256 FTG256 FGG320 FG456 FGG456 FG676 FGG676 FG900 FGG900 FG1156 FGG1156 User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff XC3S50 63 29 89 44 97 46 124 56 - - - - - - - - - - - - XC3S200 63 29 - - 97 46 141 62 173 76 - - - - - - - - - - XC3S400 - - - - 97 46 141 62 173 76 221 100 264 116 - - - - - - XC3S1000 - - - - - - - - 173 76 221 100 333 149 391 175 - - - - XC3S1500 - - - - - - - - - - 221 100 333 149 487 221 - - - - XC3S2000 - - - - - - - - - - - - 333 149 489 221 565 270 - - XC3S4000 - - - - - - - - - - - - - - 489 221 633 300 712 312 XC3S5000 - - - - - - - - - - - - - - - - 633 300 784 344 Notes: 1. All device options listed in a given package column are pin-compatible. 2. User = User I/O pins. Diff = Differential I/O pairs. Package Marking Mask Revision Code Fabrication Code F = UMC 8D (200 mm) G = UMC 12A (300 mm) R SPARTAN XC3S50TM PQ208AFQ0350 xxxxxxxxx 4C R Device Type Package Speed Grade Process Technology Q = 90 nm Date Code Lot Code Temperature Range ds099-1_03_011705 4 6 www.xilinx.com DS099-1 (v1.4) January 17, 2005 Preliminary Product Specification R Spartan-3 FPGA Family: Introduction and Ordering Information Ordering Information Spartan-3 FPGAs are available in both standard and Pb-free packaging options for all device/package combinations. The Pb-free packages include a special 'G' character in the ordering code. Standard Packaging Example: XC3S50 -4 PQ 208 C Device Type Temperature Range: C = Commercial (TJ = 0C to 85C) I = Industrial (TJ = -40C to 100C) Speed Grade Package Type Number of Pins DS099-1_02a_071304 Pb-Free Packaging For additional information on Pb-free packaging, see XAPP427: "Implementation and Solder Reflow Guidelines for Pb-Free Packages". Example: XC3S50 -4 PQ G 208 C Device Type Speed Grade Package Type Device XC3S50 XC3S200 Speed Grade -4 Standard Performance -5 High Performance1 Temperature Range: C = Commercial (TJ = 0C to 85C) I = Industrial (TJ = -40C to 100C) Number of Pins Pb-free DS099-1_02b_071304 Package Type / Number of Pins VQ(G)100 100-pin Very Thin Quad Flat Pack (VQFP) C Commercial (0C to 85C) CP(G)132 132-pin Chip-Scale Package (CSP) I XC3S400 TQ(G)144 144-pin Thin Quad Flat Pack (TQFP) XC3S1000 PQ(G)208 208-pin Plastic Quad Flat Pack (PQFP) XC3S1500 FT(G)256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA) XC3S2000 FG(G)320 320-ball Fine-Pitch Ball Grid Array (FBGA) XC3S4000 FG(G)456 456-ball Fine-Pitch Ball Grid Array (FBGA) XC3S5000 Temperature Range (TJ ) Industrial (-40C to 100C) FG(G)676 676-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)900 900-ball Fine-Pitch Ball Grid Array (FBGA) FG(G)1156 1156-ball Fine-Pitch Ball Grid Array (FBGA) Notes: 1. The -5 speed grade is exclusively available in the Commercial temperature range. DS099-1 (v1.4) January 17, 2005 Preliminary Product Specification www.xilinx.com 5 R Spartan-3 FPGA Family: Introduction and Ordering Information Revision History Date Version No. Description 04/11/03 1.0 Initial Xilinx release. 04/24/03 1.1 Updated block RAM, DCM, and multiplier counts for the XC3S50. 12/24/03 1.2 Added the FG320 package. 07/13/04 1.3 Added information on Pb-free packaging options. 01/17/05 1.4 Referenced Spartan-3L Low Power FPGA and Spartan-3 XA Automotive FPGA families in Table 1. Added XC3S50CP132, XC3S2000FG456, XC3S4000FG676 options to Table 3. Updated Package Marking to show mask revision code, fabrication facility code, and process technology code. The Spartan-3 Family Data Sheet DS099-1, Spartan-3 FPGA Family: Introduction and Ordering Information (Module 1) DS099-2, Spartan-3 FPGA Family: Functional Description (Module 2) DS099-3, Spartan-3 FPGA Family: DC and Switching Characteristics (Module 3) DS099-4, Spartan-3 FPGA Family: Pinout Descriptions (Module 4) DS313, Spartan-3L Low Power FPGA Family DS314-1, Spartan-3 XA Automotive FPGA Family 6 6 www.xilinx.com DS099-1 (v1.4) January 17, 2005 Preliminary Product Specification