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Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9761
Dual 10-Bit TxDAC+®
with 2 Interpolation Filters
FEATURES
Complete 10-Bit, 40 MSPS Dual Transmit DAC
Excellent Gain and Offset Matching
Differential Nonlinearity Error: 0.5 LSB
Effective Number of Bits: 9.5
Signal-to-Noise and Distortion Ratio: 59 dB
Spurious-Free Dynamic Range: 71 dB
2 Interpolation Filters
20 MSPS/Channel Data Rate
Single Supply: 3 V to 5.5 V
Low Power Dissipation: 93 mW (3 V Supply @
40 MSPS)
On-Chip Reference
28-Lead SSOP
FUNCTIONAL BLOCK DIAGRAM
ACOM
REFLO
I
DAC
FSADJ
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOM DVDD CLOCK
AD9761
2
LATCH
I
REFIO
REFERENCE
COMP1
COMP2
COMP3
BIAS
GENERATOR
QOUTA
QOUTB
2
LATCH
Q
MUX
CONTROL
AVDD
DAC DATA
INPUTS
(10 BITS)
SLEEP
Q
DAC
PRODUCT DESCRIPTION
The AD9761 is a complete dual-channel, high speed, 10-bit
CMOS DAC. The AD9761 has been developed specically for
use in wide bandwidth communication applications (e.g., spread
spectrum) where digital I and Q information is being processed
during transmit operations. It integrates two 10-bit, 40 MSPS
DACs, dual 2 interpolation lters, a voltage reference, and digi-
tal input interface circuitry. The AD9761 supports a 20 MSPS
per channel input data rate that is then interpolated by 2 up to
40 MSPS before simultaneously updating each DAC.
The interleaved I and Q input data stream is presented to the
digital interface circuitry, which consists of I and Q latches as
well as some additional control logic. The data is de-interleaved
back into its original I and Q data. An on-chip state machine
ensures the proper pairing of I and Q data. The data output from
each latch is then processed by a 2 digital interpolation lter
that eases the reconstruction lter requirements. The interpo-
lated output of each lter serves as the input of their respective
10-bit DAC.
The DACs utilize a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and to maximize dynamic accuracy. Each DAC provides
differential current output, thus supporting single-ended or dif-
ferential applications. Both DACs are simultaneously updated
and provide a nominal full-scale current of 10 mA. Also, the
full-scale currents between each DAC are matched to within
0.07 dB (i.e., 0.75%), thus eliminating the need for additional
gain calibration circuitry.
The AD9761 is manufactured on an advanced low cost CMOS
process. It operates from a single supply of 3 V to 5.5 V and
consumes 200 mW of power. To make the AD9761 complete, it
also offers an internal 1.20 V temperature-compensated band gap
reference.
PRODUCT HIGHLIGHTS
1. Dual 10-Bit, 40 MSPS DACs
A pair of high performance 40 MSPS DACs optimized for low
distortion performance provide for exible transmission of I
and Q information.
2. 2 Digital Interpolation Filters
Dual matching FIR interpolation lters with 62.5 dB stop-
band rejection precede each DAC input, thus reducing the
DACs’ reconstruction lter requirements.
3. Low Power
Complete CMOS dual DAC function operates on a low
200 mW on a single supply from 3 V to 5.5 V. The DAC
full-scale current can be reduced for lower power opera-
tion, and a sleep mode is provided for power reduction
during idle periods.
4. On-Chip Voltage Reference
The AD9761 includes a 1.20 V temperature-compensated
band gap voltage reference.
5. Single 10-Bit Digital Input Bus
The AD9761 features a exible digital interface that allows
each DAC to be addressed in a variety of ways including dif-
ferent update rates.
6. Small Package
The AD9761 offers the complete integrated function in a
compact 28-lead SSOP package.
7. Product Family
The AD9761 Dual Transmit DAC has a pair of Dual Receive
ADC companion products, the AD9281 (8 bits) and AD9201
(10 bits).
REV. C
–2–
AD9761–SPECIFICATIONS
AD9761
–3–
DC SPECIFICATIONS
(TMIN to TMax, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA, unless otherwise noted.)
Parameter Min Typ Max Unit
RESOLUTION 10 Bits
DC ACCURACY1
Integral Nonlinearity Error (INL)
TA = 25°C –1.75 ±0.5 +1.75 LSB
TMIN to TMAX –2.75 ±0.7 +2.75 LSB
Differential Nonlinearity (DNL)
TA = 25°C –1 ±0.4 +1.25 LSB
TMIN to TMAX –1 ±0.5 +1.75 LSB
Monotonicity (10-Bit) Guaranteed over Rated Specication Temperature Range
ANALOG OUTPUT
Offset Error –0.05 ±0.025 +0.05 % of FSR
Offset Matching between DACs –0.10 ±0.05 +0.10 % of FSR
Gain Error (without Internal Reference) –5.5 ±1.0 +5.5 % of FSR
Gain Error (with Internal Reference) –5.5 ±1.0 +5.5 % of FSR
Gain Matching between DACs –1.0 ±0.25 +1.0 % of FSR
Full-Scale Output Current2 10 mA
Output Compliance Range –1.0 +1.25 V
Output Resistance 100 k
Output Capacitance 5 pF
REFERENCE OUTPUT
Reference Voltage 1.14 1.20 1.26 V
Reference Output Current3 100 nA
REFERENCE INPUT
Input Compliance Range 0.1 1.25 V
Reference Input Resistance 1 M
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift 0 ppm/°C
Gain Drift (without Internal Reference) ±50 ppm/°C
Gain Drift (with Internal Reference) ±140 ppm/°C
Gain Matching Drift (between DACs) ±25 ppm/°C
Reference Voltage Drift ±50 ppm/°C
POWER SUPPLY
AVDD
Voltage Range 3.0 5.0 5.5 V
Analog Supply Current (IAVDD) 26 29 mA
DVDD
Voltage Range 2.7 5.0 5.5 V
Digital Supply Current at 5 V (IDVDD)4 15 18 mA
Digital Supply Current at 3 V (IDVDD)4 5 mA
Nominal Power Dissipation5
AVDD and DVDD at 3 V 93 mW
AVDD and DVDD at 5 V 200 250 mW
Power Supply Rejection Ratio (PSRR)–AVDD –0.25 +0.25 % of FSR/V
Power Supply Rejection Ratio (PSRR)–DVDD –0.02 +0.02 % of FSR/V
OPERATING RANGE –40 +85 °C
NOTES
1Measured at IOUTA and QOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 16 the IREF current.
3Use an external amplier to drive any external load.
4Measured at fCLOCK = 40 MSPS and fOUT = 1 MHz.
5Measured as unbuffered voltage output into 50 RLOAD at IOUTA, IOUTB, QOUTA, and QOUTB; fCLOCK = 40 MSPS and fOUT = 8 MHz.
Specications subject to change without notice.
REV. C REV. C
–2–
AD9761–SPECIFICATIONS
AD9761
–3–
DYNAMIC SPECIFICATIONS
(TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output,
50 Doubly Terminated, unless otherwise noted.)
DIGITAL SPECIFICATIONS
(TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA unless otherwise noted.)
Parameter Min Typ Max Unit
DYNAMIC PERFORMANCE
Maximum Output Update Rate 40 MSPS
Output Settling Time (tST to 0.025%) 35 ns
Output Propagation Delay (tPD) 55 Input Clock Cycles
Glitch Impulse 5 pV-s
Output Rise Time (10% to 90%) 2.5 ns
Output Fall Time (10% to 90%) 2.5 ns
AC LINEARITY TO NYQUIST
Signal-to-Noise and Distortion (SINAD)
fOUT = 1 MHz; CLOCK = 40 MSPS 56 59 dB
Effective Number of Bits (ENOBs) 9.0 9.5 Bits
Total Harmonic Distortion (THD)
fOUT = 1 MHz; CLOCK = 40 MSPS
TA = 25°C –68 –58 dB
TMIN to TMAX –67 –53 dB
Spurious-Free Dynamic Range (SFDR)
fOUT = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span 59 68 dB
Channel Isolation
fOUT = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span 90 dBc
Specications subject to change without notice.
Parameter Min Typ Max Unit
DIGITAL INPUTS
Logic 1 Voltage @ DVDD = 5 V 3.5 5 V
Logic 1 Voltage @ DVDD = 3 V 2.4 3 V
Logic 0 Voltage @ DVDD = 5 V 0 1.3 V
Logic 0 Voltage @ DVDD = 3 V 0 0.9 V
Logic 1 Current –10 +10 µA
Logic 0 Current –10 +10 µA
Input Capacitance 5 pF
Input Setup Time (tS) 3 ns
Input Hold Time (tH) 2 ns
CLOCK High 5 ns
CLOCK Low 5 ns
Invalid CLOCK/WRITE Window (tCINV)* 1 5 ns
*tCINV is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur.
Specications subject to change without notice.
I DATA Q DATA
tCINV
DB9–DB0
DAC
INPUTS
SELECT
WRITE
CLOCK
tS
tH
NOTE: WRITE AND CLOCK CAN BE
TIED TOGETHER. FOR TYPICAL EXAMPLES,
REFER TO DIGITAL INPUTS AND INTERLEAVED
INTERFACE CONSIDERATION SECTION.
Figure 1. Timing Diagram
REV. C REV. C
AD9761
–4–
AD9761
–5–
DIGITAL FILTER SPECIFICATIONS
(TMIN to TMAX, AVDD = 2.7 V to 5.5 V, DVDD = 2.7 V to 5.5 V, IOUTFS = 10 mA, unless
otherwise noted.)
Parameter Min Typ Max Unit
MAXIMUM INPUT CLOCK RATE (fCLOCK) 40 MSPS
DIGITAL FILTER CHARACTERISTICS
Pass Bandwidth1: 0.005 dB 0.2010 fOUT/fCLOCK
Pass Bandwidth: 0.01 dB 0.2025 fOUT/fCLOCK
Pass Bandwidth: 0.1 dB 0.2105 fOUT/fCLOCK
Pass Bandwidth: –3 dB 0.239 fOUT/fCLOCK
Linear Phase (FIR Implementation)
Stop-Band Rejection: 0.3 fCLOCK to 0.7 fCLOCK –62.5 dB
Group Delay2 32 Input Clock Cycles
Impulse Response Duration3
–40 dB 28 Input Clock Cycles
–60 dB 40 Input Clock Cycles
NOTES
1Excludes SINx/x characteristic of DAC.
2Dened as the number of data clock cycles between impulse input and peak of output response.
355 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update.
Specications subject to change without notice.
FREQUENCY RESPONSE (DC to fCLOCK/2)
OUTPUT (dBFS)
0
–20
–1200 0.50.1 0.2 0.3 0.4
–40
–60
–80
–100
Figure 2a. FIR Filter Frequency Response
TIME (Samples)
1
0
0 405 10 15 20 25 30 35
0.9
0.6
0.4
0.2
0.1
0.8
0.7
0.5
0.3
–0.1
–0.2
–0.3
NORMALIZED OUTPUT
Figure 2b. FIR Filter Impulse Response
Table I. Integer Filter Coefcients for 43-Tap Half-Band
FIR Filter
Lower Coefcient Upper Coefcient Integer Value
H(1) H(43) 1
H(2) H(42) 0
H(3) H(41) –3
H(4) H(40) 0
H(5) H(39) 8
H(6) H(38) 0
H(7) H(37) –16
H(8) H(36) 0
H(9) H(35) 29
H(10) H(34) 0
H(11) H(33) –50
H(12) H(32) 0
H(13) H(31) 81
H(14) H(30) 0
H(15) H(29) –131
H(16) H(28) 0
H(17) H(27) 216
H(18) H(26) 0
H(19) H(25) –400
H(20) H(24) 0
H(21) H(23) 1264
H(22) 1998
REV. C
REV. C
AD9761
–4–
AD9761
–5–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although the AD9761 features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
Package Package
Model Description Option
AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28
AD9761-EB Evaluation Board
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead SSOP
qJA = 109°C/W
COMP1
I
DAC
FSADJ
IOUTA
IOUTB
WRITE
SELECT
COMP2 AVDD AVSS
AD9761
2x
LATCH
I
REFLO
Q
DAC
QOUTA
QOUTB2x
LATCH
Q
MUX
CONTROL
COMP3
DB9–DB0
SLEEPCLOCK
REFIO
100
5020pF
5020pF
DIGITAL
DATA
TEKTRONIX
AWG-2021
CLOCK
OUT MARKER 1
RETIMED
CLOCK
OUTPUT*
LE CROY 9210
PULSE GENERATOR
*AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK.
MINI-CIRCUITS
T1-1T
RSET
2k
0.1F
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50 INPUT
100
5020pF
5020pF
MINI-CIRCUITS
T1-1T
TO HP3589A
SPECTRUM/NETWORK
ANALYZER
50 INPUT
0.1F 0.1F0.1F
DVDD DCOM
2.7V TO
5.5V
3V TO
5.5V
Figure 3. Basic AC Characterization Test Setup
ABSOLUTE MAXIMUM RATINGS*
With
Parameter Respect to Min Max Unit
AVDD ACOM –0.3 +6.5 V
DVDD DCOM –0.3 +6.5 V
ACOM DCOM –0.3 +0.3 V
AVDD DVDD –6.5 +6.5 V
CLOCK, WRITE DCOM –0.3 DVDD + 0.3 V
SELECT, SLEEP DCOM –0.3 DVDD + 0.3 V
Digital Inputs DCOM –0.3 DVDD + 0.3 V
IOUTA, IOUTB ACOM –1.0 AVDD + 0.3 V
QOUTA, QOUTB ACOM –1.0 AVDD + 0.3 V
COMP1, COMP2 ACOM –0.3 AVDD + 0.3 V
COMP3 ACOM –0.3 AVDD + 0.3 V
REFIO, FSADJ ACOM –0.3 AVDD + 0.3 V
REFLO ACOM –0.3 +0.3 V
Junction Temperature 150 °C
Storage Temperature –65 +150 °C
Lead Temperature (10 sec) 300 °C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specication is not implied. Exposure to absolute maximum ratings for extended
periods may affect device reliability.
REV. C
REV. C
AD9761
–6–
AD9761
–7–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 DB9 Most Signicant Data Bit (MSB).
2–9 DB8–DB1 Data Bits 1–8.
10 DB0 Least Signicant Data Bit (LSB).
11 CLOCK Clock Input. Both DACs’ outputs updated on positive edge of clock and digital lters read respective
input registers.
12 WRITE Write Input. DAC input registers latched on positive edge of write.
13 SELECT Select Input. Select high routes input data to I DAC; select low routes data to Q DAC.
14 DVDD Digital Supply Voltage (2.7 V to 5.5 V).
15 DCOM Digital Common.
16 COMP3 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 µF capacitor.
17 QOUTA Q DAC Current Output. Full-scale current when all data bits are 1s.
18 QOUTB Q DAC Complementary Current Output. Full-scale current when all data bits are 0s.
19 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
20 REFIO Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V
reference output when internal reference activated. Requires 0.1 µF capacitor to ACOM when internal
reference activated.
21 FSADJ Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current.
22 COMP2 Bandwidth/Noise Reduction Node. Add 0.1 µF to AVDD for optimum performance.
23 AVDD Analog Supply Voltage (3 V to 5.5 V).
24 ACOM Analog Common.
25 IOUTB I DAC Complementary Current Output. Full-scale current when all data bits are 0s.
26 IOUTA I DAC Current Output. Full-scale current when all data bits are 1s.
27 COMP1 Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 µF capacitor.
28 RESET/SLEEP Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if
asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/
SLEEP Mode Operation section.
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9761
(MSB) DB9
IOUTB
IOUTA
COMP1
RESET/SLEEP
DB8
DB7
DB6
COMP2
AVDD
ACOM
DB5
DB4
DB3
DB2
DB1
(LSB) DB0 REFLO
REFIO
FSADJ
CLOCK
WRITE
SELECT
DVDD
QOUTB
DCOM
COMP3
QOUTA
REV. C
REV. C
AD9761
–6–
AD9761
–7–
DEFINITIONS OF SPECIFICATIONS
Linearity Error
(Also Called Integral Nonlinearity or INL)
Linearity error is dened as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For IOUTA, 0 mA output is expected when
the inputs are all 0s. For IOUTB, 0 mA output is expected when
all inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set to
1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specied as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specied
voltages.
Settling Time
The time required for the output to reach and remain within a
specied error band about its nal value, measured from the start
of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantied by a glitch impulse. It is
specied as the net area of the glitch in pV-s.
Channel Isolation
Channel Isolation is a measure of the level of crosstalk between
channels. It is measured by producing a full-scale 8 MHz signal
output for one channel and measuring the leakage into the other
channel.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specied bandwidth.
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the rst six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio
S/N+D is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/N+D is expressed in decibels.
Effective Number of Bits (ENOB)
For a sine wave, SINAD can be expressed in terms of the number
of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to get a measure of performance expressed as N, the
effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
Pass Band
Frequency band in which any input applied therein
passes unattenuated to the DAC output.
Stop-Band Rejection
The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.
Group Delay
Number of input clocks between an impulse applied at
the device input and peak DAC output current.
Impulse Response
Response of the device to an impulse applied to the input.
REV. C
REV. C
–8–
AD9761—Typical Performance Characteristics
AD9761
–9–
Typical AC Characterization Curves @ 5 V Supplies
(AVDD = 5 V, DVDD = 5 V, 50 Doubly Terminated Load, TA = 25C, fCLOCK = 40 MSPS, unless otherwise noted, worst of I or Q output
performance shown.)
0
–10
–20
–30
–40
–50
–70
–60
–80
–90
START: 0Hz STOP: 40MHz
10dB (Div)
–100
TPC 1. Single-Tone SFDR (DC
to 2 fDATA, fCLOCK = 2 fDATA)
TPC 4. Out-of-Band SFDR vs.
fOUT (fDATA/2 to 3/2 fDATA)
fOUT (MHz)
dB
80
70 SFDR @ 10mA
65
2
75
60
55
0
SINAD @ 10mA
SFDR @ 5mA
SINAD @ 5mA
SFDR @ 2.5mA
SINAD @ 2.5mA
4 6 8 10
TPC 7. SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Differential Output)
fOUT (MHz)
dB
65
60
50
55
0 2.0 10.04.0 6.0 8.0
10.50
9.67
8.01
8.84
ENOB
S/E 0dBFS
DIFF 0dBFS
S/E –6dBFS
DIFF –6dBFS
TPC 2. SINAD (ENOBs) vs.
fOUT (DC to fDATA/2)
AOUT (dBFS)
dB
80
75
60
65
–25 –20 –5
SFDR @ 40MSPS
55
50
–30 –15 –10
SINAD @ 40MSPS
SFDR @ 20MSPS
SINAD @ 20MSPS
SFDR @ 10MSPS
SINAD @ 10MSPS
70
45
40
35
–0
TPC 5. SINAD vs. AOUT (DC to
fDATA/2, Differential Output)
fOUT (MHz)
dB
80
70
SFDR @ 10mA
65
2
75
60
55
0
SINAD @ 10mA
SFDR @ 5mA
SINAD @ 5mA
SFDR @ 2.5mA
SINAD @ 2.5mA
4 6 8 10
TPC 8. SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Single-Ended Output)
fOUT (MHz)
dB
80
75
65
70
0 5.0 10.0
S/E 0dBFS
DIFF 0dBFS
S/E –6dBFS
DIFF –6dBFS
TPC 3. SFDR vs. fOUT (DC to fDATA/2)
AOUT (dBFS)
dB
80
75
60
65
–25 –20 –5
SFDR @ 40MSPS
55
50
–30 –15 –10
SINAD @ 40MSPS
SFDR @ 20MSPS
SINAD @ 20MSPS
SFDR @ 10MSPS
SINAD @ 10MSPS
70
45
40
35
0
TPC 6. SINAD vs. AOUT (DC to
fDATA/2, Single-Ended Output)
–45
–65
–55
–75
–85
START: 0Hz STOP: 20MHz
10dB (Div)
–105
–95
TPC 9. Wideband Spread-
Spectrum Spectral Plot (DC to fDATA)
REV. C
REV. C
–8–
AD9761—Typical Performance Characteristics
AD9761
–9–
Typical AC Characterization Curves @ 3 V Supplies
(AVDD = 3 V, DVDD = 3 V, 50 Doubly Terminated Load, TA = 25C, fCLOCK = 10 MSPS, unless otherwise noted, worst of I or Q output
performance shown.)
0
–10
–20
–30
–40
–50
–70
–60
–80
–90 START: 0Hz STOP: 10MHz
10dB (Div)
TPC 10. Single-Tone SFDR (DC to
2 fDATA, fCLOCK = 2 fDATA)
fOUT (MHz)
dB
75
70
60
65
0 0.5 2.51.0 1.5 2.0
S/E 0dBFS
DIFF 0dBFS
S/E –6dBFS
DIFF –6dBFS
80
TPC 13. Out-of-Band SFDR vs.
fOUT (fDATA/2 to 3/2fDATA)
fOUT (MHz)
dB
80
70
SFDR @ 10mA
65
2
75
60
55
0
SINAD @ 10mA
SFDR @ 5mA
SINAD @ 5mA
SFDR @ 2.5mA
SINAD @ 2.5mA
4 6 8 10
TPC 16. SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Differential Output)
fOUT (MHz)
dB
65
60
50
55
0 0.5 2.51.0 1.5 2.0
10.50
9.67
8.01
8.84
ENOB
S/E 0dBFS
DIFF
0dBFS
S/E –6dBFS
DIFF –6dBFS
TPC 11. SINAD (ENOBs) vs. fOUT
(DC to fDATA/2)
AOUT (dBFS)
dB
75
70
60
65
–30 –25 –5–20 –15 –10
SFDR @ 40MSPS
80 SFDR @ 20MSPS
SFDR @ 10MSPS
SINAD @ 40MSPS
SINAD @ 20MSPS
SINAD @ 10MSPS
55
50
45
40
35
0
TPC 14. SINAD vs. AOUT (DC to
fDATA/2, Differential Output)
SFDR @ 10mA
fOUT (MHz)
dB
80
70
65
2
75
60
550
SINAD @ 10mA
SFDR @ 5mA
SINAD @ 5mA
SFDR @ 2.5mA
SINAD @ 2.5mA
4 6 8 10
TPC 17. SINAD/SFDR vs. IOUTFS
(DC to fDATA/2, Single-Ended Output)
fOUT (MHz)
dB
75
70
60
65
0 0.5 2.51.0 1.5 2.0
S/E 0dBFS
DIFF 0dBFS
S/E –6dBFS
DIFF –6dBFS
80
85
TPC 12. SFDR vs. fOUT (DC to fDATA/2)
AOUT (dBFS)
dB
70
65
55
60
–30 –25 –5–20 –15 –10
SFDR @ 40MSPS
75 SFDR @ 20MSPS
SFDR @ 10MSPS
SINAD @ 20MSPS
SINAD @ 10MSPS
50
45
40
35
30
0
SINAD @ 40MSPS
TPC 15. SINAD vs. AOUT (DC to
fDATA/2, Single-Ended Output)
0
–10
–20
–30
–40
–50
–70
–60
–80
START: 0Hz STOP: 10MHz
10dB (Div)
TPC 18. Narrow-Band Spread-
Spectrum Spectral Plot (DC to fDATA)
REV. C
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AD9761
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AD9761
–11–
FUNCTIONAL DESCRIPTION
Figure 4 shows a simplied block diagram of the AD9761. The
AD9761 is a complete dual-channel, high speed, 10-bit CMOS
DAC capable of operating up to a 40 MHz clock rate. It has
been optimized for the transmit section of wideband communica-
tion systems employing I and Q modulation schemes. Excellent
matching characteristics between channels reduce the need for
any external calibration circuitry. Dual matching 2 interpola-
tion lters included in the I and Q data path simplify any post
band-limiting lter requirements. The AD9761 interfaces with a
single 10-bit digital input bus that supports interleaved I and Q
input data.
ACOM
REFLO
I
DAC
FSADJ
IOUTA
IOUTB
WRITE INPUT
SELECT INPUT
DCOM DVDD CLOCK
AD9761
2
LATCH
I
REFIO
REFERENCE
COMP1
COMP2
COMP3
BIAS
GENERATOR
QOUTA
QOUTB
2
LATCH
Q
MUX
CONTROL
AVDD
DAC DATA
INPUTS
(10 BITS)
SLEEP
Q
DAC
Figure 4. Dual DAC Functional Block Diagram
Referring to Figure 4, the AD9761 consists of an analog sec-
tion and a digital section. The analog section includes matched
I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and
a reference control amplier. The digital section includes two 2
interpolation lters, segment decoding logic, and some additional
digital input interface circuitry. The analog and digital sections of
the AD9761 have separate power supply inputs (i.e., AVDD and
DVDD) that can operate independently. The digital supply can
operate over a 2.7 V to 5.5 V range, allowing it to accommodate
TTL as well as 3.3 V and 5 V CMOS logic families. The analog
supply must be restricted from 3.0 V to 5.5 V to maintain opti-
mum performance.
Each DAC consists of a large PMOS current source array capable
of providing up to 10 mA of full-scale current, IOUTFS. Each array is
divided into 15 equal currents that make up the four most signi-
cant bits (MSBs). The next four bits or middle bits consist of 15
equal current sources whose values are 1/16 of an MSB current
source. The remaining LSBs are binary weighted fractions of
the middle bits’ current sources. All of these current sources are
switched to one of two output nodes (i.e., IOUTA or IOUTB)
via PMOS differential current switches.
The full-scale output current, IOUTFS, of each DAC is regulated
from the same voltage reference and control amplier, thus
ensuring excellent gain matching and drift characteristics
between DACs. IOUTFS can be set from 1 mA to 10 mA via an
external resistor, RSET. The external resistor in combination
with both the reference control amplier and voltage reference,
VREFIO, sets the reference current, IREF, which is mirrored over
to the segmented current sources with the proper scaling factor.
IOUTFS is exactly 16 times the value of IREF.
The I and Q DACs are simultaneously updated on the rising
edge of CLOCK with digital data from their respective 2
digital interpolation lters. The 2 interpolation lters essen-
tially multiply the input data rate of each DAC by a factor of
2, relative to its original input data rate, while simultaneously
reducing the magnitude of the rst image associated with the
DAC’s original input data rate. Since the AD9761 supports a
single 10-bit digital bus with interleaved I and Q input data, the
original I and Q input data rate before interpolation is one-half
the CLOCK rate. After interpolation, the data rate into each I
and Q DAC becomes equal to the CLOCK rate.
The benets of an interpolation lter are illustrated in Figure 5,
which shows an example of the frequency and time domain rep-
resentation of a discrete time sine wave signal before and after
it is applied to a digital interpolation lter. Images of the sine
wave signal appear around multiples of the DAC’s input data
rate as predicted by the sampling theory. These undesirable
images will also appear at the output of a reconstruction DAC,
although modied by the DAC’s sin(x)/(x) response. In many
band-limited applications, these images must be suppressed by
an analog lter following the DAC. The complexity of this ana-
FUNDAMENTAL
1
fCLOCK
FUNDAMENTAL DIGITAL
FILTER
SUPPRESSED
OLD
1ST IMAGE
NEW
1ST IMAGE
fCLOCK
1ST IMAGE
2
fCLOCK
fCLOCK
fCLOCK
2
fCLOCK
DACs SIN(X)
X
TIME DOMAIN
FREQUENCY DOMAIN
2 INTERPOLATION FILTER
INPUT DATA LATCH DAC
fCLOCK
fCLOCK
2
fCLOCK
2
fCLOCK
2
2
Figure 5. Time and Frequency Domain Example of Digital Interpolation Filter
REV. C
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AD9761
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AD9761
–11–
log lter is typically determined by the proximity of the desired
fundamental to the rst image and the required amount of image
suppression.
Referring to Figure 5, the “new” rst image associated with the
DAC’s higher data rate after interpolation is “pushed” out fur-
ther relative to the input signal. The “old” rst image associated
with the lower DAC data rate before interpolation is suppressed
by the digital lter. As a result, the transition band for the analog
reconstruction lter is increased, thus reducing the complexity
of the analog lter.
The digital interpolation lters for I and Q paths are identi-
cal 43-tap half-band symmetric FIR lters. Each lter receives
de-interleaved I or Q data from the digital input interface. The
input CLOCK signal is internally divided by 2 to generate the
lter clock. The lters are implemented with two parallel paths
running at the lter clock rate. The output from each path is
selected on opposite phases of the lter clock, thus producing
interpolated ltered output data at the input clock rate. The
frequency response and impulse response of these lters are
shown in Figures 2a and 2b. Table I lists the idealized lter
coefcients that correspond to the lter’s impulse response.
The digital section of the AD9761 also includes an input interface
section designed to support interleaved I and Q input data from
a single 10-bit bus. This section de-interleaves the I and Q input
data while ensuring its proper pairing for the 2 interpolation
lters. A RESET/SLEEP input serves a dual function by providing
a reset function for this section as well as providing power-down
functionality. Refer to the Digital Inputs and Interleaved Interface
Considerations and RESET/SLEEP Mode Operation sections for
a more detailed discussion.
DAC TRANSFER FUNCTION
Each I and Q DAC provides complementary current output
pins: IOUT(A/B) and QOUT(A/B), respectively. Note that
QOUTA and QOUTB operate identically to IOUTA and
IOUTB. IOUTA will provide a near full-scale current output,
IOUTFS, when all bits are high (i.e., DAC CODE = 1023), while
IOUTB, the complementary output, provides no current. The
current outputs of IOUTA and IOUTB are a function of both
the input code and IOUTFS and can be expressed as
I DAC CODE/ I
OUTA OUTFS
=
( )
×1024
(1)
I – DAC CODE I
OUTB OUTFS
=
( )
×1023 1024/
(2)
where:
DAC CODE = 0 to 1023 (i.e., decimal representation).
As previously mentioned, IOUTFS is a function of the reference
current, IREF, which is nominally set by a reference, VREFIO, and
external resistor, RSET. It can be expressed as
I I
OUTFS REF
= ×16
(3)
where:
I V R
REF REFIO SET
=/
(4)
The two current outputs will typically drive a resistive load
directly or via a transformer. If dc coupling is required, IOUTA
and IOUTB should be directly connected to matching resistive
loads, RLOAD, which are tied to analog common, ACOM. Note
that RLOAD represents the equivalent load resistance seen by
IOUTA or IOUTB. The single-ended voltage output appearing
at IOUTA and IOUTB pins is simply
V I R
IOUTA OUTA LOAD
= ×
(5)
V I R
IOUTB OUTB LOAD
= ×
(6)
Note that the full-scale value of VIOUTA and VIOUTB should not
exceed the specied output compliance range to maintain speci-
ed distortion and linearity performance.
The differential voltage, VIDIFF, appearing across IOUTA and
IOUTB is
V I I R
IDIFF IOUTA IOUTB LOAD
=
( )
×–
(7)
Substituting the values of IIOUTA, IIOUTB, and IREF, VIDIFF can be
expressed as
V DAC CODE –
R R V
IDIFF
LOAD SET REFIO
=
( )
)
{ }
×
( )
×
2 1023 1024
16
/
/
(8)
These last two equations highlight some of the advantages of
operating the AD9761 differentially. First, differential opera-
tion will help cancel common-mode error sources associated
with IIOUTA and IIOUTB, such as noise and distortion. Second,
the differential code-dependent current and subsequent volt-
age, VIDIFF, is twice the value of the single-ended voltage output
(i.e., VIOUTA or VIOUTB), thus providing twice the signal power to
the load.
REFERENCE OPERATION
The AD9761 contains an internal 1.20 V band gap reference that
can be easily disabled and overridden by an external reference.
REFIO serves as either an input or output depending on whether
the internal or an external reference is selected. If REFLO is tied
to ACOM as shown in Figure 6, the internal reference is activated
and REFIO provides a 1.20 V output. In this case, the internal ref-
erence must be ltered externally with a ceramic chip capacitor of
0.1 µF or greater from REFIO to REFLO. Also, REFIO should be
buffered with an external amplier having a low input bias current
(i.e., <1 µA) if any additional loading is required.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO COMP2 AVDD
0.1F
RSET
2k
0.1F
OPTIONAL EXTERNAL
REF BUFFER FOR
ADDITIONAL LOADS
COMPENSATION
CAPACITOR
REQUIREDAD9761
Figure 6. Internal Reference Conguration
The internal reference can also be disabled by connecting
REFLO to AVDD. In this case, an external reference may then
be applied to REFIO as shown in Figure 7. The external reference
may provide either a xed reference voltage to enhance accura-
cy and drift performance or a varying reference voltage for gain
control. Note that the 0.1 µF compensation capacitor is not
required since the internal reference is disabled and the high
input impedance (i.e., 1 M) of REFIO minimizes any loading
of the external reference.
REV. C
REV. C
AD9761
–12–
AD9761
–13–
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO COMP2 AVDD
IREF =
VREF/RSET
AVDD
RSET
EXT.
VREF
AVDD
0.1F
AD9761
+
–
Figure 7. External Reference Conguration
REFERENCE CONTROL AMPLIFIER
The AD9761 also contains an internal control amplier that
is
used to simultaneously regulate both DACs’ full-scale out
put
current, IOUTFS. Since the I and Q IOUTFS are derived
from
the same voltage reference and control circuitry, ex
cellent
gain matching is ensured. The control amplier is congured
as a V-I converter as shown in Figure
7 such that its current
output, IREF, is determined by the ratio of the VREFIO and an
external resistor, RSET, as stated in Equation
4. IREF is cop
ied
over to the segmented current sources with the proper scal
ing
factor to set IOUTFS as stated in Equation
3.
The control amplier allows a wide (10:1) adjustment span
of IOUTFS over a 1 mA to 10 mA range by setting IREF be
tween
62.5 µA and 625 µA. The wide adjustment span of IOUTFS
provides several application benets. The rst benet relates
directly to the power dissipation of the AD9761’s analog
supply, AVDD, which is proportional to IOUTFS (refer to the
Power Dissipation section). The second benet relates
to the
20 dB adjustment span, which may be useful for sys
tem gain
control purposes.
Optimum noise and dynamic performance for the AD9761 is
obtained with a 0.1 µF external capacitor installed be
tween
COMP2 and AVDD. The bandwidth of the reference control
amplier is limited to approximately 5
kHz with a 0.1
µF
capacitor installed. Since the –3
dB bandwidth corresponds
to the dominant pole and therefore its dominant time con-
stant,
the settling time of the control amplier to a stepped
refer
ence
input response can be easily determined. Note
that
the output
of the control amplier, COMP2, is internally
compensated via a 50 pF capacitor, thus ensuring its stabil-
ity if no external capacitor is added.
Depending on the requirements of the application, IREF
can be adjusted by varying either RSET, or, in the external
reference mode, by varying the REFIO voltage. IREF can be
varied for a xed RSET by disabling the internal reference and
varying the voltage of REFIO over its compliance range of
1.25 V to 0.10 V. REFIO can be driven by a single-supply
amplier or DAC, thus allowing IREF to be varied for a xed
RSET. Since the input impedance of REFIO is approximately
1 M, a simple, low cost R-2R ladder DAC congured in
the voltage mode topology may be used to control the gain.
This circuit is shown in Figure 8 using the AD7524 and an
external 1.2 V reference, the AD1580.
ANALOG OUTPUTS
As previously stated, both the I and Q DACs produce two
complementary current outputs
that
may be congured for
single-ended or differential operation. IIOUTA and IIOUTB can be
converted into complementary single-ended voltage outputs,
VIOUTA and VIOUTB, via a load resistor, RLOAD, as described in
the DAC Transfer Function section by Equations 5 through
8. The differential voltage, VIDIFF, existing between VIOUTA
and VIOUTB, can also be converted to a single-ended voltage
via a transformer or differential amplier conguration.
Figure 9 shows an equivalent circuit of the AD9761’s I (or Q)
DAC output. It consists of a parallel array of PMOS current
sources in which each current source is switched to either
IOUTA or IOUTB via a differential PMOS switch. As a re
sult,
the equivalent output impedance of IOUTA and IOUTB
remains quite high (i.e., >100 k and 5 pF).
AD9761
AVDD
RLOAD
RLOAD
IOUTA IOUTB
Figure 9. Equivalent Circuit of the AD9761 DAC Output
IOUTA and IOUTB have a negative and positive voltage
compliance range that must be adhered to achieve optimum
performance. The negative output compliance range of –1
V is
set by the breakdown limits of the CMOS process. Operation
beyond this maximum limit may result in a breakdown of the
output stage.
50pF
CURRENT
SOURCE
ARRAY
+1.2V REF
REFIO
FSADJ
REFLO COMP2 AVDD
AVDD
AD1580
1.2V
OPTIONAL
BAND LIMITING
CAPACITOR
IREF =
VREF/RSET
AVDD
RSET
0.1V TO 1.2V
RFB VDD
OUT1
OUT2
AGND VREF
AD7524
DB7–DB0
+
–
AD9761
Figure 8. Single-Supply Gain Control Circuit
REV. C
REV. C
AD9761
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AD9761
–13–
The positive output compliance range is slightly dependent on
the full-scale output current, IOUTFS. It degrades slightly from
its nominal 1.25 V for an IOUTFS = 10 mA to 1.00 V for an
IOUTFS = 2 mA. Applications requiring the AD9761’s output
(i.e., VOUTA and/or VOUTB) to extend to its output compliance
range should size RLOAD accordingly. Operation beyond this
compliance range will adversely affect the AD9761’s linear
ity
performance and subsequently degrade its distortion per
for-
mance. Note that the optimum distortion performance of
the AD9761 is obtained by restricting its output(s) as seen at
IOUT(A/B) and QOUT(A/B) to within ±0.5 V.
DIGITAL INPUTS AND INTERLEAVED INTERFACE
CONSIDERATIONS
The AD9761 digital interface consists of 10 data input pins,
a clock input pin, and three control pins. It is designed to
support a clock rate up to 40 MSPS. The 10-bit parallel
data inputs follow standard positive binary coding, where
DB9
is the most signicant bit (MSB) and DB0 is the
least sig
nicant
bit (LSB). IOUTA (or QOUTA) produces
a full-scale out
put current when all data bits are at Logic 1.
IOUTB (or QOUTB) produces a complementary output,
with the full-scale current split between the two outputs as a
function of the input code.
STATE
MACHINE
I AND Q DATA
CLOCK
SELECT
RESET/SLEEP
WRITE
Q DATA
CLOCK
2
I DATA
I
INPUT
REGISTER
I
FILTER
REGISTER
Q
INPUT
REGISTER
Q
INPUT
REGISTER
Figure 10. Block Diagram of Digital Interface
The AD9761 interfaces with a single 10-bit digital input
bus that supports interleaved I and Q input data. Figure 10
shows a simplied block diagram of the digital interface
circuitry consisting of two banks of edge triggered registers,
two multiplexers, and a state machine. Interleaved I and Q
input data is presented at the DATA input bus, where it is
then latched into the selected I or Q input register on the
rising edge of the WRITE input. The output of these input
registers is transferred in pairs to their respective interpola-
tor lters’ register after each Q write on the rising edge of
the CLOCK input (refer to Timing Diagram in Figure 1).
A state machine ensures the proper pairing of I and Q in
put
data to the interpolation lter’s inputs.
The SELECT signal at the time of the rising edge of the
WRITE signal determines which input register latches
the input data. If SELECT is high around the rising
edge of WRITE, the data is latched into the I register of
the AD9761. If SELECT is low around the rising edge
of WRITE, the data is latched into the Q register of the
AD9761. If SELECT is kept in one state while data is
repeatedly writing to the AD9761, the data will be written
into the selected lter register at half the input data rate
since the data is always assumed to be interleaved.
The state machine controls the generation of the divided
clock and thus pairing of I and Q data inputs. After the
AD9761 is reset, the state machine keeps track of the paired
I and Q data. The state transition diagram is shown in Fig-
ure 11, in which all states are dened. A transition in state
occurs upon the rising edge of CLOCK and is a function
of the current state as well as status of SELECT, WRITE,
and SLEEP. The state machine is reset on the rst rising
CLOCK edge while RESET remains high. Upon RESET
returning low, a state transition will occur on the rst rising
edge of CLOCK. The most recent I and Q data samples
are transferred to the correct interpolation lter only upon
entering state FILTER DATA.
Note that it is possible to ensure proper pairing of I and Q data
inputs without issuing RESET high. This may be accomplished
by writing two or more successive Q data inputs
followed by
a clock. In this case, the state machine will ad
vance
to either
the RESET or FILTER DATA state. The state
machine
will advance to the ONE-I state upon writing I data followed
by a clock.
ONE, I
RESET
FILTER
DATA
I or Q or N
N
I = WRITE AND SELECT FOLLOWED BY A CLOCK
Q = WRITE AND SELECT FOLLOWED BY A CLOCK
N = CLOCK ONLY, NO WRITE
I
I
Q
Q or N
Figure 11. State Transition Diagram of AD9761
Digital Interface
An example helps illustrate the digital timing and control
requirements to ensure proper pairing of I and Q data.
In
this example, the AD9761 is assumed to interface with
a host
processor on a dedicated data bus and the state machine
is reset by asserting a Logic Level 1 to the RESET/SLEEP
input for a duration of one clock cycle. In the timing dia
gram
shown in Figure 12, WRITE and CLOCK are tied together
while SELECT is updated at the same instance as DATA.
Since SELECT is high upon RESET returning low, I
data is
latched into the I input register on the rst rising WRITE.
On the next rising WRITE edge, the Q data is latched into
its input register and the outputs of both input registers
are
latched into their respective I and Q filter registers. The
sequence of events is repeated on the next rising WRITE
edge
with the new I data being latched into the I input
register.
The digital inputs are CMOS compatible with logic
thresholds,
VTHRESHOLD, set to approximately half the digital positive
supply (DVDD) or VTHRESHOLD = DVDD/2 (±20%).
The internal digital circuitry of the AD9761 is capable of
operating over a digital supply range of 2.7 V to 5.5 V. As a
REV. C
REV. C
AD9761
–14–
AD9761
–15–
result, the digital inputs can also accommodate TTL levels
when DVDD is set to accommodate the maximum high
level voltage, VOH(MAX), of the TTL drivers. A DVDD of 3 V
to 3.3 V will typically ensure proper compatibility of most
TTL logic families. Figure 13 shows the equivalent digital
input circuit for the data, sleep, and clock inputs.
RESET
DATA
SELECT
CLOCK/WRITE
I0Q0I1Q1
Figure 12. Timing Diagram
DVDD
DIGITAL
INPUT
Figure 13. Equivalent Digital Input
Since the AD9761 is capable of being updated up to
40 MSPS,
the quality of the clock and data input signals are important
in achieving the optimum performance. The drivers of the
digital data interface circuitry should be specied to meet
the minimum setup and hold times of the AD9761 as well
as its required min/max input logic level thresholds. The
external clock driver circuitry should provide the AD9761
with a low jitter clock input meeting the min/max logic
levels while providing fast edges. Fast clock edges will help
minimize any jitter that can manifest itself as phase noise
on a reconstructed waveform.
Digital signal paths should be kept short, and run lengths
matched to avoid propagation delay mismatch. The inser-
tion of a low value resistor network (i.e., 20 to 100 )
between the AD9761 digital inputs and driver outputs
may
be helpful in reducing any overshooting and ringing at
the digital inputs, which contributes to data feedthrough.
Operating the AD9761 with reduced logic swings and a
corresponding digital supply (DVDD) will also reduce data
feedthrough.
RESET/SLEEP MODE OPERATION
The RESET/SLEEP input can be used either to power down
the AD9761 or reset its internal digital interface logic. If the
RESET/SLEEP input is asserted for greater than one clock
cycle but under four clock cycles by applying a Logic 1, the
internal state machine will be reset. If the RESET/SLEEP input
is asserted for four clock cycles or longer, the power-down func-
tion of the AD9761 will be initiated. The power-down function
turns off the output current and reduces the supply current to
less than 9 mA over the specied supply range of 3 V to 5.5 V
and temperature range
.
The power-up and power-down characteristics of the
AD9761
are dependent upon the value of the compensation
capacitor connected to COMP1 and COMP3. With a
nominal value of 0.1 µF, the AD9761 takes less than 5 µs to
power down and approximately 3.25 ms to power back up.
POWER DISSIPATION
The power dissipation of the AD9761 is dependent on
several
factors, including
1. AVDD and DVDD, the power supply voltages.
2. IOUTFS, the full-scale current output.
3. fCLOCK, the update rate.
4. The reconstructed digital input waveform.
The power dissipation is directly proportional to the ana
log
supply current, IAVDD, and the digital supply current, IDVDD.
IAVDD is directly proportional to IOUTFS, as shown in Fig-
ure 14, and is insensitive to fCLOCK.
IOUTFS (mA)
30
01 1023456789
25
20
15
10
5
IAVDD (mA)
Figure 14. IAVDD vs. IOUTFS
Conversely, IDVDD is dependent on both the digital input
waveform, fCLOCK, and digital supply, DVDD. Figures 15
and 16 show IDVDD as a function of a full-scale sine wave
output ratio’s (fOUT/fCLOCK) for various update rates with
DVDD = 5 V and DVDD = 3 V, respectively.
5MSPS
RATIO (fOUT/fCLK)
40
30
0.05 0.15
40MSPS
20
0 0.10
20MSPS
10MSPS
10
0
IDVDD (mA)
0.20
50
60
70
2.5MSPS
Figure 15. IDVDD vs. Ratio @ DVDD = 5 V
REV. C
REV. C
AD9761
–14–
AD9761
–15–
5MSPS
RATIO (fOUT/fCLK)
40
30
0.05 0.15
40MSPS
20
0 0.10
20MSPS
10MSPS
10
0
IDVDD (mA)
0.20
2.5MSPS
5
35
25
15
Figure 16. IDVDD vs. Ratio @ DVDD = 3 V
APPLYING THE AD9761
Output Congurations
The following sections illustrate some typical output congu-
rations for the AD9761. Unless otherwise noted, it is assumed
that IOUTFS is set to a nominal 10
mA. For applications requir-
ing the optimum dynamic performance, a differential output
conguration is suggested. A differential output conguration
may consist of either an RF transformer or a differential op amp
conguration. The transformer conguration provides the
optimum high frequency performance and is recommended
for any application allowing for ac coupling. The differential
op amp conguration is suitable for applications requiring dc
coupling, a bipolar output, signal gain, and/or level shifting.
A single-ended output is suitable for applications requiring
a unipolar voltage output. A positive unipolar output volt
age
will result if IOUTA and/or IOUTB is connected to an
appropriately sized load resistor, RLOAD, referred to ACOM.
This conguration may be more suitable for a single-sup
ply
system requiring a dc-coupled, ground referred output volt-
age.
Alternatively, an amplier could be congured as an I-V
converter, thus converting IOUTA or IOUTB into a negative
unipolar voltage. This conguration provides the best dc
linearity since IOUTA or IOUTB is maintained at a virtual
ground.
Differential Coupling Using a Transformer
An RF transformer can be used to perform a differential-
to-single-ended signal conversion as shown in Figure 17.
A
differentially coupled transformer output provides the op
timum
distortion performance for output signals whose spectral
content lies within the transformer’s pass band. An RF
transformer such as the Mini-Circuits T1-1T provides
excellent rejection of common-mode distortion (i.e., even-or
der
harmonics) and noise over a wide frequency range. It also
provides electrical isolation and the ability to deliver twice
the power to the load. Transformers with different imped
ance
ratios may also be used for impedance matching purposes.
Note that the transformer provides ac coupling only.
OPTIONAL
RDIFF
RLOAD
MINI-CIRCUITS
T1-1T
IOUTA
IOUTB
AD9761
Figure 17. Differential Output Using a Transformer
The center tap on the primary side of the transformer must
be connected to ACOM to provide the necessary dc cur
rent
path for both IOUTA and IOUTB. The complementary voltages
appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB)
swing symmetrically around ACOM and should be main
tained
with the specied output compliance range of the AD9761.
A differential resistor, RDIFF, may be inserted in applica
tions
in which the output of the transformer is connected to
the
load, RLOAD, via a passive reconstruction lter or cable
requiring double termination. RDIFF is determined by the
transformer’s impedance ratio and provides the proper
source termination, which results in a low VSWR. Note
that approximately half the signal power will be dissipated
across RDIFF.
Differential Coupling Using an Op Amp
An op amp can also be used to perform a differential
to single-ended conversion as shown in Figure 18. The
AD9761 is congured with two equal load resistors, RLOAD,
of 50 . The differential voltage developed across IOUTA
and IOUTB is converted to a single-ended signal via the
differential op amp conguration. An optional capacitor
can be installed across IOUTA and IOUTB forming a real
pole in a low-pass lter. The addition of this capacitor also
enhances the op amp’s distortion performance by prevent-
ing the DAC’s high slewing output from overloading the op
amp’s input.
COPT 200
500
IOUTA
IOUTB
AD9761
RLOAD
50
200
AD8042
500
RLOAD
50
Figure 18. DC Differential Coupling Using an Op Amp
The common-mode rejection of this conguration is typi
cally
determined by the resistor matching. In this circuit, the
differential op amp circuit using the AD8042 is congured
to provide some additional signal gain. The op amp must
operate from a dual supply since its output is approxi
mately
±1.0 V. A high speed amplier capable of preserving the
differential performance of the AD9761 while meeting
other
system level objectives (i.e., cost, power) should be select
ed.
The op amp’s differential gain, gain setting resistor val
ues,
and full-scale output swing capabilities should all be con
sid-
ered when optimizing this circuit.
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The differential circuit shown in Figure 19 provides the nec
es-
sary level-shifting required in a single-supply system. In this
case, AVDD, which is the positive analog supply for both the
AD9761 and the op amp, is also used to level-shift the differ-
ential output of the AD9761 to midsupply (i.e., AVDD/2)
.
COPT 200
1k
IOUTA
IOUTB
AD9761
RLOAD
50
200
AD8042
500
RLOAD
50
1k
AVDD
Figure 19. Single-Supply DC Differential Coupled
Circuit
Single-Ended Unbuffered Voltage Output
Figure 20 shows the AD9761 congured to provide a uni-
polar output range of approximately 0 V to 0.5 V since the
nominal full-scale current, IOUTFS, of 10 mA ows through an
RLOAD of 50
. In the case of a doubly terminated low-pass
lter, RLOAD represents the equivalent load resistance seen by
IOUTA or IOUTB. The unused output (IOUTA or IOUTB)
can be connected to ACOM directly or via a matching RLOAD.
Different values of IOUTFS and RLOAD can be selected as long
as the positive compliance range is adhered to.
50
IOUTA
IOUTB
AD9761
50
IOUTFS = 10mA VOUT =
0V TO 0.5V
Figure 20. 0 V to 0.5 V Unbuffered Voltage Output
Differential, DC-Coupled Output Conguration with
Level Shifting
Some applications may require the AD9761 differential
outputs
to interface to a single-supply quadrature upconverter.
Although most of these devices provide differential inputs,
its common-mode voltage range does not typically extend
to ground. As a result, the ground-referenced output sig
nals
shown in Figure 20 must be level shifted to within the
specied common-mode range of the single-supply quadra
ture
upconverter. Figure 21 shows the addition of a resistor pull-
up
network that provides the level shifting function. The use
of matched resistor networks will maintain maximum gain
matching and minimum offset performance between the
I and Q channels. Note, the resistor pull-up network will
introduce approximately 6 dB of signal attenuation.
50**
IOUTA
IOUTB
AD9761
50**
500*500*
500*
500*
AVDD
VIN+
VIN–
QUADRATURE
UPCONVERTER
*OHMTEK TO MC-1603-5000D
**OHMTEK TO MC-1603-1000D
Figure 21. Differential, DC-Coupled Output
Conguration with Level-Shifting
POWER AND GROUNDING CONSIDERATIONS
In systems seeking to simultaneously achieve high speed
and
high performance, the implementation and construction of
the printed circuit board design is often as important as the
circuit design. Proper RF techniques must be used in
device
selection, placement and routing, and supply bypass
ing and
grounding. The evaluation board for the AD9761, which
uses a 4-layer PC board, serves as a good example for the
previously mentioned considerations. The evaluation board
provides an illustration of the recommended printed circuit
board ground, power, and signal plane layout.
Proper grounding and decoupling should be a primary objec-
tive in any high speed, high resolution system. The AD9761
features separate analog and digital supply and ground pins
to optimize the management of analog and digital ground
currents in a system. In general, AVDD, the analog supply,
should be decoupled to ACOM, the analog common, as
close to the chip as physically possible. Similarly, DVDD,
the digital supply should be decoupled as close to DCOM as
physically as possible.
For those applications requiring a single 5 V or 3.3 V supply
for both the analog and digital supply, a clean analog sup
ply
may be generated using the circuit shown in Figure 22.
The circuit consists of a differential LC lter with separate
power supply and return lines. Lower noise can be attained
using low ESR type electrolytic and tantalum capacitors.
0.1F
CER.
10F–22F
TANT.
100F
ELECT.
AVDD
ACOM
+ +
– –
FERRITE
BEADS
5V OR 3V POWER
SUPPLY
TTL/CMOS
LOGIC
CIRCUITS
Figure 22. Differential LC Filter for Single 5 V or 3 V
Applications
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Maintaining low noise on power supplies and ground is
critical
to obtaining optimum results from the AD9761. If properly
implemented, ground planes can perform a host of func
tions
on high speed circuit boards such as bypassing, shielding,
current transport. In mixed signal design, the analog and
digital portions of the board should be distinct from each
other,
with the analog ground plane conned to the areas
cover
ing
the analog signal traces and the digital ground plane
con
ned to areas covering the digital interconnects.
All analog ground pins of the DAC, reference, and other
analog components should be tied directly to the analog
ground plane. The two ground planes should be connected
by a path 1/8 to 1/4 inch wide underneath, or within 1/2 inch
of the DAC to maintain optimum performance. Care should
be taken to ensure that the ground plane is uninterrupted
over crucial signal paths. On the digital side, this includes the
digital input lines running to the DAC as well as any clock
signals. On the analog side, this includes the DAC output
signal, reference signal, and the supply feeders.
The use of wide runs or planes in the routing of power lines
is also recommended. This serves the dual role of provid
ing
a low series impedance power supply to the part, as well
as
providing some free capacitive decoupling to the appropri-
ate ground plane. It is essential that care be taken in the
layout of signal and power ground interconnects to avoid
induc
ing extraneous voltage drops in the signal ground
paths. It is recommended that all connections be short, di
rect,
and as physically close to the package as possible in order
to minimize the sharing of conduction paths between dif
fer-
ent currents. When runs exceed an inch in length, strip
line
techniques with a proper termination resistor should be
considered. The necessity and value of this resistor will be
dependent upon the logic family used.
For a more detailed discussion of the implementation and
construction of high speed, mixed signal printed circuit
boards, refer to Analog Devices’ Application Notes AN-280
and AN-333.
APPLICATIONS
Using the AD9761 for QAM Modulation
QAM is one of the most widely used digital modulation
schemes in digital communication systems. This modula
tion
technique can be found in both FDM as well as spread
spectrum (i.e., CDMA) based systems. A QAM signal is a
carrier frequency that is modulated both in amplitude (i.e.,
AM modulation) and in phase (i.e., PM modulation).
It can
be generated by independently modulating two carriers of
identical frequency but with a 90° phase difference. This re
sults
in an in-phase (I) carrier component and a quadrature (Q)
carrier component at a 90° phase shift with
respect to the
I component. The I and Q components are
then summed to
provide a QAM signal at the specied carrier frequency.
A common and traditional implementation of a QAM
modulator is shown in Figure 23. The modulation is per
formed
in the analog domain in which two DACs are used to gen-
erate the baseband I and Q components, respectively. Each
component is then typically applied to a Nyquist lter
before being applied to a quadrature mixer. The matching
Nyquist
lter shapes and limits each component’s spectral
enve
lope while minimizing intersymbol interference. The
DAC is typically updated at the QAM symbol rate or pos
sibly
a multiple of it if an interpolating lter precedes the DAC.
The use of an interpolating lter typically eases the imple-
mentation and complexity of the analog lter, which can be
a signicant contributor to mismatches in gain and phase
between the two baseband channels. A quadrature mixer
modulates the I and Q components with in-phase and
quadrature phase carrier frequency and then sums the two
outputs to provide the QAM signal.
S
0
90
CARRIER
FREQ
NYQUIST
FILTERS
QUADRATURE
MODULATOR
TO
MIXER
IOUT
QOUT
AD9761
10
DSP
OR
ASIC
Figure 23. Typical Analog QAM Architecture
EVALUATION BOARD
The AD9761-EB is an evaluation board for the AD9761
dual 10-bit, 40 MSPS DAC. Careful attention to layout
and circuit design along with prototyping area allows the
user to easily and effectively evaluate the AD9761. This
board allows the user the exibility to operate each of the
AD9761 DACs in a single-ended or differential output
conguration. Each of the DACs’ single-ended outputs are
terminated in a 50 resistor. Evaluation using a transform
er
coupled output can be accomplished simply by installing
a Mini-Circuits transformer (i.e., Model T2-1T) into the
available socket.
The digital inputs are designed to be driven directly from
various word generators with the on-board option to add
a resistor network for proper load termination. Separate
50
terminated SMA connectors are also provided for the
CLOCK, WRITE, and SELECT inputs. Provisions are also
made to operate the AD9761 with either the internal or an
external reference as well as to exercise the power-down
feature.
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Figure 24a. Evaluation Board Schematic
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AD9761
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Figure 24b. Evaluation Board Schematic
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AD9761
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Figure 25. Silkscreen Layer—Top
Figure 26. Component Side PCB Layout (Layer 1)
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Figure 27. Ground Plane PCB Layout (Layer 2)
Figure 28. Power Plane PCB Layout (Layer 3)
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Figure 29. Solder Side PCB Layout (Layer 4)
Figure 30. Silkscreen Layer—Bottom
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OUTLINE DIMENSIONS
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
0.25
0.09
0.95
0.75
0.55
8
4
0
0.05
MIN
1.85
1.75
1.65
2.00 MAX
0.38
0.22 SEATING
PLANE
0.65
BSC
0.10
COPLANARITY
28 15
14
1
10.50
10.20
9.90
5.60
5.30
5.00
8.20
7.80
7.40
COMPLIANT TO JEDEC STANDARDS MO-150AH
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AD9761
Revision History
Location Page
6/03—Data Sheet changed from REV. B to REV. C.
Renumbered TPCs and subsequent gures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal
Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REV. C