Dual 10-Bit TxDAC+ with 2 Interpolation Filters AD9761 (R) FEATURES Complete 10-Bit, 40 MSPS Dual Transmit DAC Excellent Gain and Offset Matching Differential Nonlinearity Error: 0.5 LSB Effective Number of Bits: 9.5 Signal-to-Noise and Distortion Ratio: 59 dB Spurious-Free Dynamic Range: 71 dB 2 Interpolation Filters 20 MSPS/Channel Data Rate Single Supply: 3 V to 5.5 V Low Power Dissipation: 93 mW (3 V Supply @ 40 MSPS) On-Chip Reference 28-Lead SSOP FUNCTIONAL BLOCK DIAGRAM DCOM SLEEP DVDD LATCH I DAC DATA INPUTS (10 BITS) LATCH Q WRITE INPUT SELECT INPUT MUX CONTROL CLOCK 2 ACOM AVDD I DAC IOUTA IOUTB REFERENCE REFLO FSADJ REFIO BIAS GENERATOR COMP1 COMP2 COMP3 2 Q DAC QOUTA QOUTB AD9761 PRODUCT DESCRIPTION The AD9761 is a complete dual-channel, high speed, 10-bit CMOS DAC. The AD9761 has been developed specifically for use in wide bandwidth communication applications (e.g., spread spectrum) where digital I and Q information is being processed during transmit operations. It integrates two 10-bit, 40 MSPS DACs, dual 2 interpolation filters, a voltage reference, and digital input interface circuitry. The AD9761 supports a 20 MSPS per channel input data rate that is then interpolated by 2 up to 40 MSPS before simultaneously updating each DAC. The interleaved I and Q input data stream is presented to the digital interface circuitry, which consists of I and Q latches as well as some additional control logic. The data is de-interleaved back into its original I and Q data. An on-chip state machine ensures the proper pairing of I and Q data. The data output from each latch is then processed by a 2 digital interpolation filter that eases the reconstruction filter requirements. The interpolated output of each filter serves as the input of their respective 10-bit DAC. The DACs utilize a segmented current source architecture combined with a proprietary switching technique to reduce glitch energy and to maximize dynamic accuracy. Each DAC provides differential current output, thus supporting single-ended or differential applications. Both DACs are simultaneously updated and provide a nominal full-scale current of 10 mA. Also, the full-scale currents between each DAC are matched to within 0.07 dB (i.e., 0.75%), thus eliminating the need for additional gain calibration circuitry. The AD9761 is manufactured on an advanced low cost CMOS process. It operates from a single supply of 3 V to 5.5 V and consumes 200 mW of power. To make the AD9761 complete, it also offers an internal 1.20 V temperature-compensated band gap reference. PRODUCT HIGHLIGHTS 1. Dual 10-Bit, 40 MSPS DACs A pair of high performance 40 MSPS DACs optimized for low distortion performance provide for flexible transmission of I and Q information. 2. 2 Digital Interpolation Filters Dual matching FIR interpolation filters with 62.5 dB stopband rejection precede each DAC input, thus reducing the DACs' reconstruction filter requirements. 3. Low Power Complete CMOS dual DAC function operates on a low 200 mW on a single supply from 3 V to 5.5 V. The DAC full-scale current can be reduced for lower power operation, and a sleep mode is provided for power reduction during idle periods. 4. On-Chip Voltage Reference The AD9761 includes a 1.20 V temperature-compensated band gap voltage reference. 5. Single 10-Bit Digital Input Bus The AD9761 features a flexible digital interface that allows each DAC to be addressed in a variety of ways including different update rates. 6. Small Package The AD9761 offers the complete integrated function in a compact 28-lead SSOP package. 7. Product Family The AD9761 Dual Transmit DAC has a pair of Dual Receive ADC companion products, the AD9281 (8 bits) and AD9201 (10 bits). REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2003 Analog Devices, Inc. All rights reserved. AD9761-SPECIFICATIONS DC SPECIFICATIONS (TMIN to TMax, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA, unless otherwise noted.) Parameter Min RESOLUTION Typ Max 10 Unit Bits 1 DC ACCURACY Integral Nonlinearity Error (INL) TA = 25C TMIN to TMAX Differential Nonlinearity (DNL) TA = 25C TMIN to TMAX Monotonicity (10-Bit) ANALOG OUTPUT Offset Error Offset Matching between DACs Gain Error (without Internal Reference) Gain Error (with Internal Reference) Gain Matching between DACs Full-Scale Output Current2 Output Compliance Range Output Resistance Output Capacitance -1.75 -2.75 -0.05 -0.10 -5.5 -5.5 -1.0 -1.0 1.14 REFERENCE INPUT Input Compliance Range Reference Input Resistance 0.1 TEMPERATURE COEFFICIENTS Unipolar Offset Drift Gain Drift (without Internal Reference) Gain Drift (with Internal Reference) Gain Matching Drift (between DACs) Reference Voltage Drift OPERATING RANGE +1.75 +2.75 -1 0.4 +1.25 -1 0.5 +1.75 Guaranteed over Rated Specification Temperature Range REFERENCE OUTPUT Reference Voltage Reference Output Current3 POWER SUPPLY AVDD Voltage Range Analog Supply Current (IAVDD) DVDD Voltage Range Digital Supply Current at 5 V (IDVDD)4 Digital Supply Current at 3 V (IDVDD)4 Nominal Power Dissipation5 AVDD and DVDD at 3 V AVDD and DVDD at 5 V Power Supply Rejection Ratio (PSRR)-AVDD Power Supply Rejection Ratio (PSRR)-DVDD 0.5 0.7 0.025 0.05 1.0 1.0 0.25 10 100 5 1.20 100 1 +0.05 +0.10 +5.5 +5.5 +1.0 +1.25 LSB LSB LSB LSB % of FSR % of FSR % of FSR % of FSR % of FSR mA V k pF 1.26 V nA 1.25 V M 0 50 140 25 50 ppm/C ppm/C ppm/C ppm/C ppm/C 3.0 5.0 26 5.5 29 V mA 2.7 5.0 15 5 5.5 18 V mA mA -0.25 -0.02 -40 93 200 250 +0.25 +0.02 mW mW % of FSR/V % of FSR/V +85 C NOTES 1Measured at IOUTA and QOUTA, driving a virtual ground. 2Nominal full-scale current, I OUTFS, is 16 the IREF current. 3Use an external amplifier to drive any external load. 4Measured at f CLOCK = 40 MSPS and fOUT = 1 MHz. 5Measured as unbuffered voltage output into 50 R LOAD at IOUTA, IOUTB, QOUTA, and QOUTB; fCLOCK = 40 MSPS and fOUT = 8 MHz. Specifications subject to change without notice. -2- REV. C AD9761 DYNAMIC SPECIFICATIONS (TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA, Differential Transformer Coupled Output, 50 Doubly Terminated, unless otherwise noted.) Parameter Min DYNAMIC PERFORMANCE Maximum Output Update Rate Output Settling Time (tST to 0.025%) Output Propagation Delay (tPD) Glitch Impulse Output Rise Time (10% to 90%) Output Fall Time (10% to 90%) 40 AC LINEARITY TO NYQUIST Signal-to-Noise and Distortion (SINAD) fOUT = 1 MHz; CLOCK = 40 MSPS Effective Number of Bits (ENOBs) Total Harmonic Distortion (THD) fOUT = 1 MHz; CLOCK = 40 MSPS TA = 25C TMIN to TMAX Spurious-Free Dynamic Range (SFDR) fOUT = 1 MHz; CLOCK = 40 MSPS; 10 MHz Span Channel Isolation fOUT = 8 MHz; CLOCK = 40 MSPS; 10 MHz Span 56 9.0 Typ Unit 35 55 5 2.5 2.5 MSPS ns Input Clock Cycles pV-s ns ns 59 9.5 dB Bits -68 -67 59 Max -58 -53 dB dB 68 dB 90 dBc Specifications subject to change without notice. DIGITAL SPECIFICATIONS (TMIN to TMAX, AVDD = 5 V, DVDD = 5 V, IOUTFS = 10 mA unless otherwise noted.) Parameter DIGITAL INPUTS Logic 1 Voltage @ DVDD = 5 V Logic 1 Voltage @ DVDD = 3 V Logic 0 Voltage @ DVDD = 5 V Logic 0 Voltage @ DVDD = 3 V Logic 1 Current Logic 0 Current Input Capacitance Input Setup Time (tS) Input Hold Time (tH) CLOCK High CLOCK Low Invalid CLOCK/WRITE Window (tCINV)* Min Typ 3.5 2.4 5 3 0 0 -10 -10 1 5 3 2 5 5 Max 1.3 0.9 +10 +10 5 *tCINV is an invalid window of 4 ns duration beginning 1 ns after the rising edge of WRITE in which the rising edge of CLOCK must not occur. Specifications subject to change without notice. tS DB9-DB0 DAC INPUTS tH I DATA Q DATA SELECT NOTE: WRITE AND CLOCK CAN BE TIED TOGETHER. FOR TYPICAL EXAMPLES, REFER TO DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATION SECTION. WRITE CLOCK tCINV Figure 1. Timing Diagram REV. C -3- Unit V V V V A A pF ns ns ns ns ns AD9761 (TMIN to TMAX, AVDD = 2.7 V to 5.5 V, DVDD = 2.7 V to 5.5 V, IOUTFS = 10 mA, unless otherwise noted.) DIGITAL FILTER SPECIFICATIONS Parameter Min MAXIMUM INPUT CLOCK RATE (fCLOCK) 40 Typ Max Unit MSPS DIGITAL FILTER CHARACTERISTICS Pass Bandwidth1: 0.005 dB Pass Bandwidth: 0.01 dB Pass Bandwidth: 0.1 dB Pass Bandwidth: -3 dB Linear Phase (FIR Implementation) Stop-Band Rejection: 0.3 fCLOCK to 0.7 fCLOCK Group Delay2 Impulse Response Duration3 -40 dB -60 dB 0.2010 0.2025 0.2105 0.239 fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK fOUT/fCLOCK -62.5 32 dB Input Clock Cycles 28 40 Input Clock Cycles Input Clock Cycles NOTES 1Excludes SINx/x characteristic of DAC. 2Defined as the number of data clock cycles between impulse input and peak of output response. 355 input clock periods from input to I DAC, 56 to Q DAC. Propagation delay is delay from data input to DAC update. Specifications subject to change without notice. 0 Table I. Integer Filter Coefficients for 43-Tap Half-Band FIR Filter OUTPUT (dBFS) -20 -40 -60 -80 -100 -120 0 0.1 0.2 0.3 0.4 FREQUENCY RESPONSE (DC to fCLOCK/2) 0.5 Figure 2a. FIR Filter Frequency Response 1 0.9 0.8 NORMALIZED OUTPUT 0.7 0.6 0.5 0.4 0.3 0.2 0.1 Lower Coefficient Upper Coefficient Integer Value H(1) H(2) H(3) H(4) H(5) H(6) H(7) H(8) H(9) H(10) H(11) H(12) H(13) H(14) H(15) H(16) H(17) H(18) H(19) H(20) H(21) H(22) H(43) H(42) H(41) H(40) H(39) H(38) H(37) H(36) H(35) H(34) H(33) H(32) H(31) H(30) H(29) H(28) H(27) H(26) H(25) H(24) H(23) 1 0 -3 0 8 0 -16 0 29 0 -50 0 81 0 -131 0 216 0 -400 0 1264 1998 0 -0.1 -0.2 -0.3 0 5 10 15 20 25 TIME (Samples) 30 35 40 Figure 2b. FIR Filter Impulse Response -4- REV. C AD9761 THERMAL CHARACTERISTICS Thermal Resistance ORDERING GUIDE Package Description Model Package Option 28-Lead SSOP qJA = 109C/W AD9761ARS 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761ARSRL 28-Lead Shrink Small Outline (SSOP) RS-28 AD9761-EB Evaluation Board ABSOLUTE MAXIMUM RATINGS* Parameter AVDD DVDD ACOM AVDD CLOCK, WRITE SELECT, SLEEP Digital Inputs IOUTA, IOUTB QOUTA, QOUTB COMP1, COMP2 COMP3 REFIO, FSADJ REFLO Junction Temperature Storage Temperature Lead Temperature (10 sec) With Respect to Min Max Unit ACOM DCOM DCOM DVDD DCOM DCOM DCOM ACOM ACOM ACOM ACOM ACOM ACOM -0.3 -0.3 -0.3 -6.5 -0.3 -0.3 -0.3 -1.0 -1.0 -0.3 -0.3 -0.3 -0.3 +6.5 +6.5 +0.3 +6.5 DVDD + 0.3 DVDD + 0.3 DVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 AVDD + 0.3 +0.3 150 +150 300 V V V V V V V V V V V V V C C C -65 *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. 3V TO 5.5V 2.7V TO 5.5V 0.1F DVDD DCOM COMP2 LATCH I 0.1F AVDD AVSS COMP1 2x I DAC 0.1F MINI-CIRCUITS T1-1T COMP3 IOUTA TO HP3589A SPECTRUM/NETWORK ANALYZER 50 INPUT 100 IOUTB REFLO TEKTRONIX AWG-2021 DIGITAL DATA LATCH Q SELECT WRITE RETIMED CLOCK OUTPUT* LE CROY 9210 PULSE GENERATOR AD9761 DB9-DB0 CLOCK OUT MARKER 1 CLOCK REFIO 2x FSADJ Q DAC 50 20pF 0.1F RSET 2k MINI-CIRCUITS T1-1T TO HP3589A SPECTRUM/NETWORK ANALYZER 50 INPUT 100 QOUTB MUX CONTROL 50 20pF SLEEP *AWG2021 CLOCK RETIMED SUCH THAT DIGITAL DATA TRANSITIONS ON FALLING EDGE OF 50% DUTY CYCLE CLOCK. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9761 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. -5- 20pF QOUTA Figure 3. Basic AC Characterization Test Setup REV. C 50 50 20pF AD9761 PIN CONFIGURATION 28 RESET/SLEEP (MSB) DB9 1 DB8 2 27 COMP1 DB7 3 26 IOUTA DB6 4 25 IOUTB DB5 5 DB4 6 AD9761 24 ACOM TOP VIEW 23 AVDD DB3 7 (Not to Scale) 22 COMP2 DB2 8 21 FSADJ DB1 9 20 REFIO (LSB) DB0 10 19 REFLO CLOCK 11 18 QOUTB WRITE 12 17 QOUTA SELECT 13 16 COMP3 DVDD 14 15 DCOM PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Description 1 DB9 Most Significant Data Bit (MSB). 2-9 DB8-DB1 Data Bits 1-8. 10 DB0 Least Significant Data Bit (LSB). 11 CLOCK Clock Input. Both DACs' outputs updated on positive edge of clock and digital filters read respective input registers. 12 WRITE Write Input. DAC input registers latched on positive edge of write. 13 SELECT Select Input. Select high routes input data to I DAC; select low routes data to Q DAC. 14 DVDD Digital Supply Voltage (2.7 V to 5.5 V). 15 DCOM Digital Common. 16 COMP3 Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1 F capacitor. 17 QOUTA Q DAC Current Output. Full-scale current when all data bits are 1s. 18 QOUTB Q DAC Complementary Current Output. Full-scale current when all data bits are 0s. 19 REFLO Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference. 20 REFIO Reference Input/Output. Serves as reference input when internal reference disabled. Serves as 1.2 V reference output when internal reference activated. Requires 0.1 F capacitor to ACOM when internal reference activated. 21 FSADJ Full-Scale Current Output Adjust. Resistance to ACOM sets full-scale output current. 22 COMP2 Bandwidth/Noise Reduction Node. Add 0.1 F to AVDD for optimum performance. 23 AVDD Analog Supply Voltage (3 V to 5.5 V). 24 ACOM Analog Common. 25 IOUTB I DAC Complementary Current Output. Full-scale current when all data bits are 0s. 26 IOUTA I DAC Current Output. Full-scale current when all data bits are 1s. 27 COMP1 Internal Bias Node for Switch Driver Circuitry. Decouple to AGND with 0.1 F capacitor. 28 RESET/SLEEP Power-Down Control Input if Asserted for Four Clock Cycles or Longer. Reset control input if asserted for less than four clock cycles. Active high. Connect to DCOM if not used. Refer to RESET/ SLEEP Mode Operation section. -6- REV. C AD9761 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Channel Isolation Channel Isolation is a measure of the level of crosstalk between channels. It is measured by producing a full-scale 8 MHz signal output for one channel and measuring the leakage into the other channel. Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Spurious-Free Dynamic Range The difference, in dB, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Total Harmonic Distortion A D/A converter is monotonic if the output either increases or remains constant as the digital input increases. THD is the ratio of the sum of the rms value of the first six harmonic components to the rms value of the measured output signal. It is expressed as a percentage or in decibels (dB). Offset Error Signal-to-Noise and Distortion (S/N+D, SINAD) Ratio The deviation of the output current from the ideal of zero is called offset error. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. S/N+D is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. Gain Error Effective Number of Bits (ENOB) The difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula, Output Compliance Range it is possible to get a measure of performance expressed as N, the effective number of bits. Monotonicity N = (SINAD - 1.76)/6.02 The range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits may cause either output stage saturation or breakdown, resulting in nonlinear performance. Thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured SINAD. Temperature Drift Pass Band Temperature drift is specified as the maximum change from the ambient (25C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of full-scale range (FSR) per C. For reference drift, the drift is reported in ppm per C. Frequency band in which any input applied therein passes unattenuated to the DAC output. Stop-Band Rejection The amount of attenuation of a frequency outside the pass band applied to the DAC, relative to a full-scale signal applied at the DAC input within the pass band. Power Supply Rejection The maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. Group Delay Number of input clocks between an impulse applied at the device input and peak DAC output current. Settling Time The time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Impulse Response Response of the device to an impulse applied to the input. Glitch Impulse Asymmetrical switching times in a DAC give rise to undesired output transients that are quantified by a glitch impulse. It is specified as the net area of the glitch in pV-s. REV. C -7- AD9761--Typical Performance Characteristics Typical AC Characterization Curves @ 5 V Supplies (AVDD = 5 V, DVDD = 5 V, 50 Doubly Terminated Load, TA = 25C, fCLOCK = 40 MSPS, unless otherwise noted, worst of I or Q output performance shown.) 65 0 10.50 80 9.67 75 -10 -20 DIFF -6dBFS 60 DIFF 0dBFS S/E 0dBFS -60 55 -70 -80 S/E 0dBFS 8.84 DIFF -6dBFS 70 S/E -6dBFS -90 -100 START: 0Hz DIFF 0dBFS 50 STOP: 40MHz 0 2.0 4.0 6.0 fOUT (MHz) 8.0 8.01 10.0 80 75 65 0 80 SFDR @ 40MSPS 60 70 60 55 50 S/E 0dBFS 0 2.0 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS 40 S/E -6dBFS 4.0 6.0 8.0 35 -30 10.0 SFDR @ 10MSPS 60 55 50 45 55 SFDR @ 20MSPS 65 SFDR @ 10MSPS dB dB DIFF 0dBFS dB SFDR @ 20MSPS 65 65 SFDR @ 40MSPS 75 70 DIFF -6dBFS -25 -20 -15 -10 -5 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS 45 40 35 -30 -0 -25 -20 AOUT (dBFS) fOUT (MHz) -5 0 -45 SFDR @ 5mA -55 75 75 -10 TPC 6. SINAD vs. AOUT (DC to fDATA/2, Single-Ended Output) 80 SFDR @ 2.5mA -15 AOUT (dBFS) TPC 5. SINAD vs. AOUT (DC to fDATA/2, Differential Output) TPC 4. Out-of-Band SFDR vs. fOUT (fDATA/2 to 3/2 fDATA) 80 10.0 TPC 3. SFDR vs. fOUT (DC to fDATA/2) 75 70 5.0 fOUT (MHz) TPC 2. SINAD (ENOBs) vs. fOUT (DC to fDATA/2) TPC 1. Single-Tone SFDR (DC to 2 fDATA, fCLOCK = 2 fDATA) 50 S/E -6dBFS dB -50 ENOB -40 dB 10dB (Div) -30 SFDR @ 10mA 70 70 65 0 2 4 6 fOUT (MHz) SFDR @ 2.5mA 65 SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA 60 55 dB dB SFDR @ 5mA TPC 7. SINAD/SFDR vs. IOUTFS (DC to fDATA/2, Differential Output) 55 -75 SINAD @ 2.5mA 60 10 -65 -85 SINAD @ 5mA 8 10dB (Div) SFDR @ 10mA -95 SINAD @ 10mA 0 2 4 6 fOUT (MHz) 8 10 TPC 8. SINAD/SFDR vs. IOUTFS (DC to fDATA/2, Single-Ended Output) -8- -105 START: 0Hz STOP: 20MHz TPC 9. Wideband SpreadSpectrum Spectral Plot (DC to fDATA) REV. C AD9761 Typical AC Characterization Curves @ 3 V Supplies (AVDD = 3 V, DVDD = 3 V, 50 Doubly Terminated Load, TA = 25C, fCLOCK = 10 MSPS, unless otherwise noted, worst of I or Q output performance shown.) 65 0 10.50 85 -10 DIFF -6dBFS DIFF 0dBFS 9.67 75 ENOB S/E 0dBFS -40 -50 DIFF -6dBFS 55 -60 -70 S/E -6dBFS dB 60 -30 80 dB 10dB (Div) -20 70 8.84 DIFF 0dBFS 65 S/E -6dBFS S/E 0dBFS -80 -90 START: 0Hz 50 STOP: 10MHz 0 TPC 10. Single-Tone SFDR (DC to 2 fDATA, fCLOCK = 2 fDATA) 0.5 80 70 dB dB dB S/E -6dBFS 55 50 65 0 0.5 1.0 1.5 fOUT (MHz) 2.0 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS 35 -30 2.5 TPC 13. Out-of-Band SFDR vs. fOUT (fDATA/2 to 3/2fDATA) 75 75 -25 -20 -15 -10 AOUT (dBFS) -5 65 SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA 60 60 -25 -20 -15 -10 AOUT (dBFS) -5 0 0 -10 -20 10dB (Div) SFDR @ 5mA 65 SINAD @ 40MSPS SINAD @ 20MSPS SINAD @ 10MSPS TPC 15. SINAD vs. AOUT (DC to fDATA/2, Single-Ended Output) SFDR @ 5mA 70 dB dB SFDR @ 2.5mA 50 30 -30 0 SFDR @ 10mA 70 SFDR @ 40MSPS 55 35 80 SFDR @ 10mA 2.5 SFDR @ 20MSPS 40 TPC 14. SINAD vs. AOUT (DC to fDATA/2, Differential Output) 80 2.0 SFDR @ 10MSPS 45 45 40 60 1.0 1.5 fOUT (MHz) 60 SFDR @ 40MSPS 60 DIFF 0dBFS 0.5 65 65 70 75 SFDR @ 10MSPS 70 S/E 0dBFS 0 TPC 12. SFDR vs. fOUT (DC to fDATA/2) SFDR @ 20MSPS 75 DIFF -6dBFS 60 8.01 2.5 2.0 TPC 11. SINAD (ENOBs) vs. fOUT (DC to fDATA/2) 80 75 1.0 1.5 fOUT (MHz) SFDR @ 2.5mA SINAD @ 2.5mA SINAD @ 5mA SINAD @ 10mA -30 -40 -50 -60 -70 55 0 2 4 6 fOUT (MHz) 8 10 TPC 16. SINAD/SFDR vs. IOUTFS (DC to fDATA/2, Differential Output) REV. C 55 0 2 4 6 fOUT (MHz) 8 10 TPC 17. SINAD/SFDR vs. IOUTFS (DC to fDATA/2, Single-Ended Output) -9- -80 START: 0Hz STOP: 10MHz TPC 18. Narrow-Band SpreadSpectrum Spectral Plot (DC to fDATA) AD9761 FUNCTIONAL DESCRIPTION Each DAC consists of a large PMOS current source array capable of providing up to 10 mA of full-scale current, IOUTFS. Each array is divided into 15 equal currents that make up the four most significant bits (MSBs). The next four bits or middle bits consist of 15 equal current sources whose values are 1/16 of an MSB current source. The remaining LSBs are binary weighted fractions of the middle bits' current sources. All of these current sources are switched to one of two output nodes (i.e., IOUTA or IOUTB) via PMOS differential current switches. Figure 4 shows a simplified block diagram of the AD9761. The AD9761 is a complete dual-channel, high speed, 10-bit CMOS DAC capable of operating up to a 40 MHz clock rate. It has been optimized for the transmit section of wideband communication systems employing I and Q modulation schemes. Excellent matching characteristics between channels reduce the need for any external calibration circuitry. Dual matching 2 interpolation filters included in the I and Q data path simplify any post band-limiting filter requirements. The AD9761 interfaces with a single 10-bit digital input bus that supports interleaved I and Q input data. DCOM SLEEP DVDD CLOCK LATCH I LATCH Q WRITE INPUT IOUTA IOUTB REFERENCE REFLO FSADJ REFIO BIAS GENERATOR COMP1 COMP2 COMP3 The I and Q DACs are simultaneously updated on the rising edge of CLOCK with digital data from their respective 2 digital interpolation filters. The 2 interpolation filters essentially multiply the input data rate of each DAC by a factor of 2, relative to its original input data rate, while simultaneously reducing the magnitude of the first image associated with the DAC's original input data rate. Since the AD9761 supports a single 10-bit digital bus with interleaved I and Q input data, the original I and Q input data rate before interpolation is one-half the CLOCK rate. After interpolation, the data rate into each I and Q DAC becomes equal to the CLOCK rate. QOUTA Q DAC 2 MUX CONTROL AVDD I DAC 2 DAC DATA INPUTS (10 BITS) SELECT INPUT ACOM The full-scale output current, IOUTFS, of each DAC is regulated from the same voltage reference and control amplifier, thus ensuring excellent gain matching and drift characteristics between DACs. IOUTFS can be set from 1 mA to 10 mA via an external resistor, RSET. The external resistor in combination with both the reference control amplifier and voltage reference, VREFIO, sets the reference current, IREF, which is mirrored over to the segmented current sources with the proper scaling factor. IOUTFS is exactly 16 times the value of IREF. QOUTB AD9761 Figure 4. Dual DAC Functional Block Diagram Referring to Figure 4, the AD9761 consists of an analog section and a digital section. The analog section includes matched I and Q 10-bit DACs, a 1.20 V band gap voltage reference, and a reference control amplifier. The digital section includes two 2 interpolation filters, segment decoding logic, and some additional digital input interface circuitry. The analog and digital sections of the AD9761 have separate power supply inputs (i.e., AVDD and DVDD) that can operate independently. The digital supply can operate over a 2.7 V to 5.5 V range, allowing it to accommodate TTL as well as 3.3 V and 5 V CMOS logic families. The analog supply must be restricted from 3.0 V to 5.5 V to maintain optimum performance. The benefits of an interpolation filter are illustrated in Figure 5, which shows an example of the frequency and time domain representation of a discrete time sine wave signal before and after it is applied to a digital interpolation filter. Images of the sine wave signal appear around multiples of the DAC's input data rate as predicted by the sampling theory. These undesirable images will also appear at the output of a reconstruction DAC, although modified by the DAC's sin(x)/(x) response. In many band-limited applications, these images must be suppressed by an analog filter following the DAC. The complexity of this ana- TIME DOMAIN 2 1 fCLOCK fCLOCK FUNDAMENTAL 1ST FUNDAMENTAL DIGITAL FILTER IMAGE NEW 1ST IMAGE DACs SIN(X) X FREQUENCY DOMAIN fCLOCK fCLOCK 2 INPUT DATA LATCH SUPPRESSED OLD 1ST IMAGE fCLOCK fCLOCK 2 2 INTERPOLATION FILTER 2 fCLOCK fCLOCK fCLOCK 2 DAC fCLOCK 2 Figure 5. Time and Frequency Domain Example of Digital Interpolation Filter -10- REV. C AD9761 log filter is typically determined by the proximity of the desired fundamental to the first image and the required amount of image suppression. Referring to Figure 5, the "new" first image associated with the DAC's higher data rate after interpolation is "pushed" out further relative to the input signal. The "old" first image associated with the lower DAC data rate before interpolation is suppressed by the digital filter. As a result, the transition band for the analog reconstruction filter is increased, thus reducing the complexity of the analog filter. The digital interpolation filters for I and Q paths are identical 43-tap half-band symmetric FIR filters. Each filter receives de-interleaved I or Q data from the digital input interface. The input CLOCK signal is internally divided by 2 to generate the filter clock. The filters are implemented with two parallel paths running at the filter clock rate. The output from each path is selected on opposite phases of the filter clock, thus producing interpolated filtered output data at the input clock rate. The frequency response and impulse response of these filters are shown in Figures 2a and 2b. Table I lists the idealized filter coefficients that correspond to the filter's impulse response. The digital section of the AD9761 also includes an input interface section designed to support interleaved I and Q input data from a single 10-bit bus. This section de-interleaves the I and Q input data while ensuring its proper pairing for the 2 interpolation filters. A RESET/SLEEP input serves a dual function by providing a reset function for this section as well as providing power-down functionality. Refer to the Digital Inputs and Interleaved Interface Considerations and RESET/SLEEP Mode Operation sections for a more detailed discussion. DAC TRANSFER FUNCTION Each I and Q DAC provides complementary current output pins: IOUT(A/B) and QOUT(A/B), respectively. Note that QOUTA and QOUTB operate identically to IOUTA and IOUTB. IOUTA will provide a near full-scale current output, IOUTFS, when all bits are high (i.e., DAC CODE = 1023), while IOUTB, the complementary output, provides no current. The current outputs of IOUTA and IOUTB are a function of both the input code and IOUTFS and can be expressed as IOUTA = (DAC CODE/ 1024) x IOUTFS IOUTB = (1023 - DAC CODE ) /1024 x IOUTFS where: IOUTA or IOUTB. The single-ended voltage output appearing at IOUTA and IOUTB pins is simply VIOUTA = IOUTA x RLOAD (5) VIOUTB = IOUTB x RLOAD (6) Note that the full-scale value of VIOUTA and VIOUTB should not exceed the specified output compliance range to maintain specified distortion and linearity performance. The differential voltage, VIDIFF, appearing across IOUTA and IOUTB is VIDIFF = ( IIOUTA - IIOUTB ) x RLOAD Substituting the values of IIOUTA, IIOUTB, and IREF, VIDIFF can be expressed as VIDIFF = {(2 DAC CODE - 1023) /1024)} x (16 RLOAD /RSET ) x VREFIO REFERENCE OPERATION The AD9761 contains an internal 1.20 V band gap reference that can be easily disabled and overridden by an external reference. REFIO serves as either an input or output depending on whether the internal or an external reference is selected. If REFLO is tied to ACOM as shown in Figure 6, the internal reference is activated and REFIO provides a 1.20 V output. In this case, the internal reference must be filtered externally with a ceramic chip capacitor of 0.1 F or greater from REFIO to REFLO. Also, REFIO should be buffered with an external amplifier having a low input bias current (i.e., <1 A) if any additional loading is required. 0.1F OPTIONAL EXTERNAL REF BUFFER FOR ADDITIONAL LOADS (1) REFIO 0.1F COMPENSATION CAPACITOR REQUIRED As previously mentioned, IOUTFS is a function of the reference current, IREF, which is nominally set by a reference, VREFIO, and external resistor, RSET. It can be expressed as where: IREF = VREFIO /RSET (4) The two current outputs will typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTA and IOUTB should be directly connected to matching resistive loads, RLOAD, which are tied to analog common, ACOM. Note that RLOAD represents the equivalent load resistance seen by REV. C REFLO +1.2V REF (2) (3) (8) These last two equations highlight some of the advantages of operating the AD9761 differentially. First, differential operation will help cancel common-mode error sources associated with IIOUTA and IIOUTB, such as noise and distortion. Second, the differential code-dependent current and subsequent voltage, VIDIFF, is twice the value of the single-ended voltage output (i.e., VIOUTA or VIOUTB), thus providing twice the signal power to the load. DAC CODE = 0 to 1023 (i.e., decimal representation). IOUTFS = 16 x IREF (7) RSET 2k FSADJ COMP2 AVDD 50pF CURRENT SOURCE ARRAY AD9761 Figure 6. Internal Reference Configuration The internal reference can also be disabled by connecting REFLO to AVDD. In this case, an external reference may then be applied to REFIO as shown in Figure 7. The external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. Note that the 0.1 F compensation capacitor is not required since the internal reference is disabled and the high input impedance (i.e., 1 M) of REFIO minimizes any loading of the external reference. -11- AD9761 Depending on the requirements of the application, IREF can be adjusted by varying either RSET, or, in the external reference mode, by varying the REFIO voltage. IREF can be varied for a fixed RSET by disabling the internal reference and varying the voltage of REFIO over its compliance range of 1.25 V to 0.10 V. REFIO can be driven by a single-supply amplifier or DAC, thus allowing IREF to be varied for a fixed RSET. Since the input impedance of REFIO is approximately 1 M, a simple, low cost R-2R ladder DAC configured in the voltage mode topology may be used to control the gain. This circuit is shown in Figure 8 using the AD7524 and an external 1.2 V reference, the AD1580. AVDD 0.1F REFLO COMP2 AVDD +1.2V REF REFIO EXT. VREF RSET IREF = VREF/RSET CURRENT SOURCE ARRAY - FSADJ AVDD 50pF + AD9761 Figure 7. External Reference Configuration ANALOG OUTPUTS As previously stated, both the I and Q DACs produce two complementary current outputs that may be configured for single-ended or differential operation. IIOUTA and IIOUTB can be converted into complementary single-ended voltage outputs, VIOUTA and VIOUTB, via a load resistor, RLOAD, as described in the DAC Transfer Function section by Equations 5 through 8. The differential voltage, VIDIFF, existing between VIOUTA and VIOUTB, can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. REFERENCE CONTROL AMPLIFIER The AD9761 also contains an internal control amplifier that is used to simultaneously regulate both DACs' full-scale output current, IOUTFS. Since the I and Q IOUTFS are derived from the same voltage reference and control circuitry, excellent gain matching is ensured. The control amplifier is configured as a V-I converter as shown in Figure 7 such that its current output, IREF, is determined by the ratio of the VREFIO and an external resistor, RSET, as stated in Equation 4. IREF is copied over to the segmented current sources with the proper scaling factor to set IOUTFS as stated in Equation 3. The control amplifier allows a wide (10:1) adjustment span of IOUTFS over a 1 mA to 10 mA range by setting IREF between 62.5 A and 625 A. The wide adjustment span of IOUTFS provides several application benefits. The first benefit relates directly to the power dissipation of the AD9761's analog supply, AVDD, which is proportional to IOUTFS (refer to the Power Dissipation section). The second benefit relates to the 20 dB adjustment span, which may be useful for system gain control purposes. Optimum noise and dynamic performance for the AD9761 is obtained with a 0.1 F external capacitor installed between COMP2 and AVDD. The bandwidth of the reference control amplifier is limited to approximately 5 kHz with a 0.1 F capacitor installed. Since the -3 dB bandwidth corresponds to the dominant pole and therefore its dominant time constant, the settling time of the control amplifier to a stepped reference input response can be easily determined. Note that the output of the control amplifier, COMP2, is internally compensated via a 50 pF capacitor, thus ensuring its stability if no external capacitor is added. Figure 9 shows an equivalent circuit of the AD9761's I (or Q) DAC output. It consists of a parallel array of PMOS current sources in which each current source is switched to either IOUTA or IOUTB via a differential PMOS switch. As a result, the equivalent output impedance of IOUTA and IOUTB remains quite high (i.e., >100 k and 5 pF). AD9761 AVDD IOUTA IOUTB RLOAD RLOAD Figure 9. Equivalent Circuit of the AD9761 DAC Output IOUTA and IOUTB have a negative and positive voltage compliance range that must be adhered to achieve optimum performance. The negative output compliance range of -1 V is set by the breakdown limits of the CMOS process. Operation beyond this maximum limit may result in a breakdown of the output stage. AVDD OPTIONAL BAND LIMITING CAPACITOR AVDD REFLO 1.2V AD1580 OUT1 RFB VDD AD7524 OUT2 VREF AGND 0.1V TO 1.2V REFIO FSADJ IREF = VREF/RSET AVDD 50pF +1.2V REF RSET DB7-DB0 COMP2 - + CURRENT SOURCE ARRAY AD9761 Figure 8. Single-Supply Gain Control Circuit -12- REV. C AD9761 The positive output compliance range is slightly dependent on the full-scale output current, IOUTFS. It degrades slightly from its nominal 1.25 V for an IOUTFS = 10 mA to 1.00 V for an IOUTFS = 2 mA. Applications requiring the AD9761's output (i.e., VOUTA and/or VOUTB) to extend to its output compliance range should size RLOAD accordingly. Operation beyond this compliance range will adversely affect the AD9761's linearity performance and subsequently degrade its distortion performance. Note that the optimum distortion performance of the AD9761 is obtained by restricting its output(s) as seen at IOUT(A/B) and QOUT(A/B) to within 0.5 V. DIGITAL INPUTS AND INTERLEAVED INTERFACE CONSIDERATIONS The AD9761 digital interface consists of 10 data input pins, a clock input pin, and three control pins. It is designed to support a clock rate up to 40 MSPS. The 10-bit parallel data inputs follow standard positive binary coding, where DB9 is the most significant bit (MSB) and DB0 is the least significant bit (LSB). IOUTA (or QOUTA) produces a full-scale output current when all data bits are at Logic 1. IOUTB (or QOUTB) produces a complementary output, with the full-scale current split between the two outputs as a function of the input code. I AND Q DATA I INPUT REGISTER I FILTER REGISTER the AD9761. If SELECT is low around the rising edge of WRITE, the data is latched into the Q register of the AD9761. If SELECT is kept in one state while data is repeatedly writing to the AD9761, the data will be written into the selected filter register at half the input data rate since the data is always assumed to be interleaved. The state machine controls the generation of the divided clock and thus pairing of I and Q data inputs. After the AD9761 is reset, the state machine keeps track of the paired I and Q data. The state transition diagram is shown in Figure 11, in which all states are defined. A transition in state occurs upon the rising edge of CLOCK and is a function of the current state as well as status of SELECT, WRITE, and SLEEP. The state machine is reset on the first rising CLOCK edge while RESET remains high. Upon RESET returning low, a state transition will occur on the first rising edge of CLOCK. The most recent I and Q data samples are transferred to the correct interpolation filter only upon entering state FILTER DATA. Note that it is possible to ensure proper pairing of I and Q data inputs without issuing RESET high. This may be accomplished by writing two or more successive Q data inputs followed by a clock. In this case, the state machine will advance to either the RESET or FILTER DATA state. The state machine will advance to the ONE-I state upon writing I data followed by a clock. I DATA I or Q or N ONE, I FILTER DATA I Q N I Q INPUT REGISTER Q INPUT REGISTER Q DATA RESET I = WRITE AND SELECT FOLLOWED BY A CLOCK Q = WRITE AND SELECT FOLLOWED BY A CLOCK N = CLOCK ONLY, NO WRITE CLOCK 2 CLOCK SELECT RESET/SLEEP STATE MACHINE Figure 11. State Transition Diagram of AD9761 Digital Interface WRITE Figure 10. Block Diagram of Digital Interface The AD9761 interfaces with a single 10-bit digital input bus that supports interleaved I and Q input data. Figure 10 shows a simplified block diagram of the digital interface circuitry consisting of two banks of edge triggered registers, two multiplexers, and a state machine. Interleaved I and Q input data is presented at the DATA input bus, where it is then latched into the selected I or Q input register on the rising edge of the WRITE input. The output of these input registers is transferred in pairs to their respective interpolator filters' register after each Q write on the rising edge of the CLOCK input (refer to Timing Diagram in Figure 1). A state machine ensures the proper pairing of I and Q input data to the interpolation filter's inputs. The SELECT signal at the time of the rising edge of the WRITE signal determines which input register latches the input data. If SELECT is high around the rising edge of WRITE, the data is latched into the I register of REV. C Q or N An example helps illustrate the digital timing and control requirements to ensure proper pairing of I and Q data. In this example, the AD9761 is assumed to interface with a host processor on a dedicated data bus and the state machine is reset by asserting a Logic Level 1 to the RESET/SLEEP input for a duration of one clock cycle. In the timing diagram shown in Figure 12, WRITE and CLOCK are tied together while SELECT is updated at the same instance as DATA. Since SELECT is high upon RESET returning low, I data is latched into the I input register on the first rising WRITE. On the next rising WRITE edge, the Q data is latched into its input register and the outputs of both input registers are latched into their respective I and Q filter registers. The sequence of events is repeated on the next rising WRITE edge with the new I data being latched into the I input register. The digital inputs are CMOS compatible with logic thresholds, VTHRESHOLD, set to approximately half the digital positive supply (DVDD) or VTHRESHOLD = DVDD/2 (20%). The internal digital circuitry of the AD9761 is capable of operating over a digital supply range of 2.7 V to 5.5 V. As a -13- AD9761 result, the digital inputs can also accommodate TTL levels when DVDD is set to accommodate the maximum high level voltage, VOH(MAX), of the TTL drivers. A DVDD of 3 V to 3.3 V will typically ensure proper compatibility of most TTL logic families. Figure 13 shows the equivalent digital input circuit for the data, sleep, and clock inputs. The power-up and power-down characteristics of the AD9761 are dependent upon the value of the compensation capacitor connected to COMP1 and COMP3. With a nominal value of 0.1 F, the AD9761 takes less than 5 s to power down and approximately 3.25 ms to power back up. POWER DISSIPATION The power dissipation of the AD9761 is dependent on several factors, including RESET I0 DATA Q0 I1 Q1 1. AVDD and DVDD, the power supply voltages. 2. IOUTFS, the full-scale current output. SELECT 3. fCLOCK, the update rate. 4. The reconstructed digital input waveform. CLOCK/WRITE The power dissipation is directly proportional to the analog supply current, IAVDD, and the digital supply current, IDVDD. IAVDD is directly proportional to IOUTFS, as shown in Figure 14, and is insensitive to fCLOCK. Figure 12. Timing Diagram DVDD 30 DIGITAL INPUT 25 IAVDD (mA) 20 Figure 13. Equivalent Digital Input Since the AD9761 is capable of being updated up to 40 MSPS, the quality of the clock and data input signals are important in achieving the optimum performance. The drivers of the digital data interface circuitry should be specified to meet the minimum setup and hold times of the AD9761 as well as its required min/max input logic level thresholds. The external clock driver circuitry should provide the AD9761 with a low jitter clock input meeting the min/max logic levels while providing fast edges. Fast clock edges will help minimize any jitter that can manifest itself as phase noise on a reconstructed waveform. 10 5 0 1 2 3 4 5 6 IOUTFS (mA) 7 8 9 10 Figure 14. IAVDD vs. IOUTFS Conversely, IDVDD is dependent on both the digital input waveform, fCLOCK, and digital supply, DVDD. Figures 15 and 16 show IDVDD as a function of a full-scale sine wave output ratio's (fOUT/fCLOCK) for various update rates with DVDD = 5 V and DVDD = 3 V, respectively. 70 40MSPS 60 50 IDVDD (mA) Digital signal paths should be kept short, and run lengths matched to avoid propagation delay mismatch. The insertion of a low value resistor network (i.e., 20 to 100 ) between the AD9761 digital inputs and driver outputs may be helpful in reducing any overshooting and ringing at the digital inputs, which contributes to data feedthrough. Operating the AD9761 with reduced logic swings and a corresponding digital supply (DVDD) will also reduce data feedthrough. 15 RESET/SLEEP MODE OPERATION The RESET/SLEEP input can be used either to power down the AD9761 or reset its internal digital interface logic. If the RESET/SLEEP input is asserted for greater than one clock cycle but under four clock cycles by applying a Logic 1, the internal state machine will be reset. If the RESET/SLEEP input is asserted for four clock cycles or longer, the power-down function of the AD9761 will be initiated. The power-down function turns off the output current and reduces the supply current to less than 9 mA over the specified supply range of 3 V to 5.5 V and temperature range. 40 20MSPS 30 2.5MSPS 20 10MSPS 5MSPS 10 0 0 0.05 0.10 0.15 0.20 RATIO (fOUT/f CLK) Figure 15. IDVDD vs. Ratio @ DVDD = 5 V -14- REV. C AD9761 40 AD9761 35 IOUTA IDVDD (mA) 30 RLOAD 25 IOUTB OPTIONAL RDIFF 20 20MSPS 15 2.5MSPS 10 Figure 17. Differential Output Using a Transformer 10MSPS 5MSPS 5 0 0 0.05 0.10 0.15 0.20 RATIO (fOUT/f CLK) Figure 16. IDVDD vs. Ratio @ DVDD = 3 V APPLYING THE AD9761 Output Configurations The following sections illustrate some typical output configurations for the AD9761. Unless otherwise noted, it is assumed that IOUTFS is set to a nominal 10 mA. For applications requiring the optimum dynamic performance, a differential output configuration is suggested. A differential output configuration may consist of either an RF transformer or a differential op amp configuration. The transformer configuration provides the optimum high frequency performance and is recommended for any application allowing for ac coupling. The differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain, and/or level shifting. A single-ended output is suitable for applications requiring a unipolar voltage output. A positive unipolar output voltage will result if IOUTA and/or IOUTB is connected to an appropriately sized load resistor, RLOAD, referred to ACOM. This configuration may be more suitable for a single-supply system requiring a dc-coupled, ground referred output voltage. Alternatively, an amplifier could be configured as an I-V converter, thus converting IOUTA or IOUTB into a negative unipolar voltage. This configuration provides the best dc linearity since IOUTA or IOUTB is maintained at a virtual ground. The center tap on the primary side of the transformer must be connected to ACOM to provide the necessary dc current path for both IOUTA and IOUTB. The complementary voltages appearing at IOUTA and IOUTB (i.e., VOUTA and VOUTB) swing symmetrically around ACOM and should be maintained with the specified output compliance range of the AD9761. A differential resistor, RDIFF, may be inserted in applications in which the output of the transformer is connected to the load, RLOAD, via a passive reconstruction filter or cable requiring double termination. RDIFF is determined by the transformer's impedance ratio and provides the proper source termination, which results in a low VSWR. Note that approximately half the signal power will be dissipated across RDIFF. Differential Coupling Using an Op Amp An op amp can also be used to perform a differential to single-ended conversion as shown in Figure 18. The AD9761 is configured with two equal load resistors, RLOAD, of 50 . The differential voltage developed across IOUTA and IOUTB is converted to a single-ended signal via the differential op amp configuration. An optional capacitor can be installed across IOUTA and IOUTB forming a real pole in a low-pass filter. The addition of this capacitor also enhances the op amp's distortion performance by preventing the DAC's high slewing output from overloading the op amp's input. An RF transformer can be used to perform a differentialto-single-ended signal conversion as shown in Figure 17. A differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformer's pass band. An RF transformer such as the Mini-Circuits T1-1T provides excellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. It also provides electrical isolation and the ability to deliver twice the power to the load. Transformers with different impedance ratios may also be used for impedance matching purposes. Note that the transformer provides ac coupling only. 500 AD9761 200 IOUTA AD8042 IOUTB Differential Coupling Using a Transformer REV. C MINI-CIRCUITS T1-1T 40MSPS COPT RLOAD 50 200 RLOAD 50 500 Figure 18. DC Differential Coupling Using an Op Amp The common-mode rejection of this configuration is typically determined by the resistor matching. In this circuit, the differential op amp circuit using the AD8042 is configured to provide some additional signal gain. The op amp must operate from a dual supply since its output is approximately 1.0 V. A high speed amplifier capable of preserving the differential performance of the AD9761 while meeting other system level objectives (i.e., cost, power) should be selected. The op amp's differential gain, gain setting resistor values, and full-scale output swing capabilities should all be considered when optimizing this circuit. -15- AD9761 The differential circuit shown in Figure 19 provides the necessary level-shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both the AD9761 and the op amp, is also used to level-shift the differential output of the AD9761 to midsupply (i.e., AVDD/2). AVDD QUADRATURE UPCONVERTER 500* VIN+ VIN- AD9761 500 AD9761 500* 500* 500* 50** 50** IOUTA 200 IOUTA IOUTB AD8042 IOUTB COPT RLOAD 50 200 RLOAD 50 1k AVDD *OHMTEK TO MC-1603-5000D **OHMTEK TO MC-1603-1000D 1k Figure 21. Differential, DC-Coupled Output Configuration with Level-Shifting Figure 19. Single-Supply DC Differential Coupled Circuit POWER AND GROUNDING CONSIDERATIONS Single-Ended Unbuffered Voltage Output Figure 20 shows the AD9761 configured to provide a unipolar output range of approximately 0 V to 0.5 V since the nominal full-scale current, IOUTFS, of 10 mA flows through an RLOAD of 50 . In the case of a doubly terminated low-pass filter, RLOAD represents the equivalent load resistance seen by IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be connected to ACOM directly or via a matching RLOAD. Different values of IOUTFS and RLOAD can be selected as long as the positive compliance range is adhered to. AD9761 IOUTFS = 10mA IOUTA VOUT = 0V TO 0.5V 50 IOUTB 50 Figure 20. 0 V to 0.5 V Unbuffered Voltage Output Differential, DC-Coupled Output Configuration with Level Shifting Some applications may require the AD9761 differential outputs to interface to a single-supply quadrature upconverter. Although most of these devices provide differential inputs, its common-mode voltage range does not typically extend to ground. As a result, the ground-referenced output signals shown in Figure 20 must be level shifted to within the specified common-mode range of the single-supply quadrature upconverter. Figure 21 shows the addition of a resistor pull-up network that provides the level shifting function. The use of matched resistor networks will maintain maximum gain matching and minimum offset performance between the I and Q channels. Note, the resistor pull-up network will introduce approximately 6 dB of signal attenuation. In systems seeking to simultaneously achieve high speed and high performance, the implementation and construction of the printed circuit board design is often as important as the circuit design. Proper RF techniques must be used in device selection, placement and routing, and supply bypassing and grounding. The evaluation board for the AD9761, which uses a 4-layer PC board, serves as a good example for the previously mentioned considerations. The evaluation board provides an illustration of the recommended printed circuit board ground, power, and signal plane layout. Proper grounding and decoupling should be a primary objective in any high speed, high resolution system. The AD9761 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, AVDD, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, DVDD, the digital supply should be decoupled as close to DCOM as physically as possible. For those applications requiring a single 5 V or 3.3 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 22. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR type electrolytic and tantalum capacitors. AVDD TTL/CMOS LOGIC CIRCUITS FERRITE BEADS + 100F + 10F-22F - ELECT. - TANT. 0.1F CER. ACOM 5V OR 3V POWER SUPPLY Figure 22. Differential LC Filter for Single 5 V or 3 V Applications -16- REV. C AD9761 Maintaining low noise on power supplies and ground is critical to obtaining optimum results from the AD9761. If properly implemented, ground planes can perform a host of functions on high speed circuit boards such as bypassing, shielding, current transport. In mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces and the digital ground plane confined to areas covering the digital interconnects. All analog ground pins of the DAC, reference, and other analog components should be tied directly to the analog ground plane. The two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath, or within 1/2 inch of the DAC to maintain optimum performance. Care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. On the digital side, this includes the digital input lines running to the DAC as well as any clock signals. On the analog side, this includes the DAC output signal, reference signal, and the supply feeders. The use of wide runs or planes in the routing of power lines is also recommended. This serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. It is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous voltage drops in the signal ground paths. It is recommended that all connections be short, direct, and as physically close to the package as possible in order to minimize the sharing of conduction paths between different currents. When runs exceed an inch in length, strip line techniques with a proper termination resistor should be considered. The necessity and value of this resistor will be dependent upon the logic family used. For a more detailed discussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to Analog Devices' Application Notes AN-280 and AN-333. APPLICATIONS Using the AD9761 for QAM Modulation QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in both FDM as well as spread spectrum (i.e., CDMA) based systems. A QAM signal is a carrier frequency that is modulated both in amplitude (i.e., AM modulation) and in phase (i.e., PM modulation). It can be generated by independently modulating two carriers of identical frequency but with a 90 phase difference. This results in an in-phase (I) carrier component and a quadrature (Q) carrier component at a 90 phase shift with respect to the I component. The I and Q components are then summed to provide a QAM signal at the specified carrier frequency. REV. C A common and traditional implementation of a QAM modulator is shown in Figure 23. The modulation is performed in the analog domain in which two DACs are used to generate the baseband I and Q components, respectively. Each component is then typically applied to a Nyquist filter before being applied to a quadrature mixer. The matching Nyquist filter shapes and limits each component's spectral envelope while minimizing intersymbol interference. The DAC is typically updated at the QAM symbol rate or possibly a multiple of it if an interpolating filter precedes the DAC. The use of an interpolating filter typically eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. A quadrature mixer modulates the I and Q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the QAM signal. IOUT DSP OR ASIC 10 AD9761 CARRIER FREQ 0 90 S TO MIXER QOUT NYQUIST FILTERS QUADRATURE MODULATOR Figure 23. Typical Analog QAM Architecture EVALUATION BOARD The AD9761-EB is an evaluation board for the AD9761 dual 10-bit, 40 MSPS DAC. Careful attention to layout and circuit design along with prototyping area allows the user to easily and effectively evaluate the AD9761. This board allows the user the flexibility to operate each of the AD9761 DACs in a single-ended or differential output configuration. Each of the DACs' single-ended outputs are terminated in a 50 resistor. Evaluation using a transformer coupled output can be accomplished simply by installing a Mini-Circuits transformer (i.e., Model T2-1T) into the available socket. The digital inputs are designed to be driven directly from various word generators with the on-board option to add a resistor network for proper load termination. Separate 50 terminated SMA connectors are also provided for the CLOCK, WRITE, and SELECT inputs. Provisions are also made to operate the AD9761 with either the internal or an external reference as well as to exercise the power-down feature. -17- AD9761 Figure 24a. Evaluation Board Schematic -18- REV. C AD9761 Figure 24b. Evaluation Board Schematic REV. C -19- AD9761 Figure 25. Silkscreen Layer--Top Figure 26. Component Side PCB Layout (Layer 1) -20- REV. C AD9761 Figure 27. Ground Plane PCB Layout (Layer 2) Figure 28. Power Plane PCB Layout (Layer 3) REV. C -21- AD9761 Figure 29. Solder Side PCB Layout (Layer 4) Figure 30. Silkscreen Layer--Bottom -22- REV. C AD9761 OUTLINE DIMENSIONS 28-Lead Shrink Small Outline Package [SSOP] (RS-28) Dimensions shown in millimeters 10.50 10.20 9.90 28 15 5.60 5.30 5.00 8.20 7.80 7.40 14 1 1.85 1.75 1.65 2.00 MAX 0.10 COPLANARITY 0.25 0.09 0.05 MIN 0.65 BSC 0.38 0.22 SEATING PLANE 8 4 0 COMPLIANT TO JEDEC STANDARDS MO-150AH REV. C -23- 0.95 0.75 0.55 AD9761 Revision History Location Page 6/03--Data Sheet changed from REV. B to REV. C. Changes to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 -24- REV. C C00615-0-6/03(C) Renumbered TPCs and subsequent figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Universal