MKW36A512VFT4 - NXP SEMICONDUCTORS

MKW36A/35A/34A Data Sheet

An ultra low power, highly integrated Bluetooth® Low

Energy 5.0 wireless microcontroller

Multi-Standard Radio

• 2.4 GHz Bluetooth Low Energy (Bluetooth LE) version

5.0 compliant supporting up to 8 simultaneous

hardware connections

• Generic FSK modulation

• Data Rate: 250, 500 and 1000 kbps

• Modulations: GFSK BT = 0.3, 0.5, and 0.7;

FSK/MSK

• Modulation Index: 0.32, 0.5, 0.7, and 1.0

•

Typical Receiver Sensitivity

(Bluetooth LE 1 Mbps) = –95 dBm

Typical Receiver Sensitivity

(250 kbps GFSK-BT=0.5, h=0.5) = –99 dBm

• Programmable Transmitter Output Power:

–30 dBm to 5 dBm

• Low external component counts for low cost application

• On-chip balun with single ended bidirectional RF port

MCU and Memories

• 256 KB program flash memory plus 256 KB FlexNVM

on KW36A/34A

• 8 KB FlexRAM supporting EEPROM emulation on

KW36A/34A

• 512 KB program flash memory on KW35A

• Up to 48 MHz Arm® Cortex®-M0+ core

• On-chip 64 KB SRAM

System peripherals

• Nine MCU low-power modes to provide power

optimization based on application requirements

• DC-DC Converter supporting Buck and Bypass

operating modes

• Direct memory access (DMA) Controller

• Computer operating properly (COP) watchdog

• Serial wire debug (SWD) Interface and Micro Trace

buffer

• Bit Manipulation Engine (BME)

Analog Modules

• 16-bit Analog-to-Digital Converter (ADC)

• 6-bit High Speed Analog Comparator (CMP)

• 1.2 V voltage reference (VREF)

Timers

• 16-bit low-power timer (LPTMR)

• 3 Timer/PWM Modules(TPM): One 4 channel TPM

and two 2 channel TPMs

• Programmable Interrupt Timer (PIT)

• Real-Time Clock (RTC)

Communication interfaces

• 2 serial peripheral interface (SPI) modules

• 2 inter-integrated circuit (I2C) modules

MKW36A512VHT4

MKW36A512VFP4

MKW36A512VFT4

MKW35A512VFP4

MKW35A512VFT4

MKW34A512VFT4

48 LQFN

7x7 mm Pitch 0.5 mm

48 "Wettable" HVQFN

7x7 mm Pitch 0.5 mm

40 "Wettable" HVQFN

6x6 mm Pitch 0.5 mm

NXP Semiconductors MKW36A512

Data Sheet: Technical Data Rev. 8, 05/2020

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Low Power Consumption

• Transceiver current (DC-DC buck mode, 3.6 V supply)

• Typical Rx Current: 6.3 mA

• Typical Tx current: 5.7 mA (0 dBm output)

• Low Power Mode (VLLS0) Current: 258 nA

Clocks

• 26 and 32 MHz supported for Bluetooth LE and

Generic FSK modes

• 32.768 kHz Crystal Oscillator

Operating Characteristics

• Voltage range: 1.71 V to 3.6 V

• Ambient temperature range: –40 to 105 °C

• AEC Q100 Grade 2 Automotive Qualification

Human-machine interface

• General-purpose input/output

• Low Power UART (LPUART) module with LIN

support (2x LPUART on KW36A)

• Carrier Modulator Timer (CMT)

• FlexCAN module (with CAN FD support up to 3.2

Mbps baudrate) on KW36A

Security

• AES-128 Hardware Accelerator (AESA)

• True Random Number Generator (TRNG)

• Advanced flash security on Program Flash

• 80-bit unique identification number per chip

• 40-bit unique media access control (MAC) sub-

address

• LE Secure Connections

Orderable parts details

Device Top Line

Marking Qualification CAN

2nd UART with

LIN FlexRAM Package

MKW36A512VHT4 (F)M36A Auto Y Y Y 7X7 mm 48-pin LQFN

MKW36A512VFT4 MW36A512V4 Auto Y Y Y 7X7 mm 48-pin "Wettable"

HVQFN

MKW36A512VFP4 M36A9V4 Auto Y Y Y 6X6 mm 40-pin "Wettable"

HVQFN

MKW35A512VFT4 MW35A512V4 Auto N N N 7X7 mm 48-pin "Wettable"

HVQFN

MKW35A512VFP4 M35A9V4 Auto N N N 6X6 mm 40-pin "Wettable"

HVQFN

MKW34A512VFT4 MW34A512V4 Auto N N Y 7X7 mm 48-pin "Wettable"

HVQFN

Related Resources

Type Description Resource

Product

Selector

The Product Selector lets you find the right Kinetis part for your design. W-Series Product Selector

Fact Sheet The Fact Sheet gives overview of the product key features and its uses. KW36-35-34 Fact Sheet

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

MKW36A512RM1

Data Sheet The Data Sheet includes electrical characteristics and signal

connections.

This document.

Chip Errata The chip mask set Errata provides additional or corrective information for

a particular device mask set.

KINETIS_W_1N41U1

Table continues on the next page...

2MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Related Resources (continued)

Type Description Resource

Package

drawing

Package dimensions are provided in package drawings. • 40-pin "Wettable" HVQFN

(6x6): 98ASA01025D1

• 48-pin LQFN (7x7):

98ASA00694D1

• 48-pin "Wettable" HVQFN

(7x7): 98ASA01307D1

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 3

NXP Semiconductors

Table of Contents

1 Introduction........................................................................... 5

2 Feature Descriptions.............................................................6

2.1 Block Diagram............................................................... 6

2.2 Radio features............................................................... 7

2.3 Microcontroller features................................................. 8

2.4 System features.............................................................10

2.5 Peripheral features........................................................ 12

2.6 Security Features...........................................................16

3 Transceiver Description........................................................ 17

3.1 Key Specifications......................................................... 18

3.2 Channel Map Frequency Plans .................................... 18

3.2.1 Channel Plan for Bluetooth Low Energy............18

3.2.2 Other Channel Plans ........................................ 20

3.3 Transceiver Functions................................................... 20

4 Transceiver Electrical Characteristics...................................20

4.1 Radio operating conditions............................................ 21

4.2 Receiver Feature Summary...........................................21

4.3 Transmit and PLL Feature Summary.............................23

5 System and Power Management..........................................28

5.1 Power Management.......................................................28

5.1.1 DC-DC Converter.............................................. 28

5.2 Modes of Operation....................................................... 29

5.2.1 Power modes.....................................................29

6 KW36A/35A/34A Electrical Characteristics...........................31

6.1 AC electrical characteristics...........................................31

6.2 Nonswitching electrical specifications............................32

6.2.1 Voltage and current operating requirements..... 32

6.2.2 LVD and POR operating requirements..............33

6.2.3 Voltage and current operating behaviors...........34

6.2.4 Power mode transition operating behaviors...... 35

6.2.5 Power consumption operating behaviors.......... 35

6.2.6 Diagram: Typical IDD_RUN operating behavior41

6.2.7 SoC Power Consumption.................................. 43

6.2.8 Designing with radiated emissions in mind........44

6.2.9 Capacitance attributes.......................................44

6.3 Switching electrical specifications..................................45

6.3.1 Device clock specifications................................45

6.3.2 General switching specifications....................... 45

6.4 Thermal specifications...................................................46

6.4.1 Thermal operating requirements....................... 46

6.4.2 Thermal attributes..............................................47

6.5 Peripheral operating requirements and behaviors.........47

6.5.1 Core modules.................................................... 47

6.5.2 System modules................................................ 48

6.5.3 Clock modules................................................... 49

6.5.4 Memories and memory interfaces..................... 53

6.5.5 Security and integrity modules.......................... 55

6.5.6 Analog............................................................... 56

6.5.7 Timers................................................................63

6.5.8 Communication interfaces................................. 63

6.5.9 Human-machine interfaces (HMI)......................68

6.6 DC-DC Converter Operating Requirements.................. 68

6.7 Ratings...........................................................................71

6.7.1 Thermal handling ratings................................... 71

6.7.2 Moisture handling ratings.................................. 71

6.7.3 ESD handling ratings.........................................71

6.7.4 Voltage and current operating ratings............... 72

7 Pin Diagrams and Pin Assignments......................................72

7.1 KW36A Signal Multiplexing and Pin Assignments.........72

7.2 KW36A Pinouts..............................................................75

7.3 KW35A Signal Multiplexing and Pin Assignments.........78

7.4 KW35A Pinouts..............................................................81

7.5 KW34A Signal Multiplexing and Pin Assignments.........83

7.6 KW34A Pinouts..............................................................86

7.7 Module Signal Description Tables................................. 87

7.7.1 Core Modules.................................................... 87

7.7.2 Radio Modules...................................................88

7.7.3 System Modules................................................ 89

7.7.4 Clock Modules................................................... 90

7.7.5 Analog Modules.................................................90

7.7.6 Timer Modules...................................................91

7.7.7 Communication Interfaces.................................92

7.7.8 Human-Machine Interfaces(HMI)...................... 93

8 Package Information............................................................. 94

8.1 Obtaining package dimensions......................................94

9 Part identification...................................................................94

9.1 Description.....................................................................94

9.2 Format........................................................................... 95

9.3 Fields............................................................................. 95

9.4 Example.........................................................................95

10 Revision History.................................................................... 96

4MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

1 Introduction

The KW36A/35A/34A wireless microcontrollers (MCU), which includes the KW36A,

KW35A, and KW34A families of devices, are highly integrated single-chip devices

that enable Bluetooth Low Energy (Bluetooth LE) and Generic FSK connectivity for

automotive embedded systems. To meet the stringent requirements of automotive

applications, the KW36A/35A/34A is fully AEC Q100 Grade 2 Automotive

Qualified. The target applications center on wirelessly bridging the embedded world

with mobile devices to enhance the human interface experience, share embedded data

between devices and the cloud and enable wireless firmware updates. Leading the

automotive applications is the Digital Key, where a smartphone can be used by the

owner as an alternative to the key FOB for unlocking and personalizing the driving

experience. For a car sharing experience, the owner can provide selective, temporary

authorization for access to the car allowing the authorized person to unlock, start and

operate the car using their mobile device using Bluetooth LE.

The KW36A/35A/34A Wireless MCU integrates an Arm® Cortex®-M0+ CPU with

up to 512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE

5.0 and Generic FSK modulations. The Bluetooth LE radio supports up to 8

simultaneous connections in any master/slave combination. The Medical Body Area

Network (MBAN) frequencies from 2.36 to 2.4 GHz are also supported enabling

wearable or implantable wireless medical devices.

The KW36A includes an integrated FlexCAN module enabling seamless integration

into a cars in-vehicle CAN communication network. The FlexCAN module can

support CAN’s flexible data-rate (CAN FD) protocol for increased bandwidth and

lower latency required by many automotive applications.

The KW36A/35A/34A devices can be used as a "BlackBox" modem in order to add

Bluetooth LE or Generic FSK connectivity to an existing host MCU or MPU

(microprocessor), or may be used as a standalone smart wireless sensor with

embedded application where no host controller is required.

The RF circuit of the KW36A/35A/34A is optimized to require very few external

components, achieving the smallest RF footprint possible on a printed circuit board.

Extremely long battery life is achieved through the efficiency of code execution in the

Cortex-M0+ CPU core and the multiple low power operating modes of the

KW36A/35A/34A. For power critical applications, an integrated DC-DC converter

enables operation from a single coin cell or Li-ion battery with a significant reduction

of peak receive and transmit current consumption.

Introduction

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 5

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2 Feature Descriptions

This section provides a simplified block diagram and highlights the KW36A/35A/34A

features.

2.1 Block Diagram

DCDC

VDCDC_IN

Crossbar-Lite Switch (AXBS)

SRAM

Flash

Arm Cortex M0+ Core

NVIC WIC

IOPORT

DAP

MTB

GPIO BME

Flash AIPS-Lite

MDM

DWT

RTC

LPTMR

PIT

SIM

RCM

PMC

SMC LPUART x2

ADC

Unified Bus

Serial Wire Debug

IPS

AHBLite

Controller

IPS

256 KB

FlexNVM

32K Osc

MCG

FLL IRC

32 kHz

IRC

4 MHz

DMA MUX

4ch DMA

AHBLite

CMP

FlexCAN

TPM x3

32M Osc

VREF

I2C x2

CMT

256 KB

64 KByte

TRNG

APB

SPI x2

M2A

Radio

LTC(AESA)

8 KB

FlexRAM

Figure 1. KW36 Detailed Block Diagram

Feature Descriptions

6MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

DCDC

VDCDC_IN

Crossbar-Lite Switch (AXBS)

SRAM

Flash

Arm Cortex M0+ Core

NVIC WIC

IOPORT

DAP

MTB

GPIO BME

Flash AIPS-Lite

MDM

DWT

RTC

LPTMR

PIT

SIM

RCM

PMC

SMC LPUART

ADC

Unified Bus

Serial Wire Debug

IPS

AHBLite

Controller

IPS

Prg Acc RAM

8 KB

32K Osc

MCG

FLL IRC

32 kHz

IRC

4 MHz

DMA MUX

4ch DMA

AHBLite

CMP TPM x3

32M Osc

VREF

I2C x2

CMT

512 KB

64 KByte

TRNG

APB

SPI x2

M2A

Radio

LTC(AESA)

Figure 2. KW35 Detailed Block Diagram

DCDC

VDCDC_IN

Crossbar-Lite Switch (AXBS)

SRAM

Flash

Arm Cortex M0+ Core

NVIC WIC

IOPORT

DAP

MTB

GPIO BME

Flash AIPS-Lite

MDM

DWT

RTC

LPTMR

PIT

SIM

RCM

PMC

SMC LPUART

ADC

Unified Bus

Serial Wire Debug

IPS

AHBLite

Controller

IPS

FlexNVM

256 KB

FlexRAM

8 KB

32K Osc

MCG

FLL IRC

32 kHz

IRC

4 MHz

DMA MUX

4ch DMA

AHBLite

CMP TPM x3

32M Osc

VREF

I2C x2

CMT

256 KB

64 KByte

TRNG

APB

SPI x2

M2A

Radio

LTC(AESA)

Figure 3. KW34 Detailed Block Diagram

2.2 Radio features

Operating frequencies:

• 2.4 GHz ISM band (2400-2483.5 MHz)

• Medical Body Area Network (MBAN) 2360-2400 MHz

Supported standards:

Feature Descriptions

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 7

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• Bluetooth Low Energy Version 5.0 compliant radio

• Generic FSK modulation supporting data rates up to 1 Mbit/s

• Support for up to 8 simultaneous Bluetooth LE hardware connections in any

master, slave combination

• Bluetooth LE Application Profiles

Receiver performance:

• Receive sensitivity of up to –95 dBm for Bluetooth LE

• Receive sensitivity of up to –99 dBm for a 250 kbit/s GFSK mode with a

modulation index of 0.5. Receive sensitivity in Generic FSK modes depends on

mode selection and data rate.

Other features:

• Programmable transmit output power from –30 dBm to +5 dBm

• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK modes

• Bluetooth Low Energy version 5.0 Link Layer hardware with 1 Mbit/s PHY

support

• Hardware acceleration for Generic FSK packet processing

• Generic FSK modulation at 250, 500 and 1000 kbit/s

• Supports 8 simultaneous Bluetooth LE connections in any master/slave

combination

• Enhanced Bluetooth LE automatic deep sleep modes (DSM) supporting Slave

Latency

• Up to 26 devices supported by whitelist in hardware

• Up to 8 private resolvable addresses supported in hardware

• Supports DMA capture of IQ data with sampling rate of up to 2 MHz, when using a

32 MHz crystal

• Integrated on-chip balun

• Single ended bidirectional RF port shared by transmit and receive

• Low external component count

• Supports transceiver range extension using external PA and/or LNA

2.3 Microcontroller features

Arm Cortex-M0+ CPU

• Up to 48 MHz CPU

Feature Descriptions

8MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline

microarchitecture for reduced power consumption and improved architectural

performance (cycles per instruction)

• Supports up to 32 interrupt request sources

• Binary compatible instruction set architecture with the Cortex-M0 core

• Thumb instruction set combines high code density with 32-bit performance

• Serial Wire Debug (SWD) reduces the number of pins required for debugging

• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using

system RAM as the destination memory

Nested Vectored Interrupt Controller (NVIC)

• 32 vectored interrupts, 4 programmable priority levels

• Includes a single non-maskable interrupt

Wake-up Interrupt Controller (WIC)

• Supports interrupt handling when system clocking is disabled in low-power

modes

• Takes over and emulates the NVIC behavior when correctly primed by the NVIC

on entry to very-deep-sleep

• A rudimentary interrupt masking system with no prioritization logic signals for

wake-up as soon as a non-masked interrupt is detected

Debug Controller

• Two-wire Serial Wire Debug (SWD) interface

• Hardware breakpoint unit for 2 code addresses

• Hardware watchpoint unit for 2 data items

• Micro Trace Buffer for program tracing

On-Chip Memory

• Up to 512 KB Flash

• KW36A/34A contains 256 KB program flash with ECC and 256 KB

FlexNVM.

• KW35A contains 512 KB program flash with ECC.

• Flash implemented as two equal blocks each of 256 KB block. Code can

execute or read from one block while the other block is being erased or

programmed on KW35A only.

• Firmware distribution protection. Program flash can be marked execute-only

on a per-sector (8 KB) basis to prevent firmware contents from being read by

third parties.

Feature Descriptions

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 9

NXP Semiconductors

• 64 KB SRAM

• KW36A/34A contains 8 KB FlexRAM.

• KW35A contains 8 KB program acceleration RAM.

• Security circuitry to prevent unauthorized access to RAM and flash contents

through the debugger

2.4 System features

Power Management Control Unit (PMC)

• Programmable power saving modes

• Available wake-up from power saving modes via internal and external sources

• Integrated Power-on Reset (POR)

• Integrated Low Voltage Detect (LVD) with reset (brownout) capability

• Selectable LVD trip points

• Programmable Low Voltage Warning (LVW) interrupt capability

• Individual peripheral clocks can be gated off to reduce current consumption

• Internal Buffered bandgap reference voltage

• Factory programmed trim for bandgap and LVD

• 1 kHz Low-power Oscillator (LPO)

DC-DC Converters

• Internal switched mode power supply supporting Buck and Bypass operating

modes

• Buck operation supports external voltage sources of 2.1 V to 3.6 V

• When DC-DC is not used, the device supports an external voltage range of 1.5 V to

3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_RF3 and

VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1, and VDDA pins)

• An external inductor is required to support the Buck mode

Direct Memory Access (DMA) Controller

• All data movement via dual-address transfers: read from source, write to

destination

• Programmable source and destination addresses and transfer size

• Support for enhanced addressing modes

• 4-channel implementation that performs complex data transfers with minimal

intervention from a host processor

• Internal data buffer, used as temporary storage to support 16- and 32-byte transfers

• Connections to the crossbar switch for bus mastering the data movement

Feature Descriptions

10 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

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• Transfer Control Descriptor (TCD) organized to support two-deep, nested transfer

operations

• 32-byte TCD stored in local memory for each channel

• An inner data transfer loop defined by a minor byte transfer count

• An outer data transfer loop defined by a major iteration count

• Channel activation via one of three methods:

• Explicit software initiation

• Initiation via a channel-to-channel linking mechanism for continuous

transfers

• Peripheral-paced hardware requests, one per channel

• Fixed-priority and round-robin channel arbitration

• Channel completion reported via optional interrupt requests

• One interrupt per channel, optionally asserted at completion of major iteration

count

• Optional error terminations per channel and logically summed together to form

one error interrupt to the interrupt controller

• Optional support for scatter/gather DMA processing

• Support for complex data structures

DMA Channel Multiplexer (DMA MUX)

• 4 independently selectable DMA channel routers

• 2 periodic trigger sources available

• Each channel router can be assigned to 1 of the peripheral DMA sources

COP Watchdog Module

• Independent clock source input (independent from CPU/bus clock)

• Choice between two clock sources

• LPO oscillator

• Bus clock

System Clocks

• Both 26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE

and Generic FSK modes

• MCU can derive its clock either from the crystal reference oscillator or the

Frequency-locked Loop (FLL)1

• 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth Low

Energy timing in low-power modes

• Multipurpose Clock Generator (MCG)

1. Clock options can have restrictions based on the chosen SoC configuration.

Feature Descriptions

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 11

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• Internal reference clocks — Can be used as a clock source for other on-chip

peripherals

• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy

across full temperature range

• On-chip 4 MHz oscillator with 5% accuracy across full temperature range

• Frequency-locked Loop (FLL) controlled by internal or external reference

• 20 MHz to 48 MHz FLL output

Unique Identifiers

• 80-bit Unique ID represents a unique identifier for each chip

• 40-bit unique Media Access Control (MAC) address, which can be used to build a

unique 48-bit Bluetooth Low Energy MAC address

2.5 Peripheral features

16-bit Analog-to-Digital Converter (ADC)

• Linear successive approximation algorithm with 16-bit resolution

• Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode

• Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode

• Single or continuous conversion

• Configurable sample time and conversion speed/power

• Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec

• Input clock selection

• Operation in low-power modes for lower noise operation

• Asynchronous clock source for lower noise operation

• Selectable asynchronous hardware conversion trigger

• Automatic compare with interrupt for less-than, or greater than, or equal to

programmable value

• Temperature sensor

• Battery voltage measurement

• Hardware average function

• Selectable voltage reverence

• Self-calibration mode

High-Speed Analog Comparator (CMP)

• 6-bit DAC programmable reference generator output

• Up to eight selectable comparator inputs; each input can be compared with any

input by any polarity sequence

Feature Descriptions

12 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

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• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of

comparator output

• Two performance modes:

• Shorter propagation delay at the expense of higher power

• Low-power, with longer propagation delay

• Operational in all MCU power modes except VLLS0 mode

Voltage Reference(VREF1)

• Programmable trim register with 0.5 mV steps, automatically loaded with factory

trimmed value upon reset

• Programmable buffer mode selection:

• Off

• Bandgap enabled/standby (output buffer disabled)

• High-power buffer mode (output buffer enabled)

• 1.2 V output at room temperature

• VREF_OUT output signal

Low-power Timer (LPTMR)

• One channel

• Operation as timer or pulse counter

• Selectable clock for prescaler/glitch filter

• 1 kHz internal LPO

• External low-power crystal oscillator

• Internal reference clock

• Configurable glitch filter or prescaler

• Interrupt generated on timer compare

• Hardware trigger generated on timer compare

• Functional in all power modes

Timer/PWM (TPM)

• TPM0: 4 channels, TPM1 and TPM2: 2 channels each

• Selectable source clock

• Programmable prescaler

• 16-bit counter supporting free-running or initial/final value, and counting is up or

up-down

• Input capture, output compare, and edge-aligned and center-aligned PWM modes

• Input capture and output compare modes

• Generation of hardware triggers

• TPM1 and TPM2: Quadrature decoder with input filters

• Global time base mode shares single time base across multiple TPM instances

Feature Descriptions

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Programmable Interrupt Timer (PIT)

• Up to 2 interrupt timers for triggering ADC conversions

• 32-bit counter resolution

• Clocked by bus clock frequency

Real-Time Clock (RTC)

• 32-bit seconds counter with 32-bit alarm

• Can be invalidated on detection of tamper detect

• 16-bit prescaler with compensation

• Register write protection

• Hard Lock requires MCU POR to enable write access

• Soft lock requires POR or software reset to enable write/read access

• Capable of waking up the system from low-power modes

Inter-Integrated Circuit (I2C)

• Two channels

• Compatible with I2C bus standard and SMBus Specification Version 2 features

• Up to 400 kHz operation

• Multi-master operation

• Software programmable for one of 64 different serial clock frequencies

• Programmable slave address and glitch input filter

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• Bus busy detection broadcast and 10-bit address extension

• Address matching causes wake-up when processor is in low-power mode

LPUART

• One channel (2 channels on KW36A)

• Full-duplex operation

• Standard mark/space Non-return-to-zero (NRZ) format

• 13-bit baud rate selection with fractional divide of 32

• Programmable 8-bit or 9-bit data format

• Programmable 1 or 2 stop bits

• Separately enabled transmitter and receiver

• Programmable transmitter output polarity

• Programmable receive input polarity

• 13-bit break character option

• 11-bit break character detection option

Feature Descriptions

14 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

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• Two receiver wake-up methods:

• Idle line wake-up

• Address mark wake-up

• Address match feature in receiver to reduce address mark wake-up ISR overhead

• Interrupt or DMA driven operation

• Receiver framing error detection

• Hardware parity generation and checking

• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise

detection

• Operation in low-power modes

• Hardware Flow Control RTS\CTS

• Functional in Stop/VLPS modes

• Break detect supporting LIN

Serial Peripheral Interface (SPI)

• Two independent SPI channels

• Master and slave mode

• Full-duplex, three-wire synchronous transfers

• Programmable transmit bit rate

• Double-buffered transmit and receive data registers

• Serial clock phase and polarity options

• Slave select output

• Control of SPI operation during wait mode

• Selectable MSB-first or LSB-first shifting

• Support for both transmit and receive by DMA

Carrier Modulator Timer (CMT)

• Four modes of operation

• Time; with independent control of high and low times

• Baseband

• Frequency shift key (FSK)

• Direct software control of CMT_IRO signal

• Extended space operation in time, baseband, and FSK modes

• Selectable input clock divider

• Interrupt on end of cycle

• Ability to disable CMT_IRO signal and use as timer interrupt

General Purpose Input/Output (GPIO)

• Hysteresis and configurable pull up device on all input pins

• Independent pin value register to read logic level on digital pin

Feature Descriptions

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 15

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• All GPIO pins can generate IRQ and wake-up events

• Configurable drive strength on some output pins

• GPIO can be configured to function as a interrupt driven keyboard scanning matrix

• In the 48-pin package there are a total of 25 digital pins

• In the 40-pin package there are a total of 18 digital pins

FlexCAN (for KW36A only)

• Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol

specification and CAN protocol specification, Version 2.0 B

• Flexible Message Buffers (MBs); there are total 32 MBs of 8 bytes data length

each, configurable as Rx or Tx, all supporting standard and extended messages

• Programmable clock source to the CAN Protocol Interface, either peripheral clock

or oscillator clock

• Capability to select priority between mailboxes and Rx FIFO during matching

process

• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either

128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual

masking capability

2.6 Security Features

Advanced Encryption Standard Accelerator(AES-128 Accelerator)

The Advanced Encryption Standard Accelerator (AESA) module is a standalone

hardware coprocessor capable of accelerating the 128-bit advanced encryption standard

(AES) cryptographic algorithms.

The AESA engine supports the following cryptographic features.

LTC includes the following features:

• Cryptographic authentication

• Message Authentication Codes (MAC)

• Cipher-based MAC (AES-CMAC)

• Extended cipher block chaining message authentication code (AES-

XCBC-MAC)

• Auto padding

• Integrity Check Value(ICV) checking

• Authenticated encryption algorithms

• Counter with CBC-MAC (AES-CCM)

• Symmetric key block ciphers

Feature Descriptions

16 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

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• AES (128-bit keys)

• Cipher modes:

• AES-128 modes

• Electronic Codebook (ECB)

• Cipher Block Chaining (CBC)

• Counter (CTR)

• Secure scan

True Random Number Generator (TRNG)

True Random Number Generator (TRNG) is a hardware accelerator module that

constitutes a high-quality entropy source.

• TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-

consuming module, such as a deterministic random number generator.

• TRNG output can be read and used by a deterministic pseudo-random number

generator (PRNG) implemented in software.

• TRNG-PRNG combination achieves NIST-compliant true randomness and

cryptographic-strength random numbers using the TRNG output as the entropy

source.

• A fully FIPS 180 compliant solution can be realized using the TRNG together

with a FIPS-compliant deterministic random number generator and the SoC-level

security.

Flash Memory Protection

The on-chip flash memory controller enables the following useful features:

• Program flash protection scheme prevents accidental program or erase of stored

data.

• Automated, built-in, program and erase algorithms with verify.

• Read access to one program flash block is possible while programming or erasing

data in the other program flash block.

3Transceiver Description

• Direct Conversion Receiver (Zero IF)

• Constant Envelope Transmitter

• 2.36 GHz to 2.483 GHz PLL Range

• Low Transmit and Receive Current Consumption

• Low BOM

Transceiver Description

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NXP Semiconductors

3.1 Key Specifications

KW36A/35A/34A meets or exceeds all Bluetooth Low Energy version 5.0 performance

specifications. The key specifications for the KW36A/35A/34A are:

Frequency Band:

• ISM Band: 2400 to 2483.5 MHz

• MBAN Band: 2360 to 2400 MHz

Bluetooth Low Energy version 5.0 modulation scheme:

• Symbol rate: 1000 kbit/s

• Modulation: GFSK

• Receiver sensitivity: –95 dBm, typical

• Programmable transmitter output power: –30 dBm to +5 dBm

Generic FSK modulation scheme:

• Symbol rate: 250, 500 and 1000 kbit/s

• Modulation(s): GFSK (modulation index = 0.32, 0.5, 0.7 and 1.0, BT =0.3, 0.5, and

0.7), FSK and MSK

• Receiver Sensitivity: Mode and data rate dependent. –99 dBm typical for GFSK

(r=250 kbit/s, BT = 0.5, h = 0.5)

3.2 Channel Map Frequency Plans

3.2.1 Channel Plan for Bluetooth Low Energy

This section describes the frequency plan / channels associated with 2.4 GHz ISM and

MBAN bands for Bluetooth Low Energy.

2.4 GHz ISM Channel numbering:

• Fc=2402 + k * 2 MHz, k=0,.........,39.

MBAN Channel numbering:

• Fc=2360 + k in MHz, for k=0,.....,39

Transceiver Description

18 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

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where k is the channel number.

Table 1. 2.4 GHz ISM and MBAN frequency plan and channel designations

2.4 GHz ISM1MBAN22.4GHz ISM + MBAN

Channel Freq (MHz) Channel Freq (MHz) Channel Freq (MHz)

0 2402 0 2360 28 2390

1 2404 1 2361 29 2391

2 2406 2 2362 30 2392

3 2408 3 2363 31 2393

4 2410 4 2364 32 2394

5 2412 5 2365 33 2395

6 2414 6 2366 34 2396

7 2416 7 2367 35 2397

8 2418 8 2368 36 2398

9 2420 9 2369 0 2402

10 2422 10 2370 1 2404

11 2424 11 2371 2 2406

12 2426 12 2372 3 2408

13 2428 13 2373 4 2410

14 2430 14 2374 5 2412

15 2432 15 2375 6 2414

16 2434 16 2376 7 2416

17 2436 17 2377 8 2418

18 2438 18 2378 9 2420

19 2440 19 2379 10 2422

20 2442 20 2380 11 2424

21 2444 21 2381 12 2426

22 2446 22 2382 13 2428

23 2448 23 2383 14 2430

24 2450 24 2384 15 2432

25 2452 25 2385 16 2434

26 2454 26 2386 17 2436

27 2456 27 2387 18 2438

28 2458 28 2388 19 2440

29 2460 29 2389 20 2442

30 2462 30 2390 21 2444

31 2464 31 2391 22 2446

32 2466 32 2392 23 2448

33 2468 33 2393 24 2450

34 2470 34 2394 25 2452

Table continues on the next page...

Transceiver Description

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 19

NXP Semiconductors

Table 1. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)

2.4 GHz ISM1MBAN22.4GHz ISM + MBAN

Channel Freq (MHz) Channel Freq (MHz) Channel Freq (MHz)

35 2472 35 2395 26 2454

36 2474 36 2396 27 2456

37 2476 37 2397 37 2476

38 2478 38 2398 38 2478

39 2480 39 2399 39 2480

1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz

2. Per FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.

3.2.2 Other Channel Plans

The RF synthesizer can be configured to use any channel frequency between 2.36 and

2.487 GHz.

3.3 Transceiver Functions

Receive

The receiver architecture is Zero IF (ZIF) where the received signal after passing

through RF front end is down-converted to a baseband signal. The signal is filtered and

amplified before it is fed to analog-to-digital converter. The digital signal then

decimates to a baseband clock frequency before it digitally processes, demodulates and

passes on to packet processing/link-layer processing.

Transmit

The transmitter transmits GFSK/FSK modulation having power and channel selection

adjustment per user application. After the channel of operation is determined, coarse

and fine-tuning is executed within the Frac-N PLL to engage signal lock. After signal

lock is established, the modulated buffered signal is routed to a multi-stage amplifier for

transmission..

4Transceiver Electrical Characteristics

Transceiver Electrical Characteristics

20 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

4.1 Radio operating conditions

Table 2. Radio operating conditions

Characteristic Symbol Min Typ Max Unit

Input Frequency fin 2.360 — 2.480 GHz

Ambient Temperature Range TA–40 25 105 °C

Maximum RF Input Power Pmax — — 10 dBm

Crystal Reference Oscillator Frequency

fref 26 MHz or 32 MHz

1. The recommended crystal accuracy is ±40 ppm including initial accuracy, mechanical, temperature, and aging factors.

4.2 Receiver Feature Summary

Table 3. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise

noted)

Characteristic1Symbol Min. Typ. Max. Unit

Supply current power down on VDD_RFx supplies Ipdn — 200 1000 nA

Supply current Rx On with DC-DC converter enable

(Buck; VDCDC_IN = 3.6 V, VDD_1P5_buck=1.5 V) , 2IRxon — 6.3 — mA

Supply current Rx On with DC-DC converter disabled

(Bypass) 2IRxon — 17.2 — mA

Input RF Frequency fin 2.360 — 2.4835 GHz

GFSK Rx Sensitivity(250 kbit/s GFSK-BT=0.5, h=0.5) SENSGFSK — –99 — dBm

Bluetooth LE Rx Sensitivity 3SENSBLE — –95 — dBm

Noise Figure for maximum gain mode @ typical

sensitivity

NFHG — 7.5 — dB

Receiver Signal Strength Indicator Range4RSSIRange –100 — 55dBm

Receiver Signal Strength Indicator Resolution RSSIRes — 1 — dB

Typical RSSI variation over frequency –2 — 2 dB

Typical RSSI variation over temperature –2 — 2 dB

Narrowband RSSI accuracy6RSSIAcc –3 — 3 dB

Bluetooth LE Co-channel Interference (Wanted signal at

–67 dBm, BER <0.1%. Measurement resolution 1

MHz).

–7 dB

Adjacent/Alternate Channel Performance7

Bluetooth LE Adjacent +/–1 MHz Interference offset

(Wanted signal at –67 dBm, BER <0.1%. Measurement

resolution 1 MHz.)

SELBLE, 1 MHz — 2 — dB

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Transceiver Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 21

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Table 3. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise

noted) (continued)

Characteristic1Symbol Min. Typ. Max. Unit

Bluetooth LE Adjacent +/–2 MHz Interference offset

(Wanted signal at –67 dBm, BER <0.1%. Measurement

resolution 1 MHz.)

SELBLE, 2 MHz — 43 — dB

Bluetooth LE Alternate +/–3 MHz Interference offset

(Wanted signal at –67 dBm, BER <0.1%. Measurement

resolution 1 MHz.)

SELBLE, 3 MHz — 50 — dB

Bluetooth LE Alternate ≥ +/–4 MHz Interference offset

(Wanted signal at –67 dBm, BER <0.1%. Measurement

resolution 1 MHz.)

SELBLE, 4+ MHz — 50 — dB

Intermodulation Performance

Bluetooth LE Intermodulation with continuous wave

interferer at ± 3 MHz and modulated interferer is at ± 6

MHz (Wanted signal at –67 dBm, BER<0.1%.)

— –23 — dBm

Bluetooth LE Intermodulation with continuous wave

interferer at ±5 MHz and modulated interferer is at ±10

MHz (Wanted signal at –67 dBm, BER<0.1%.)

— –24 — dBm

Blocking Performance

Bluetooth LE Out of band blocking from 30 MHz to 1000

MHz and 4000 MHz to 5000 MHz (Wanted signal at –67

dBm, BER<0.1%. Interferer continuous wave signal.)8

— –2 — — dBm

Bluetooth LE Out of band blocking from 1000 MHz to

2000 MHz and 3000 MHz to 4000 MHz (Wanted signal

at –67 dBm, BER<0.1%. Interferer continuous wave

signal.)

— –8.4 — — dBm

Bluetooth LE Out of band blocking from 2001 MHz to

2339 MHz and 2484 MHz to 2999 MHz (Wanted signal

at –67 dBm, BER<0.1%. Interferer continuous wave

signal.)9

— –17 — — dBm

Bluetooth LE Out of band blocking from 5000 MHz to

12750 MHz (Wanted signal at –67 dBm, BER<0.1%.

Interferer continuous wave signal.)9

— — 10 — dBm

Spurious Emission < 1.6 MHz offset (Measured with

100 kHz resolution and average detector. Device

transmit on RF channel with center frequency fc and

spurious power measured in 1 MHz at RF frequency f),

where |f-fc|< 1.6 MHz

— — –54 — dBc

Spurious Emission > 2.5 MHz offset (Measured with

100 kHz resolution and average detector. Device

transmit on RF channel with center frequency fc and

spurious power measured in 1 MHz at RF frequency f),

where |f-fc|> 2.5 MHz10

— — –70 — dBc

1. All the Rx parameters are measured at the KW36A/35A/34A RF pins.

2. Transceiver power consumption.

3. Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.

4. Narrow-band RSSI mode.

5. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.

6. With one point calibration over frequency and temperature.

Transceiver Electrical Characteristics

22 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

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7. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.

8. Exceptions allowed for carrier frequency sub harmonics.

9. Exceptions allowed for carrier frequency harmonics.

10. Exceptions allowed for twice the reference clock frequency(fref) multiples.

Table 4. Receiver Specifications with Generic FSK Modulations

Adjacent/Alternate Channel Selectivity (dB)1

Modulation

Type

Data

Rate

(kbit/s)

Channel

BW (kHz)

Typical

Sensitivity

(dBm)

Desired

signal

level

(dBm)

Interferer

at –/+1*

channel

offset

Interferer

at –/+ 2*

channel

offset

Interferer

at –/+ 3*

channel

offset

Interferer

at –/+ 4*

channel

offset

Co-

channel

GFSK BT =

0.5, h=0.5

1000 2000 –95 –67 43 50 55 50 –7

500 1000 –97 –85 40 50 55 55 –7

250 500 –99 –85 30 40 50 50 –7

GFSK, BT =

0.5, h=0.3

1000 1000 –89 –67 10 38 42 47 –10

500 800 –92 –85 22 31 37 42 –10

250 500 –93 –85 20 25 30 34 –13

GFSK, BT =

0.5, h=0.7

1000 2000 –97 –85 45 50 57 60 –7

500 1000 –98 –85 40 50 55 55 –7

250 600 –99 –85 30 40 50 50 –7

GMSK

BT=0.3

1000 1600 –91 –85 40 46 53 55 –8

500 800 –93 –85 35 46 50 53 –7

250 500 –95 –85 30 40 40 50 –7

GMSK, BT =

0.7

1000 2000 –96 –85 44 53 57 60 –7

500 1000 –97 –85 40 50 55 55 –7

250 600 –99 –85 30 40 50 50 –7

Generic

MSK

1000 3000 –96 –85 43 53 60 63 –7

500 1600 –97 –85 43 50 60 60 –8

250 800 –99 –85 35 45 55 55 –7

GFSK

BT=0.5, h=1

1000 3000 –96 –85 45 55 55 59 –8

500 1400 –97 –85 40 45 50 50 –8

250 800 –98 –85 35 45 45 50 –8

1. Selectivity measured with an unmodulated blocker except for GFSK BT=0.5, h=0.5 1 Mbit/s and GFSK BT=0.5,

h=0.32 1 Mbit/s. The desired signal is set at –85 dBm.

4.3 Transmit and PLL Feature Summary

• Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN

frequency bands

• Fast PLL Lock time: < 25 µs

• Reference Frequency:

Transceiver Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 23

NXP Semiconductors

• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK

modes

Table 5. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise

noted)

Characteristic1Symbol Min. Typ. Max. Unit

Supply current power down on VDD_RFx supplies Ipdn — 200 — nA

Supply current Tx On with PRF = 0 dBm and DC-DC

converter enabled (Buck; VDDDCDC_in = 3.6 V,

VDD_1P5_buck=1.5 V) , 2

ITxone — 5.7 — mA

Supply current Tx On with PRF = 0 dBm and DC-DC

converter disabled (Bypass) 2ITxond — 16 — mA

Supply current Tx On with PRF = +3.5 dBm and DC-DC

converter enabled (Buck; VDDDCDC_in = 3.6 V,

VDD_1P5_buck=1.5 V)2

ITX3.5dBm — 6.9 — mA

Supply current Tx On with PRF = +3.5 dBm and DC-DC

converter disabled (Bypass)2ITX3.5dBmb — 19 — mA

Supply current Tx On with PRF = +5 dBm and DC-DC

converter enabled (Buck; VDDDCDC_in = 3.6 V,

VDD_1P5_buck=1.55 V, LDO-HF bumped)2, 3

ITX5dBm — 8.0 — mA

Supply current Tx On with PRF = +5 dBm and DC-DC

converter disabled (Bypass, LDO-HF bumped)2, 3ITX5dBmb — 21 — mA

Output RF Frequency fRFout 2.360 — 2.4835 GHz

Maximum RF Output Power; LDO-HF bumped 4PRF,maxV — +5 — dBm

Maximum RF Output power, nominal power supply 5PRF,maxn — +3.5 — dBm

Minimum RF Output power, nominal power supply 5PRF,minn — –30 — dBm

RF Output power control range PRFCR — 34 — dB

Bluetooth LE Tx Output Spectrum 20dB BW TXBWBLE 1.0 — MHz

Bluetooth LE average frequency deviation using a

00001111 modulation sequence

Δf1avg,BLE 250 kHz

Bluetooth LE average frequency deviation using a

01010101 modulation sequence

Δf2avg,BLE 220 kHz

Bluetooth LE RMS FSK Error FSKerr,BLE 3%

Bluetooth LE Maximum Deviation of the Center

Frequency6Fcdev,BLE — ±3 — kHz

Bluetooth LE Adjacent Channel Transmit Power at 2

MHz offset7PRF2MHz,BLE — — –55 dBm

Bluetooth LE Adjacent Channel Transmit Power at >= 3

MHz offset7PRF3MHz,BLE — — –59 dBm

Bluetooth LE Frequency Hopping Support YES

Second Harmonic of Transmit Carrier Frequency (Pout =

PRF,max), 8TXH2 — –46 — dBm/MHz

Third Harmonic of Transmit Carrier Frequency (Pout =

PRF,max)8TXH3 — –58 — dBm/MHz

1. All the Tx parameters are measured at test hardware SMA connector.

2. Transceiver power consumption.

Transceiver Electrical Characteristics

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3. VDD_RFx shall be equal to or higher than 1.55 V to support a TX Pout of +5 dBm.

4. Measured at KW36A/35A/34A RF pins, with BB_LDO_HF_TRIM=1.44 V.

5. Measured at the KW36A/35A/34A RF pins.

6. Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.

7. Measured at Pout = +5 dBm and recommended Tx match.

8. Harmonic levels based on recommended 2 component match. Transmit harmonic levels depend on the quality of

matching components. Additional harmonic margin using a third matching component (1x shunt capacitor) is possible.

Transmit PA driver output as a function of the PA_POWER[5:0] field when measured

at the IC pins is as follows:

Figure 4. TX Pout (dBm) as function TX-PA Power Code for default LDO-HF

Table 6. Transmit Output Power as a function of PA_POWER[5:0] with default LDO-HF

TX Pout (dBm)1

PA_POWER[5:0] T = –40 °C T = 25 °C T = 105 °C

1 –30.1 –31.1 –32.6

2 –24.0 –25.0 –26.4

4 –17.9 –19.0 –20.4

6 –14.5 –15.6 –17.0

8 –12.0 –13.1 –14.5

10 –10.1 –11.2 –12.6

12 –8.5 –9.6 –11.0

14 –7.2 –8.3 –9.7

16 –6.1 –7.2 –8.6

Table continues on the next page...

Transceiver Electrical Characteristics

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Table 6. Transmit Output Power as a function of PA_POWER[5:0] with default LDO-HF

(continued)

TX Pout (dBm)1

PA_POWER[5:0] T = –40 °C T = 25 °C T = 105 °C

18 –5.1 –6.2 –7.6

20 –4.2 –5.3 –6.7

22 –3.4 –4.5 –5.9

24 –2.7 –3.8 –5.2

26 –2.0 –3.1 –4.5

28 –1.4 –2.5 –3.9

30 –0.8 –1.9 –3.3

32 –0.3 –1.4 –2.8

34 0.2 –1.0 –2.4

36 0.6 –0.5 –1.9

38 1.1 –0.1 –1.5

40 1.5 0.3 –1.1

42 1.9 0.7 –0.7

44 2.2 1.1 –0.3

46 2.6 1.4 0.0

48 2.9 1.8 0.3

50 3.2 2.1 0.6

52 3.5 2.4 0.9

54 3.7 2.6 1.2

56 3.9 2.9 1.5

58 4.2 3.1 1.7

60 4.4 3.3 1.9

62 4.5 3.5 2.1

1. Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.

Transceiver Electrical Characteristics

26 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Figure 5. TX Pout (dBm) as a function of TX-PA Power Code for LDO-HF bumped

Table 7. Transmit Output Power as a function of PA_POWER[5:0] with LDO-HF Bumped

TX Pout (dBm)1

PA_POWER[5:0] T = –40 °C T = 25 °C T = 105 °C

1 –28.5 –29.6 –30.4

2 –22.4 –23.4 –24.2

4 –16.4 –17.5 –18.3

6 –12.9 –13.9 –14.8

8 –10.4 –11.5 –12.3

10 –8.5 –9.5 –10.4

12 –6.9 –8.0 –8.8

14 –5.6 –6.6 –7.5

16 –4.4 –5.5 –6.3

18 –3.4 –4.5 –5.3

20 –2.5 –3.6 –4.4

22 –1.7 –2.8 –3.6

24 –0.9 –2.0 –2.9

26 –0.3 –1.4 –2.2

28 0.4 –0.7 –1.6

30 1.0 –0.1 –1.0

32 1.4 0.3 –0.5

Table continues on the next page...

Transceiver Electrical Characteristics

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Table 7. Transmit Output Power as a function of PA_POWER[5:0] with LDO-HF Bumped

(continued)

TX Pout (dBm)1

PA_POWER[5:0] T = –40 °C T = 25 °C T = 105 °C

34 2.0 0.9 0.0

36 2.4 1.3 0.4

38 2.9 1.8 0.9

40 3.3 2.2 1.3

42 3.7 2.6 1.7

44 4.1 3.0 2.1

46 4.5 3.4 2.5

48 4.8 3.7 2.8

50 5.2 4.0 3.1

52 5.5 4.4 3.4

54 5.8 4.6 3.7

56 6.0 4.9 4.0

58 6.3 5.2 4.2

60 6.5 5.4 4.5

62 6.7 5.6 4.7

1. Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.

5 System and Power Management

5.1 Power Management

The KW36A/35A/34A includes internal power management features that can be used to

control the power usage. The power management of the KW36A/35A/34A includes

Power Management Controller (PMC) and a DC-DC converter which can operate in a

buck or bypass configuration. The PMC is designed such that the RF radio remains in

state-retention while the core is in various stop modes. It makes sure that the device can

stay in low current consumption mode while the RF radio can wake-up quick enough

for communication.

5.1.1 DC-DC Converter

The features of the DC-DC converter include the following:

System and Power Management

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• Single inductor, multiple outputs.

• Buck mode (pin selectable; CFG=VDCDC_IN).

• Continuous or pulsed operation (hardware/software configurable).

• Power switch input to allow external control of power up, and to select DC-DC

bypass mode in which all the SoC power supplies (see Table 3) are externally

provided.

• Output signal to indicate power stable. Purpose is for the rest of the chip to be

used as a POR.

• Scaled battery output voltage suitable for SAR ADC utilization.

• Internal oscillator for support when the reference oscillator is not present.

5.2 Modes of Operation

The Arm Cortex-M0+ core in the KW36A/35A/34A has three primary modes of

operation: Run, Wait, and Stop modes. For each run mode, there is a corresponding

wait and stop mode. Wait modes are similar to Arm sleep modes. Stop modes are

similar to Arm deep sleep modes. The very low-power run (VLPR) operation mode

can drastically reduce runtime power when the maximum bus frequency is not

required to handle the application needs.

The WFI instruction invokes both wait and stop modes. The primary modes are

augmented in a number of ways to provide lower power based on application needs.

5.2.1 Power modes

The power management controller (PMC) provides multiple power options to allow

the user to optimize power consumption for the level of functionality needed.

Depending on the stop requirements of the user application, various stop modes are

available that provide state retention, partial power down, or full power down of

certain logic and/or memory. I/O states are held in all modes of operation. The

following table compares the various power modes available.

For each run mode, there is a corresponding wait and stop mode. Wait modes are

similar to Arm sleep modes. Stop modes (VLPS, STOP) are similar to Arm sleep deep

mode. The very-low-power run (VLPR) operating mode can drastically reduce

runtime power when the maximum bus frequency is not required to handle the

application needs.

System and Power Management

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 29

NXP Semiconductors

The three primary modes of operation are run, wait, and stop. The WFI instruction

invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System

Control Register. The primary modes are augmented in a number of ways to provide

lower power based on application needs.

Table 8. Power modes (At 25 deg C)

Power mode Description CPU

recovery

method

Radio

Normal Run (all

peripherals clock off)

Allows maximum performance of chip. — Radio can be active

Normal Wait - via WFI Allows peripherals to function, while allowing CPU to

go to sleep reducing power.

Interrupt

Normal Stop - via

WFI

Places chip in static state. Lowest power mode that

retains all registers while maintaining LVD protection.

Interrupt

PStop2 (Partial Stop

Core and system clocks are gated. Bus clock

remains active. Masters and slaves clocked by bus

clock remain in Run or VLPRun mode. The clock

generators in MCG and the on-chip regulator in the

PMC also remain in Run or VLPRun mode.

Interrupt

PStop1 (Partial Stop

Core, system clocks, and bus clock are gated. All

bus masters and slaves enter Stop mode. The clock

generators in MCG and the on-chip regulator in the

PMC also remain in Run or VLPRun mode.

Interrupt

VLPR (Very Low-

power Run) (all

peripherals off)

Reduced frequency (1 MHz) Flash access mode,

regulator in low-power mode, LVD off. Internal

oscillator can provide low-power 4 MHz source for

core. (Values @2 MHz core/ 1 MHz bus and flash,

module off, execution from flash).

Biasing is disabled when DC-DC is configured for

continuous mode in VLPR/W

— Radio operation is possible

only when DC-DC is

configured for continuous

mode.1 However, there may

be insufficient MIPS with a 4

MHz MCU to support much in

the way of radio operation.

VLPW (Very Low-

power Wait) - via WFI

(all peripherals off)

Similar to VLPR, with CPU in sleep to further reduce

power. (Values @4 MHz core/ 1 MHz bus, module

off)

Biasing is disabled when DC-DC is configured for

continuous mode in VLPR/W

Interrupt

VLPS (Very Low-

power Stop) via WFI

Places MCU in static state with LVD operation off.

Lowest power mode with ADC and all pin interrupts

functional. LPTMR, RTC, CMP can be operational.

Biasing is disabled when DC-DC is configured for

continuous mode in VLPS.

Interrupt

LLS3 (Low Leakage

Stop)

State retention power mode. LLWU, LPTMR, RTC,

CMP can be operational. All of the radio Sea of

Gates(SOG) logic is in state retention.

Wake-up

Interrupt

Radio SOG is in state

retention in LLSx. The

Bluetooth LE/Generic FSK

DSM2 logic can be active

using the 32 kHz clock

LLS2 (Low Leakage

Stop)

State retention power mode. LLWU, LPTMR, RTC,

CMP can be operational. 16 KB or 32 KB of

programmable RAM can be powered on. All of the

radio SOG logic is in state retention.

Wake-up

Interrupt

Table continues on the next page...

System and Power Management

30 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 8. Power modes (At 25 deg C) (continued)

Power mode Description CPU

recovery

method

Radio

VLLS3 (Very Low

Leakage Stop3)

Full SRAM retention. LLWU, LPTMR, RTC, CMP can

be operational. All of the radio SOG logic is in state

retention.

Wake-up

Reset

Radio SOG is in state

retention in VLLS3/2. The

Bluetooth LE/Generic FSK

DSM logic can be active

using the 32 kHz clock.

VLLS2 (Very Low

Leakage Stop2)

Partial SRAM retention. 16 KB or 32 KB of

programmable RAM can be powered on. LLWU,

LPTMR, RTC, CMP can be operational. All of the

radio SOG logic is in state retention.

Wake-up

Reset

VLLS1 (Very Low

Leakage Stop1) with

RTC + 32 kHz OSC

All SRAM powered off. The 32-byte system register

file remains powered for customer-critical data.

LLWU, LPTMR, RTC, CMP can be operational.

Radio logic is power gated.

Wake-up

Reset

Radio operation not

supported. The Radio SOG is

power-gated in VLLS1. Radio

state is lost at VLLS1 and

lower power states.

VLLS1 (Very Low

Leakage Stop1) with

LPTMR + LPO

All SRAM powered off. The 32-byte system register

file remains powered for customer-critical data.

LLWU, LPTMR, RTC, CMP can be operational.

Wake-up

Reset

VLLS0 (Very Low

Leakage Stop0) with

Brown-out Detection

VLLS0 is not supported with DC-DC.

The 32-byte system register file remains powered for

customer-critical data. Disable all analog modules in

PMC and retains I/O state and DGO state. LPO

disabled, POR brown-out detection enabled, Pin

interrupt only. Radio logic is power gated.

Wake-up

Reset

Radio operation not

supported. The Radio digital

is power-gated in VLLS0.

VLLS0 (Very Low

Leakage Stop0)

without Brown-out

Detection

VLLS0 is not supported with DC-DC buck

configuration but is supported with bypass

configuration.

The 32-byte system register file remains powered for

customer-critical data. Disable all analog modules in

PMC and retains I/O state and DGO state. LPO

disabled, POR brown-out detection disabled, Pin

interrupt only. Radio logic is power gated.

Wake-up

Reset

1. Biasing is disabled, but the Flash is in a low-power mode for VLPx, so this configuration can realize some power

savings over use of Run/Wait/Stop.

2. DSM refers to Radio's deep sleep mode. DSM does not refer to the Arm sleep deep mode.

6 KW36A/35A/34A Electrical Characteristics

6.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

KW36A/35A/34A Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 31

NXP Semiconductors

80%

20%

50%

VIL

Input Signal

VIH

Fall Time

High

Low

Rise Time

Midpoint1

The midpoint is VIL + (VIH - VIL) / 2

Figure 6. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assume that the

output pins have the following characteristics.

• CL=30 pF loads

• Slew rate disabled

• Normal drive strength

6.2 Nonswitching electrical specifications

6.2.1 Voltage and current operating requirements

Table 9. Voltage and current operating requirements

Symbol Description Min. Max. Unit Notes

VDD Supply voltage 1.71 3.6 V

VDD_1P5 DCDC VDD_1P5 output pin 1.425 3.6 V 1

VDDA Analog supply voltage 1.71 3.6 V

VDD – VDDA VDD-to-VDDA differential voltage –0.1 0.1 V

VSS – VSSA VSS-to-VSSA differential voltage –0.1 0.1 V

VIH Input high voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

0.7 × VDD

0.75 × VDD

—

VIL Input low voltage

• 2.7 V ≤ VDD ≤ 3.6 V

• 1.7 V ≤ VDD ≤ 2.7 V

—

0.35 × VDD

0.3 × VDD

VHYS Input hysteresis 0.06 × VDD — V

IICIO IO pin negative DC injection current — single pin

• VIN < VSS–0.3V –3 — mA

Table continues on the next page...

KW36A/35A/34A Electrical Characteristics

32 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 9. Voltage and current operating requirements (continued)

Symbol Description Min. Max. Unit Notes

IICcont Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents of 16

contiguous pins

• Negative current injection –25 — mA

VODPU Open drain pullup voltage level VDD VDD V3

VRAM VDD voltage required to retain RAM 1.2 — V

1. This limit applies in any DCDC mode.

2. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN

greater than VIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current limiting resistors at the pads.

If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting

resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.

3. Open drain outputs must be pulled to VDD.

6.2.2 LVD and POR operating requirements

Table 10. VDD supply LVD and POR operating requirements

Symbol Description Min. Typ. Max. Unit Notes

VPOR Falling VDD POR detect voltage 0.8 1.1 1.5 V

VPOR_VDD_

1P5

VDD_1P5 POR threshold 1.25 1.31 1.37 V

VLVDH Falling low-voltage detect threshold — high

range (LVDV = 01)

2.48 2.56 2.64 V

VLVW1H

VLVW2H

VLVW3H

VLVW4H

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV = 00)

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

VHYSH Low-voltage inhibit reset/recover hysteresis —

high range

— ±60 — mV

VLVDL Falling low-voltage detect threshold — low

range (LVDV=00)

1.54 1.60 1.66 V

VLVW1L

VLVW2L

VLVW3L

VLVW4L

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV = 00)

• Level 2 falling (LVWV = 01)

• Level 3 falling (LVWV = 10)

• Level 4 falling (LVWV = 11)

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

VHYSL Low-voltage inhibit reset/recover hysteresis —

low range

— ±40 — mV

Table continues on the next page...

KW36A/35A/34A Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 33

NXP Semiconductors

Table 10. VDD supply LVD and POR operating requirements (continued)

Symbol Description Min. Typ. Max. Unit Notes

VBG Bandgap voltage reference 0.97 1.00 1.03 V

tLPO Internal low-power oscillator period — factory

trimmed

900 1000 1100 μs

1. Rising thresholds are falling threshold + hysteresis voltage

6.2.3 Voltage and current operating behaviors

Table 11. Voltage and current operating behaviors

Symbol Description Min. Max. Unit Notes

VOH Output high voltage — Normal drive pad (except

RESET_b)

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1 mA

VDD – 0.5

VDD – 0.35

—

1, 2

VOH Output high voltage — High drive pad (except

RESET_b)

• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA

VDD – 0.5

—

1, 2

IOHT Output high current total for all ports — 100 mA

VOL Output low voltage — Normal drive pad

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA

—

0.5

VOL Output low voltage — High drive pad

• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA

• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA

—

0.5

IOLT Output low current total for all ports — 100 mA

IIN Input leakage current (per pin) for full temperature

range

— 500 nA 3

IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3

IIN Input leakage current (total all pins) for full

temperature range

— 5 μA 3

RPU Internal pullup resistors 20 50 kΩ 4

1. PTB0-1 and PTC0-3, PTC6, PTC7, PTC17, PTC18 I/O have both high drive and normal drive capability selected by the

associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

2. The reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When

configured as a GPIO output, it acts as a pseudo open drain output.

3. Measured at VDD = 3.6 V.

KW36A/35A/34A Electrical Characteristics

34 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

4. Measured at VDD supply voltage = VDD min and Vinput = VSS.

6.2.4 Power mode transition operating behaviors

All specifications except tPOR and VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 48 MHz

• Bus and flash clock = 24 MHz

• FEI clock mode

POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system

frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.

Table 12. Power mode transition operating behaviors

Symbol Description Max. Unit Notes

tPOR After a POR event, amount of time from the point VDD

reaches 1.8 V to execution of the first instruction across the

operating temperature range of the chip.

300 μs 1

• VLLS0 → RUN

169.0

μs

• VLLS1 → RUN

168.9

μs

• VLLS2 → RUN

97.3

μs

• VLLS3 → RUN

97.3

μs

• LLS → RUN

6.3

μs

• VLPS → RUN

6.2

μs

• STOP → RUN

6.2

μs

1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300

µs spec when 1) VDD_1P5 < 1.6 V at 25 °C and 125 °C. 2) 1.5V ≤ VDD_1P5 ≤ 1.8 V. For the bypass mode special

case where VDD_1P5 = VDD_1P8, TPOR did not meet the 300 µs maximum spec when the supply slew rate <=100

V/s.

KW36A/35A/34A Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 35

NXP Semiconductors

6.2.5 Power consumption operating behaviors

Table 13. Power consumption operating behaviors - Bypass Mode

Symbol Description Typ. Max. Unit Notes

IDDA Analog supply current — See note mA 1

IDD_RUNCO_C

Run mode current in compute operation - 48 MHz

core / 24 MHz flash / bus disabled, LPTMR running

using LPO clock at 1kHz, CoreMark benchmark code

executing from flash at 3.0 V

6.80

8.41

2, 3

IDD_RUNCO Run mode current in compute operation - 48 MHz

core / 24 MHz flash / bus clock disabled, code of

while(1) loop executing from flash at 3.0 V

4.05

4.98

3, 4

IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks disabled, code of while(1)

loop executing from flash at 3.0 V

5.00

6.01

3, 4

IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks enabled, code of while(1)

loop executing from flash at 3.0 V

at 25 °C

at 70 °C

at 105 °C

6.48

6.77

7.13

6.70

6.96

7.90

3, 4, 5

IDD_WAIT Wait mode current - core disabled / 48 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

3.07 4.31 mA

IDD_WAIT Wait mode current - core disabled / 24 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

2.29 3.15 mA

IDD_PSTOP2 Stop mode current with partial stop 2 clocking option

- core and system disabled / 10.5 MHz bus at 3.0 V 2.32 3.11 mA

IDD_VLPRCO_

Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus clock

disabled, LPTMR running using LPO clock at 1 kHz

reference clock, CoreMark benchmark code

executing from flash at 3.0 V

766.9 1538 μA

IDD_VLPRCO Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus clock

disabled, code of while(1) loop executing from flash

at 3.0 V

158.45 377 μA

IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks disabled,

code of while(1) loop executing from flash at 3.0 V

185.26 410 μA

IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks enabled,

code of while(1) loop executing from flash at 3.0 V

240.96 805.3 μA

5, 7

IDD_VLPW Very-low-power wait mode current - core disabled / 4

MHz system / 0.8 MHz bus / flash disabled (flash

doze enabled), all peripheral clocks disabled at 3.0 V

133.95 552.8 μA 7

IDD_STOP Stop mode current at 3.0 V

Table continues on the next page...

KW36A/35A/34A Electrical Characteristics

36 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 13. Power consumption operating behaviors - Bypass Mode (continued)

Symbol Description Typ. Max. Unit Notes

at 25 °C

at 70 °C

at 105 °C

204.98

291.89

599.46

308.3

872.5

1662

μA

IDD_VLPS Very-low-power stop mode current at Bypass

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

6.4

30.64

157

76.6

328

μA

IDD_LLS3 Low-leakage stop mode 3 current at Bypass

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

2.57

11.76

50.92

4.31

26.07

105.4

μA

IDD_LLS2 Low-leakage stop mode 2 current at Bypass

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

2.35

9.74

42.34

3.30

21.40

80.23

μA

IDD_VLLS3 Very-low-leakage stop mode 3 current at Bypass

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

2.13

10.78

46.70

3.3

22.97

83.54

μA

IDD_VLLS2 Very-low-leakage stop mode 2 current at Bypass

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

1.84

7.88

34.76

2.40

15.19

57.85

μA

IDD_VLLS1 Very-low-leakage stop mode 1 current at Bypass

mode(3.0 V),

at 25°C

at 70°C

at 105°C

851.45

3.57

17.62

1027.8

6.28

23.06

μA

IDD_VLLS0 Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 0) at 3.0 V

at 25 °C

at 70 °C

at 105 °C

433.00

3.15

17.2

720.3

6.14

23.2

μA

Table continues on the next page...

KW36A/35A/34A Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 37

NXP Semiconductors

Table 13. Power consumption operating behaviors - Bypass Mode (continued)

Symbol Description Typ. Max. Unit Notes

IDD_VLLS0 Very-low-leakage stop mode 0 current

(SMC_STOPCTRL[PORPO] = 1) at 3.0 V

at 25 °C

at 70 °C

at 105 °C

258.12

2.97

16.9

516.43

5.81

22.4

μA

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

2. MCG configured for FEI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for

balanced.

3. Radio is off.

4. MCG configured for FEI mode.

5. Incremental current consumption from peripheral activity is not included.

6. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized

for balanced.

7. MCG configured for BLPI mode.

8. No brownout.

Table 14. Power consumption operating behaviors - Buck Mode1

Symbol Description Typ. Max. Unit Notes

IDDA Analog supply current — See note mA 2

IDD_RUNCO Run mode current in compute operation - 48 MHz

core / 24 MHz flash / bus clock disabled, code of

while(1) loop executing from flash at 3.0 V

3.51

—

3, 4

IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks disabled, code of while(1)

loop executing from flash at 3.0 V

4.00

—

3, 4

IDD_RUN Run mode current - 48 MHz core / 24 MHz bus and

flash, all peripheral clocks enabled, code of while(1)

loop executing from flash at 3.0 V

at 25 °C

at 70 °C

at 105 °C

5.81

5.92

6.36

—

3, 4, 5

IDD_WAIT Wait mode current - core disabled / 48 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

2.97 — mA

IDD_WAIT Wait mode current - core disabled / 24 MHz system /

24 MHz bus / flash disabled (flash doze enabled), all

peripheral clocks disabled at 3.0 V

2.51 — mA

IDD_PSTOP2 Stop mode current with partial stop 2 clocking option

- core and system disabled / 10.5 MHz bus at 3.0 V 2.33 — mA

IDD_VLPRCO Very-low-power run mode current in compute

operation - 4 MHz core / 0.8 MHz flash / bus clock

disabled, code of while(1) loop executing from flash

at 3.0 V

101.75 — μA

Table continues on the next page...

KW36A/35A/34A Electrical Characteristics

38 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 14. Power consumption operating behaviors - Buck Mode1 (continued)

Symbol Description Typ. Max. Unit Notes

IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks disabled,

code of while(1) loop executing from flash at 3.0 V

132.17 — μA

IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8

MHz bus and flash, all peripheral clocks enabled,

code of while(1) loop executing from flash at 3.0 V

167.65 — μA

5, 6

IDD_VLPW Very-low-power wait mode current - core disabled / 4

MHz system / 0.8 MHz bus / flash disabled (flash

doze enabled), all peripheral clocks disabled at 3.0 V

105.72 — μA 6

IDD_STOP Stop mode current at 3.0 V

at 25 °C

at 70 °C

at 105 °C

1.43

1.56

1.99

2.32

4.35

4.68

IDD_VLPS Very-low-power stop mode current at Buck mode(3.0

V),

at 25 °C

at 70 °C

at 105 °C

4.18

44.30

218.64

14.98

110

446

μA

IDD_LLS3 Low-leakage stop mode 3 current at Buck mode(3.0

V),

at 25 °C

at 70 °C

at 105 °C

2.64

15.27

81.93

4.89

25.51

104.35

μA

IDD_LLS2 Low-leakage stop mode 2 current at Buck mode(3.0

V),

at 25 °C

at 70 °C

at 105 °C

2.46

10.14

63.49

3.80

21.14

80.21

μA

IDD_VLLS3 Very-low-leakage stop mode 3 current at Buck

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

2.03

12.44

62.23

3.28

23.8

83.9

μA

IDD_VLLS2 Very-low-leakage stop mode 2 current at Buck

mode(3.0 V),

at 25 °C

at 70 °C

at 105 °C

1.79

8.87

49.39

2.43

16.7

62.94

μA

IDD_VLLS1 Very-low-leakage stop mode 1 current at Buck

mode(3.0 V),

KW36A/35A/34A Electrical Characteristics

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 39

NXP Semiconductors

Table 14. Power consumption operating behaviors - Buck Mode1

Symbol Description Typ. Max. Unit Notes

at 25 °C

at 70 °C

at 105 °C

0.830

4.95

27.51

1.07

10.67

36.14

μA

1. The device was configured in buck mode auto-start to perform the measurements. The DCDC_IN was powered with 3.0

V. VDD_1P8OUT was configured to output 1.8 V and VDD_1P5OUT_PMCIN was configured to output 1.5 V.

2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See

each module's specification for its supply current.

3. MCG configured for FEI mode.

4. Radio is off.

5. Incremental current consumption from peripheral activity is not included.

6. MCG configured for BLPI mode.

7. DCDC configured in pulsed mode.

Table 15. Low power mode peripheral adders — typical value (Bypass Mode)

Symbol Description Temperature (°C) Unit

–40 25 50 70 85

IIREFSTEN4MHz 4 MHz internal reference clock (IRC)

adder. Measured by entering STOP or

VLPS mode with 4 MHz IRC enabled.

46 46 47 47 47 µA

IIREFSTEN32KHz 32 kHz internal reference clock (IRC)

adder. Measured by entering STOP mode

with the 32 kHz IRC enabled.

88 91 90 89 88 µA

IEREFSTEN32KHz External 32 kHz crystal clock adder by

means of the RTC bits. Measured by

entering all modes with the crystal

enabled.

VLLS1

VLLS2

VLLS3

LLS2

LLS3

1.4

1.6

2.7

1.8

2.6

1.3

1.5

1.9

1.4

1.7

1.6

1.9

2.9

1.7

2.8

2.4

4.2

7.7

4.1

7.6

4.1

7.7

15.2

μA

ICMP CMP peripheral adder measured by

placing the device in VLLS1 mode with

CMP enabled using the 6-bit DAC and a

single external input for compare. Includes

6-bit DAC power consumption.

22 19 20 21 21 µA

IRTC RTC peripheral adder measured by placing

the device in VLLS1 mode with external 32

kHz crystal enabled by means of the

RTC_CR[OSCE] bit and the RTC ALARM

set for 1 minute. Includes ERCLK32K (32

kHz external crystal) power consumption.

1.4 1.3 1.6 2.4 4.3 µA

ILPUART LPUART peripheral adder measured by

placing the device in STOP or VLPS mode

Table continues on the next page...

KW36A/35A/34A Electrical Characteristics

40 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 15. Low power mode peripheral adders — typical value (Bypass Mode) (continued)

Symbol Description Temperature (°C) Unit

–40 25 50 70 85

with selected clock source waiting for RX

data at 115200 baud rate. Includes

selected clock source power consumption.

MCGIRCLK (4 MHz internal reference

clock)

µA

ILPTMR LPTMR peripheral adder measured by

placing the device in VLLS1 mode with

LPTMR enabled using LPO.

100

ITPM TPM peripheral adder measured by

placing the device in STOP or VLPS mode

with selected clock source configured for

output compare generating 100 Hz clock

signal. No load is placed on the I/O

generating the clock signal. Includes

selected clock source and I/O switching

currents.

MCGIRCLK (4 MHz internal reference

clock)

µA

IBG Bandgap adder when BGEN bit is set and

device is placed in VLPx, LLS, or VLLSx

mode.

76 82 85 87 87 µA

IADC ADC peripheral adder combining the

measured values at VDD and VDDA by

placing the device in STOP or VLPS mode.

ADC is configured for low-power mode

using the internal clock and continuous

conversions.

331 327 327 327 328 µA

6.2.6 Diagram: Typical IDD_RUN operating behavior

The following data is measured from previous devices with same MCU core (Arm®

Cortex-M0+) under these conditions:

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFA

KW36A/35A/34A Electrical Characteristics

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NOTE

The results in the following graphs are obtained using the

device in Bypass mode.

Figure 7. Run mode supply current vs. core frequency

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Figure 8. VLPR mode current vs. core frequency

6.2.7 SoC Power Consumption

Full KW36A/35A/34A system-on-chip (SoC) power consumption is a function of the

many configurations possible for the MCU platform and its peripherals including the

2.4 GHz radio and the DC-DC converter. A few measured SoC configurations are as

follows:

Table 16. SoC Power Consumption with default LDO-HF

MCU State Flash State Radio State DC-DC State Typical

Average IC

current

Unit

STOP Doze Rx Buck (VDCDC_IN=3.6 V) 8.5 mA

STOP Doze Tx (at 0 dBm) Buck (VDCDC_IN=3.6 V) 7.8 mA

STOP Doze Tx (at +3.5

dBm)

Buck (VDCDC_IN=3.6 V) 9.2 mA

Table continues on the next page...

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Table 16. SoC Power Consumption with default LDO-HF (continued)

MCU State Flash State Radio State DC-DC State Typical

Average IC

current

Unit

RUN Enabled Rx Buck (VDCDC_IN=3.6 V) 10.4 mA

RUN Enabled Tx (at 0 dBm) Buck (VDCDC_IN=3.6 V) 9.9 mA

RUN Enabled Tx (at +3.5

dBm)

Buck (VDCDC_IN=3.6 V) 11.7 mA

STOP Doze Rx Disabled/Bypass 17.3 mA

STOP Doze Tx (at 0 dBm) Disabled/Bypass 15.9 mA

STOP Doze Tx (at +3.5

dBm)

Disabled/Bypass 18.3 mA

RUN Enabled Rx Disabled/Bypass 21.5 mA

RUN Enabled Tx (at 0 dBm) Disabled/Bypass 19.9 mA

RUN Enabled Tx (at +3.5

dBm)

Disabled/Bypass 22.4 mA

Table 17. SoC Power Consumption with LDO-HF bumped

MCU State Flash State Radio State DC-DC State Typical

Average IC

current

Unit

STOP Doze Rx (LDO-HF Bumped) Buck (VDCDC_IN=3.6 V) 8.7 mA

STOP Doze Tx (LDO-HF Bumped, +5 dBm) Buck (VDCDC_IN=3.6 V) 10.3 mA

RUN Enabled Rx (LDO-HF Bumped) Buck (VDCDC_IN=3.6 V) 11.3 mA

RUN Enabled Tx (LDO-HF Bumped, +5 dBm) Buck (VDCDC_IN=3.6 V) 13.1 mA

STOP Doze Rx (LDO-HF Bumped) Disabled/Bypass (3.6 V) 18.2 mA

STOP Doze Tx (LDO-HF Bumped, +5 dBm) Disabled/Bypass (3.6 V) 20.8 mA

RUN Enabled Rx (LDO-HF Bumped) Disabled/Bypass (3.6 V) 22.6 mA

RUN Enabled Tx (LDO-HF Bumped, +5 dBm) Disabled/Bypass (3.6 V) 26.6 mA

6.2.8 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.nxp.com

2. Perform a keyword search for “EMC design.”

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6.2.9 Capacitance attributes

Table 18. Capacitance attributes

Symbol Description Min. Max. Unit

CIN Input capacitance — 7 pF

6.3 Switching electrical specifications

6.3.1 Device clock specifications

Table 19. Device clock specifications

Symbol Description Min. Max. Unit

Normal run mode

fSYS System and core clock — 48 MHz

fBUS Bus clock — 24 MHz

fFLASH Flash clock — 24 MHz

fLPTMR LPTMR clock — 24 MHz

VLPR and VLPS modes1

fSYS System and core clock — 4 MHz

fBUS Bus clock — 1 MHz

fFLASH Flash clock — 1 MHz

fLPTMR LPTMR clock2— 24 MHz

fERCLK External reference clock — 16 MHz

fLPTMR_ERCLK LPTMR external reference clock — 16 MHz

fTPM TPM asynchronous clock — 8 MHz

fLPUART0 LPUART0 asynchronous clock — 12 MHz

1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing

specification for any other module. These same frequency limits apply to VLPS, whether VLPS entered from RUN or

from VLPR.

2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.

6.3.2 General switching specifications

These general-purpose specifications apply to all signals configured for GPIO,

LPUART, CAN (for KW36A only), CMT and I2C signals.

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Table 20. General switching specifications

Description Min. Max. Unit Notes

GPIO pin interrupt pulse width (digital glitch filter disabled)

— Synchronous path

1.5 — Bus clock cycles 1, 2

NMI_b pin interrupt pulse width (analog filter enabled) —

Asynchronous path

200 — ns 3

GPIO pin interrupt pulse width (digital glitch filter disabled,

analog filter disabled) — Asynchronous path

20 — ns 3

External RESET_b input pulse width (digital glitch filter

disabled)

100 — ns

Port rise and fall time(high drive strength)

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

—

4, 5

Port rise and fall time(low drive strength)

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7 V

• 2.7 ≤ VDD ≤ 3.6 V

—

6, 7

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes.

2. The greater of synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized.

4. PTB0, PTB1, PTC0, PTC1, PTC2, PTC3, PTC6, PTC7, PTC17, PTC18.

5. 75 pF load.

6. Ports A, B, and C.

7. 25 pF load.

6.4 Thermal specifications

6.4.1 Thermal operating requirements

Table 21. Thermal operating requirements

Symbol Description Min. Max. Unit Notes

TJDie junction temperature –40 125 °C

TAAmbient temperature –40 105 °C 1

1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to

determine TJ is: TJ = TA + RθJA × chip power dissipation.

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6.4.2 Thermal attributes

Table 22. Thermal attributes

Board type Symbol Description 48-pin

LQFN

40-pin

"Wettable"

HVQFN

48-pin

"Wettable"

HVQFN

Unit Notes

Four-layer (2s2p) RθJA Thermal resistance, junction

to ambient (natural

convection)

48.3 19.2 21.6 °C/W 1, 2

—ΨJT Thermal characterization

parameter, junction to

package top (natural

convection)

0.5 0.1 0.2 °C/W 1, 3

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

construction.

2. Determined according to JEDEC Standard JESD51-2A.

3. Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2A.

The thermal characterization parameter (ΨJT) is used to determine the junction

temperature with a measurement of the temperature at the top of the package case

using the following equation:

TJ = TT + ΨJT x chip power dissipation

where TT is the thermocouple temperature at the top of the package.

6.5 Peripheral operating requirements and behaviors

6.5.1 Core modules

6.5.1.1 SWD electricals

Table 23. SWD full voltage range electricals

Symbol Description Min. Max. Unit

Operating voltage 1.71 3.6 V

J1 SWD_CLK frequency of operation

• Serial wire debug

MHz

J2 SWD_CLK cycle period 1/J1 — ns

Table continues on the next page...

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Table 23. SWD full voltage range electricals (continued)

Symbol Description Min. Max. Unit

J3 SWD_CLK clock pulse width

• Serial wire debug

—

J4 SWD_CLK rise and fall times — 3 ns

J9 SWD_DIO input data setup time to SWD_CLK rise 10 — ns

J10 SWD_DIO input data hold time after SWD_CLK rise 0 — ns

J11 SWD_CLK high to SWD_DIO data valid — 32 ns

J12 SWD_CLK high to SWD_DIO high-Z 5 — ns

J3 J3

J4 J4

SWD_CLK (input)

Figure 9. Serial wire clock input timing

J11

J12

J11

J9 J10

Input data valid

Output data valid

SWD_CLK

SWD_DIO

Figure 10. Serial wire data timing

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6.5.2 System modules

There are no specifications necessary for the device's system modules.

6.5.3 Clock modules

6.5.3.1 MCG specifications

Table 24. MCG specifications

Symbol Description Min. Typ. Max. Unit Notes

fints_ft Internal reference frequency (slow clock) —

factory trimmed at nominal VDD and 25 °C

— 32.768 — kHz

fints_t Internal reference frequency (slow clock) —

user trimmed

31.25 — 39.0625 kHz

Δfdco_res_t Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using C3[SCTRIM] and C4[SCFTRIM]

— ± 0.3 ± 0.6 %fdco 1

Δfdco_t Total deviation of trimmed average DCO output

frequency over voltage and temperature

— +0.5/–0.7 ± 3 %fdco 1, 2

Δfdco_t Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70 °C

— ± 0.4 ± 1.5 %fdco 1, 2

fintf_ft Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25 °C

— 4 — MHz

Δfintf_ft Frequency deviation of internal reference clock

(fast clock) over temperature and voltage —

factory trimmed at nominal VDD and 25 °C

— +1/–2 ± 3 %fintf_ft 2

fintf_t Internal reference frequency (fast clock) —

user trimmed at nominal VDD and 25 °C

3 — 5 MHz

floc_low Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

fints_t

— — kHz

floc_high Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

fints_t

— — kHz

FLL

ffll_ref FLL reference frequency range 31.25 — 39.0625 kHz

fdco DCO output

frequency range

Low range (DRS = 00)

640 × ffll_ref

20 20.97 25 MHz 3, 4

Mid range (DRS = 01)

1280 × ffll_ref

40 41.94 48 MHz

fdco_t_DMX3

DCO output

frequency

Low range (DRS = 00)

732 × ffll_ref

— 23.99 — MHz 5, 6

Mid range (DRS = 01)

1464 × ffll_ref

— 47.97 — MHz

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Table 24. MCG specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

Jcyc_fll FLL period jitter

• fVCO = 48 MHz

— 180 — ps 7

tfll_acquire FLL target frequency acquisition time — — 1 ms 8

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.

4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation

(Δfdco_t) over voltage and temperature must be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification is based on standard deviation (RMS) of period or frequency.

8. This specification applies to any time the following changes: FLL reference source or reference divider, trim value,

DMX32 bit, DRS bits, or FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is used

as the reference, this specification assumes it is already running.

6.5.3.2 Reference Oscillator Specification

The KW36A/35A/34A has been designed to meet targeted standard specifications for

frequency error over the life of the part, which includes the temperature, mechanical

and aging effects.

The table below lists the recommended crystal specifications. Note that these are

recommendations only and deviation may be allowed. However, deviations may result

in degraded RF performance or possibly a failure to meet RF protocol certification

standards. Designers must ensure that the crystal(s) they use meet the requirements of

their application.

Table 25. Recommended Crystal and Oscillator Specification

Symbol Description F0 = 32.0 MHz F0 = 26.0 MHz Unit Notes

Min Typ Max Min Typ Max

TAOperating

Temperature

–40 — 105 –40 — 105 °C 1

Crystal initial

frequency

tolerance

–10 — 10 –10 — 10 ppm 2,3

Crystal frequency

stability and aging

–25 — 25 –25 — 24 ppm 2,4

Oscillator variation –12 — 15 –12 — 16 ppm 5

Total reference

oscillator tolerance

–50 — 50 –50 — 50 ppm 6

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Table 25. Recommended Crystal and Oscillator Specification (continued)

Symbol Description F0 = 32.0 MHz F0 = 26.0 MHz Unit Notes

Min Typ Max Min Typ Max

for Bluetooth LE

applications

CLLoad capacitance 7 10 13 7 10 13 pF 2, 7

C0Shunt capacitance 0.469 0.67 0.871 0.42 0.6 0.78 pF 2,7

Cm1 Motional

capacitance

1.435 2.05 2.665 1.435 2.05 2.665 fF 2,7

Lm1 Motional

inductance

8.47 12.1 15.73 12.81 18.3 23.79 mH 2,7

Rm1 Motional

resistance

— 25 50 — 35 50 Ohms 2

ESR Equivalent series

resistance

— — 60 — — 60 Ohms 2,8

PdMaximum crystal

drive

— 10 200 — 10 200 uW 2

TSTrim sensitivity 6.30 9.00 11.70 6.39 9.12 11.86 ppm/pF 2,7

TOSC Oscillator Startup

Time

— 500 — — 500 — μs 9

1. Full temperature range of this device. A reduced range can be chosen to meet application needs.

2. Recommended crystal specification.

3. Measured at 25 °C.

4. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over

desired lifetime of system.

5. Variation due to temperature, process, and aging of MCU.

6. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB

manufacturing variation must not exceed this value.

7. Typical is target. 30% tolerances shown.

8. ESR = Rm1 * (1 + [C0/CL])^2.

9. Time from oscillator enable to clock ready. Dependent on the complete hardware configuration of the oscillator.

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Figure 11. Crystal Electrical Model

6.5.3.3 32 kHz Oscillator Frequency Specifications

Table 26. 32 kHz Crystal and Oscillator Specifications

Symbol Description Min. Typ. Max. Unit Notes

fosc_lo Crystal

frequency

— 32.768 — kHz

TAOperating

temperature

–40 — 105 °C 1

Total crystal

frequency

tolerance

–500 — 500 ppm 2,3

CLLoad

capacitance

— 12.5 — pF 2

ESR Equivalent

series

resistance

— — 80 kOhms 2

tstart Crystal start-up

time

— 1000 — ms 4

fec_extal32 External input

clock frequency

— 32.768 — kHz 5

vec_extal32 External input

clock amplitude

0.7 — VDD V6

1. Full temperature range of this device. A reduced range can be chosen to meet application needs.

2. Recommended crystal specification.

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3. Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.

4. Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.

5. External oscillator connected to EXTAL32K. XTAL32K must be unconnected.

6. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the

applied clock must be within the range of VSS to VDD.

6.5.4 Memories and memory interfaces

6.5.4.1 Flash (FTFE) electrical specifications

This section describes the electrical characteristics of the FTFE module.

6.5.4.1.1 Flash timing specifications — commands

Table 27. Flash command timing specifications

Symbol Description1Min. Typ. Max. Unit Notes

trd1blk256k

Read 1s Block execution time

• 256 KB program/data flash

—

trd1sec2k Read 1s Section execution time (2 KB flash) — — 75 μs

tpgmchk Program Check execution time — — 95 μs

trdrsrc Read Resource execution time — — 40 μs

tpgm8 Program Phrase execution time — 90 225 μs

tersblk256k

Erase Flash Block execution time

• 256 KB program/data flash

—

125

2125

tersscr Erase Flash Sector execution time — 12 130 ms 2

tpgmsec2k Program Section execution time (2 KB flash) — 10 — ms

trd1allx

trd1alln

Read 1s All Blocks execution time

• FlexNVM devices

• Program flash only devices

—

3.5

trdonce Read Once execution time — — 30 μs

tpgmonce Program Once execution time — 90 — μs

tersall Erase All Blocks execution time — 262 4380 ms 2

tvfykey Verify Backdoor Access Key execution time — — 35 μs

tersallu Erase All Blocks Unsecure execution time — 262 4380 ms 2

tswapx01

tswapx02

tswapx04

tswapx08

Swap Control execution time

• control code 0x01

• control code 0x02

• control code 0x04

—

280

100

—

235

μs

Table continues on the next page...

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Table 27. Flash command timing specifications (continued)

Symbol Description1Min. Typ. Max. Unit Notes

tswapx10 • control code 0x08

• control code 0x10

— 100 235 μs

tpgmpart32k

tpgmpart256k

Program Partition for EEPROM execution time

• 32 KB EEPROM backup

• 256 KB EEPROM backup

—

252

262

—

tsetramff

tsetram32k

tsetram256k

Set FlexRAM Function execution time:

• Control Code 0xFF

• 32 KB EEPROM backup

• 256 KB EEPROM backup

—

115

0.8

4.5

—

1.2

6.1

μs

teewr8b32k

teewr8b256k

Byte-write to FlexRAM execution time:

• 32 KB EEPROM backup

• 256 KB EEPROM backup

—

385

1015

1700

3800

μs

teewr16b32k

teewr16b256k

16-bit write to FlexRAM execution time:

• 32 KB EEPROM backup

• 256 KB EEPROM backup

—

385

1015

1700

3800

μs

teewr32bers 32-bit write to erased FlexRAM location

execution time

— 360 2000 μs 3

teewr32b32k

teewr32b256k

32-bit write to FlexRAM execution time:

• 32 KB EEPROM backup

• 256 KB EEPROM backup

—

630

1890

2000

4100

μs

1. All command times assume 25 MHz or greater flash clock frequency (for synchronization time between internal/external

clocks).

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. First time EERAM writes after a Reset or SETRAM command may incur additional overhead for EEE cleanup, resulting

in up to 2x the times shown.

NOTE

Under certain circumstances maximum times for writes to

FlexRAM may be exceeded. In this case the user or

application may wait, or assert reset to the FTFE module to

stop the operation.

6.5.4.1.2 Reliability specifications

Table 28. NVM reliability specifications

Symbol Description Min. Typ. Max. Unit Notes

Program Flash

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Table 28. NVM reliability specifications (continued)

Symbol Description Min. Typ. Max. Unit Notes

tnvmret1k Data retention after up to 1 K cycles 20 — — years 1

nnvmcyc Cycling endurance 1 K — — cycles 2

FlexRAM as Emulated EEPROM

tnvmretee Data retention 5 — — years 1, 3

nnvmwree16

nnvmwree256

Write endurance

• EEPROM backup to FlexRAM used ratio = 16

• EEPROM backup to FlexRAM used ratio =

256

100 K

1.6 M

—

writes

4, 5, 6

1. Data retention period per block begins upon initial user factory programming or after each subsequent erase.

2. Program and Erase are supported across product temperature specification. Cycling endurance is per flash sector.

3. Background maintenance operations during normal FlexRAM usage extend effective data retention life beyond 5

years.

4. FlexMemory write endurance specified for 16-bit and/or 32-bit writes to FlexRAM and is supported across product

temperature specification. Greater write endurance may be achieved with larger ratios of EEPROM backup to

FlexRAM.

5. For usage of any EEE driver other than the FlexMemory feature, the endurance specification falls back to the Data

Flash endurance value of 1 K.

6. FlexMemory calculator tool is available on the NXP web site for help in estimating the maximum write endurance

achievable at specific EEPROM/FlexRAM ratios. The "In Spec" portions of the online calculator refer to the NVM

reliability specifications section of the data sheet. This calculator only applies to the Kinetis FlexMemory feature.

6.5.4.1.3 Write endurance to FlexRAM for EEPROM

When the FlexNVM partition code is not set to full data flash, the EEPROM data set

size can be set to any of several non-zero values.

The bytes not assigned to data flash via the FlexNVM partition code are used by the

FTFE to obtain an effective endurance increase for the EEPROM data. The built-in

EEPROM record management system raises the number of program/erase cycles that

can be attained prior to device wear-out by cycling the EEPROM data through a larger

EEPROM NVM storage space.

While different partitions of the FlexNVM are available, the intention is that a single

choice for the FlexNVM partition code and EEPROM data set size is used throughout

the entire lifetime of a given application.

6.5.5 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

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6.5.6 Analog

6.5.6.1 ADC electrical specifications

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications. The following specification is defined with the DC-DC converter

operating in Bypass mode.

6.5.6.1.1 16-bit ADC operating conditions

Table 29. 16-bit ADC operating conditions

Symbol Description Conditions Min. Typ.1Max. Unit Notes

VDDA Supply voltage Absolute 1.71 — 3.6 V

ΔVDDA Supply voltage Delta to VDD (VDD – VDDA) –100 0 +100 mV 2

ΔVSSA Ground voltage Delta to VSS (VSS – VSSA) –100 0 +100 mV 2

VREFH ADC reference

voltage high

1.13 VDDA VDDA V3

VREFL ADC reference

voltage low

VSSA VSSA VSSA V3

VADIN Input voltage • 16-bit differential mode

• All other modes

VSSA

—

31/32 ×

VREFH

CADIN Input

capacitance

• 16-bit mode

• 8-bit / 10-bit / 12-bit

modes

—

RADIN Input series

resistance

— 2 5 kΩ

RAS Analog source

resistance

(external)

13-bit / 12-bit modes

fADCK < 4 MHz

—

kΩ

fADCK ADC conversion

clock frequency

≤ 13-bit mode 1.0 — 18.0 MHz 5

fADCK ADC conversion

clock frequency

16-bit mode 2.0 — 12.0 MHz 5

Crate ADC conversion

rate

≤ 13-bit modes

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

20.000

—

818.330

kS/s

Crate ADC conversion

rate

16-bit mode

No ADC hardware averaging

37.037

—

461.467

kS/s

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Table 29. 16-bit ADC operating conditions

Symbol Description Conditions Min. Typ.1Max. Unit Notes

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied

to VSSA.

4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet are derived from a system that had < 8 Ω analog source resistance. The

RAS/CAS time constant should be kept to < 1 ns.

5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

RAS

VAS CAS

ZAS

VADIN

ZADIN

RADIN

CADIN

Pad

leakage

INPUT PIN

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

ADC SAR

ENGINE

Figure 12. ADC input impedance equivalency diagram

6.5.6.1.2 16-bit ADC electrical characteristics

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Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA)

Symbol Description Conditions1Min. Typ.2Max. Unit Notes

IDDA_ADC Supply current 0.215 — 1.7 mA 3

fADACK

ADC asynchronous

clock source

• ADLPC=1, ADHSC=0

• ADLPC=1, ADHSC=1

• ADLPC=0, ADHSC=0

• ADLPC=0, ADHSC=1

1.2

2.4

3.0

4.4

2.4

4.0

5.2

6.2

3.9

6.1

7.3

9.5

MHz tADACK =

1/fADACK

Sample Time See Reference Manual chapter for sample times

TUE Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

±4

±1.4

±6.8

±2.1

LSB45

DNL Differential non-

linearity

• 12-bit mode; Buck

Mode6

• 12-bit mode; Bypass

Mode

—

±0.7

±0.5

–1.1 to +1.9

LSB45

INL Integral non-

linearity

• 12-bit mode; Buck

Mode6

• 12-bit mode; Bypass

Mode

—

±1.0

±0.6

–2.7 to +1.9

LSB45

EFS Full-scale error • 12-bit modes

• <12-bit modes

—

–4

–1.4

–5.4

–1.8

LSB4VADIN =

VDDA5

EQQuantization error • 16-bit modes

• ≤13-bit modes

—

–1 to 0

—

±0.5

LSB4

ENOB Effective number of

bits

16-bit differential mode; Buck

Mode6

• Avg = 32

• Avg = 4

16-bit single-ended mode;

Buck Mode6

• Avg = 32

• Avg = 4

16-bit differential mode;

Bypass Mode

• Avg = 32

• Avg = 4

16-bit single-ended mode;

Bypass Mode

• Avg = 32

• Avg = 4

11.25

9.5

12.5

11.25

12.75

11.75

11.5

10.5

11.75

10.5

—

bits

SINAD Signal-to-noise plus

distortion

See ENOB 6.02 × ENOB + 1.76 dB

THD Total harmonic

distortion

16-bit differential mode; Buck

Mode68

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Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)

Symbol Description Conditions1Min. Typ.2Max. Unit Notes

• Avg = 32

16-bit single-ended mode;

Buck Mode6

• Avg = 32

16-bit differential mode;

Bypass Mode

• Avg = 32

16-bit single-ended mode;

Bypass Mode

• Avg = 32

—

–90

–88

–89

–87

—

SINAD Signal-to-noise plus

distortion

See ENOB 6.02 × ENOB + 1.76 dB

SFDR Spurious free

dynamic range

distortion

16-bit differential mode; Buck

Mode6

• Avg = 32

16-bit single-ended mode;

Buck Mode6

• Avg = 32

16-bit differential mode;

Bypass Mode

• Avg = 32

16-bit single-ended mode;

Bypass Mode

• Avg = 32

—

EIL Input leakage error IIn × RAS mV IIn =

leakage

current

(see

Voltage

and

current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.67 1.74 1.81 mV/°

VTEMP25 Temp sensor

voltage

25 °C 706 716 726 mV 9

1. All accuracy numbers assume that the ADC is calibrated with VREFH = VDDA.

2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

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3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low-

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

4. 1 LSB = (VREFH - VREFL)/2N.

5. ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).

6. VREFH = Output of Voltage Reference(VREF).

7. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

9. ADC conversion clock < 3 MHz.

6.5.6.2 Voltage reference electrical specifications

Table 31. VREF full-range operating requirements

Symbol Description Min. Max. Unit Notes

VDDA Supply voltage 1.71 3.6 V

TATemperature –40 to 105 °C

CLOutput load capacitance 100 nF 1, 2

1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external

reference.

2. The load capacitance should not exceed +/–25% of the nominal specified CL value over the operating temperature range

of the device.

Table 32. VREF full-range operating behaviors

Symbol Description Min. Typ. Max. Unit Notes

Vout Voltage reference output with factory trim at

nominal VDDA and temperature=25 °C

1.190 1.1950 1.2 V 1

Vout Voltage reference output with user trim at

nominal VDDA and temperature=25 °C

1.1945 1.1950 1.1955 V 1

Vstep Voltage reference trim step — 0.5 — mV 1

Vtdrift Temperature drift (Vmax -Vmin across the full

temperature range)

— — 20 mV 1

Ibg Bandgap only current — — 80 µA

Ilp Low-power buffer current — — 360 uA 1

Ihp High-power buffer current — — 1 mA 1

ΔVLOAD Load regulation

• current = ± 1.0 mA

—

200

—

µV 1, 2

Tstup Buffer startup time — — 100 µs

Tchop_osc_st

Internal bandgap start-up delay with chop

oscillator enabled

— — 35 ms

Vvdrift Voltage drift (Vmax –Vmin across the full voltage

range)

— 2 — mV 1

1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.

2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load

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Table 33. VREF limited-range operating requirements

Symbol Description Min. Max. Unit Notes

TATemperature 0 70 °C

Table 34. VREF limited-range operating behaviors

Symbol Description Min. Max. Unit Notes

Vtdrift Temperature drift (Vmax –Vmin across the limited

temperature range)

— 15 mV

6.5.6.3 CMP and 6-bit DAC electrical specifications

Table 35. Comparator and 6-bit DAC electrical specifications

Symbol Description Min. Typ. Max. Unit

VDD Supply voltage 1.71 — 3.6 V

IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA

IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA

VAIN Analog input voltage VSS – 0.3 — VDD V

VAIO Analog input offset voltage — — 20 mV

VHAnalog comparator hysteresis1

• CR0[HYSTCTR] = 00

• CR0[HYSTCTR] = 01

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

—

VCMPOh Output high VDD – 0.5 — — V

VCMPOl Output low — — 0.5 V

tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns

tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 80 250 600 ns

Analog comparator initialization delay2— — 40 μs

IDAC6b 6-bit DAC current adder (enabled) — 7 — μA

INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3

DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB

1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = Vreference/64

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HYSTCTR

Setting

0.1

Vin level (V)

CMP Hystereris (V)

3.12.82.5

2.2

1.91.61.3

0.70.4

0.05

0.01

0.02

0.03

0.08

0.07

0.06

0.04

Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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HYSTCTR

Setting

0.1 3.12.82.5

2.2

1.91.61.3

0.70.4

0.1

0.02

0.04

0.06

0.18

0.14

0.12

0.08

0.16

Vin level (V)

CMP Hysteresis (V)

Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.5.7 Timers

See General switching specifications.

6.5.8 Communication interfaces

6.5.8.1 CAN switching specifications

See General switching specifications.

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6.5.8.2 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. See the

DSPI chapter of the Reference Manual for information on the modified transfer formats

used for communicating with slower peripheral devices.

Table 36. Master mode DSPI timing (limited voltage range)

Num Description Min. Max. Unit Notes

Operating voltage 2.7 3.6 V

Frequency of operation — 12 MHz

DS1 DSPI_SCK output cycle time 2 x tBUS — ns

DS2 DSPI_SCK output high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns

DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −

— ns 1

DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −

— ns 2

DS5 DSPI_SCK to DSPI_SOUT valid — 8.5 ns

DS6 DSPI_SCK to DSPI_SOUT invalid –2 — ns

DS7 DSPI_SIN to DSPI_SCK input setup 16.2 — ns

DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns

1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DS3 DS4

DS1

DS2

DS7 DS8

First data Last data

DS5

First data Data Last data

DS6

Data

SPI_PCSn

SPI_SCK

(CPOL=0)

SPI_SIN

SPI_SOUT

Figure 15. DSPI classic SPI timing — master mode

Table 37. Slave mode DSPI timing (limited voltage range)

Num Description Min. Max. Unit

Operating voltage 2.7 3.6 V

Frequency of operation 6 MHz

Table continues on the next page...

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Table 37. Slave mode DSPI timing (limited voltage range) (continued)

Num Description Min. Max. Unit

DS9 DSPI_SCK input cycle time 4 x tBUS — ns

DS10 DSPI_SCK input high/low time (tSCK/2) − 2 (tSCK/2) + 2 ns

DS11 DSPI_SCK to DSPI_SOUT valid — 21.4 ns

DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns

DS13 DSPI_SIN to DSPI_SCK input setup 2.6 — ns

DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns

DS15 DSPI_SS active to DSPI_SOUT driven — 14 ns

DS16 DSPI_SS inactive to DSPI_SOUT not driven — 14 ns

First data Last data

First data Data Last data

Data

DS15

DS10 DS9

DS16

DS11

DS12

DS14

DS13

SPI_SS

SPI_SCK

(POL=0)

SPI_SOUT

SPI_SIN

Figure 16. DSPI classic SPI timing — slave mode

6.5.8.3 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. See

the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 38. Master mode DSPI timing (full voltage range)

Num Description Min. Max. Unit Notes

Operating voltage 1.71 3.6 V 1

Frequency of operation — 12 MHz

DS1 DSPI_SCK output cycle time 2 x tBUS — ns

DS2 DSPI_SCK output high/low time (tSCK/2) – 4 (tSCK/2) + 4 ns

Table continues on the next page...

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Table 38. Master mode DSPI timing (full voltage range) (continued)

Num Description Min. Max. Unit Notes

DS3 DSPI_PCSn valid to DSPI_SCK delay (tBUS x 2) −

— ns 2

DS4 DSPI_SCK to DSPI_PCSn invalid delay (tBUS x 2) −

— ns 3

DS5 DSPI_SCK to DSPI_SOUT valid — 10 ns

DS6 DSPI_SCK to DSPI_SOUT invalid –1.2 — ns

DS7 DSPI_SIN to DSPI_SCK input setup 23.3 — ns

DS8 DSPI_SCK to DSPI_SIN input hold 0 — ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DS3 DS4

DS1

DS2

DS7 DS8

First data Last data

DS5

First data Data Last data

DS6

Data

SPI_PCSn

SPI_SCK

(CPOL=0)

SPI_SIN

SPI_SOUT

Figure 17. DSPI classic SPI timing — master mode

Table 39. Slave mode DSPI timing (full voltage range)

Num Description Min. Max. Unit

Operating voltage 1.71 3.6 V

Frequency of operation — 6 MHz

DS9 DSPI_SCK input cycle time 4 x tBUS — ns

DS10 DSPI_SCK input high/low time (tSCK/2) – 4 (tSCK/2) + 4 ns

DS11 DSPI_SCK to DSPI_SOUT valid — 29.1 ns

DS12 DSPI_SCK to DSPI_SOUT invalid 0 — ns

DS13 DSPI_SIN to DSPI_SCK input setup 3.2 — ns

DS14 DSPI_SCK to DSPI_SIN input hold 7.0 — ns

DS15 DSPI_SS active to DSPI_SOUT driven — 25 ns

DS16 DSPI_SS inactive to DSPI_SOUT not driven — 25 ns

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NXP Semiconductors

First data Last data

First data Data Last data

Data

DS15

DS10 DS9

DS16

DS11

DS12

DS14

DS13

SPI_SS

SPI_SCK

(POL=0)

SPI_SOUT

SPI_SIN

Figure 18. DSPI classic SPI timing — slave mode

6.5.8.4 Inter-Integrated Circuit Interface (I2C) timing

Table 40. I 2C timing

Characteristic Symbol Standard Mode Fast Mode Unit

Minimum Maximum Minimum Maximum

SCL Clock Frequency fSCL 0 100 0 400 kHz

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated.

tHD; STA 4 — 0.6 — µs

LOW period of the SCL clock tLOW 4.7 — 1.3 — µs

HIGH period of the SCL clock tHIGH 4 — 0.6 — µs

Set-up time for a repeated START

condition

tSU; STA 4.7 — 0.6 — µs

Data hold time for I2C bus devices tHD; DAT 013.452030.91µs

Data set-up time tSU; DAT 2504— 1002, 5— ns

Rise time of SDA and SCL signals tr— 1000 20 +0.1Cb5,

6300 ns

Fall time of SDA and SCL signals tf— 300 20 +0.1Cb5,

6300 ns

Set-up time for STOP condition tSU; STO 4 — 0.6 — µs

Bus free time between STOP and

START condition

tBUF 4.7 — 1.3 — µs

Pulse width of spikes that must be

suppressed by the input filter

tSP N/A N/A 0 50 ns

1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves

acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and

SCL lines.

2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.

3. Input signal Slew = 10 ns and Output Load = 50 pF.

4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.

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5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns

must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such

a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;

DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.

6. Cb = total capacitance of the one bus line in pF.



SDA

HD; STA tHD; DAT

tLOW

tSU; DAT

tHIGH

tSU; STA SR PS

tHD; STA tSP

tSU; STO

tBUF

tftr

SCL

Figure 19. Timing definition for fast and standard mode devices on the I2C bus

6.5.8.5 LPUART

See General switching specifications.

6.5.9 Human-machine interfaces (HMI)

6.5.9.1 GPIO

The maximum input voltage on PTC0/1/2/3 is VDD+0.3V. For rest of the GPIO

specification, see General switching specifications.

6.6 DC-DC Converter Operating Requirements

Table 41. DC-DC Converter operating conditions

Characteristic Symbol Min Typ Max Unit

Bypass Mode Supply Voltage (RF and Analog) VDDRF1,

VDDRF2,

VDDRF3, VDD_1P5

1.425 — 3.6 Vdc

Bypass Mode Supply Voltage (Digital) VDDX, VDCDC_IN,

VDDA

1.71 — 3.6 Vdc

Buck Mode Supply Voltage 1, 2VDCDC_IN 2.1 — 3.6 Vdc

DC-DC Inductor

Value — 10 — μH

Table continues on the next page...

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Table 41. DC-DC Converter operating conditions (continued)

Characteristic Symbol Min Typ Max Unit

ESR — <0.2 <0.5 Ohms

DC-DC internal oscillator DCDCInt_Osc — 26 — MHz

1. In Buck mode, DC-DC converter needs 2.1 V minimum to start, the supply can drop to 1.8 V after DC-DC converter

settles.

2. In Buck mode, DC-DC converter generates 1.8 V at VDD_1P8OUT and 1.5 V at VDD_1P5OUT_PMCIN pins.

VDD_1P8OUT should supply to VDD1, VDD2 and VDDA. VDD_1P5OUT_PMCIN should supply to VDD_RF1 and

VDD_RF2. VDD_RF3 can be either supplied by 1.5 V or 1.8 V.

Table 42. DC-DC Converter Specifications

Characteristics Conditions Symbol Min Typ Max Unit

DC-DC Converter Output

Power (total power output of

1p8V and 1p5V)

VDCDC_IN above 2.7 V Pdcdc_out1 — — 1951mW

VDCDC_IN below 2.7 V Pdcdc_out2 — — 1401mW

Switching Frequency2DCDC_FREQ — DC-DC

reference

frequency

divided by 16

— MHz

Half FET Threshold I_half_FET — 5 — mA

Double FET Threshold I_double_FET — 40 — mA

Buck Mode

DC-DC Conversion Efficiency DCDC_EFF_buck — 90% — —

1.8 V Output Voltage

VDD_1P8_buck 1.71 — min(VDCD

C_IN_buc

k, 3.5)4, 5

Vdc

1.8 V Output Current6, 7

VDD_1P8 = 3.0 V

1.5 V <= VDC_1P5

<= 1.7 V

VDCDC_IN=3.1 V

IDD_1P8_buck1 — — 39 mA

VDD_1P8 = 2.65 V

1.5 V <= VDC_1P5

<= 1.7 V

VDCDC_IN=2.7 V

IDD_1P8_buck2 — — 45 mA

VDD_1P8 = 1.8 V

1.5 V <= VDC_1P5

<= 1.7 V

VDCDC_IN=2.1 V

IDD_1P8_buck3 — — 35 mA

1.5 V Output Voltage Consumed by Radio

for Pout<=+3.5 dBm

VDD_1P5_buck 1.45 1.581.8 Vdc

1.5 V Output Voltage Consumed by Radio

for Pout=+5 dBm

VDD_1P5_buck 1.55 1.62591.8 Vdc

Table continues on the next page...

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Table 42. DC-DC Converter Specifications (continued)

Characteristics Conditions Symbol Min Typ Max Unit

1.5 V Output Current6, 10 IDD_1P5_buck — — 45 mA

DC-DC Transition Operating

Behavior

LSS➔Run t_DCDCbuck_LSS➔

RUN

— 50 — μs

DC-DC Turn on Time TDCDC_ON — 2.211 — ms

DC-DC Settling Time for

increasing voltage

TDCDC_SETTLE_buck — 3.11 — ms/V

DC-DC Settling Time for

decreasing voltage

C = capacitance

attached to the DC-

DC V1P8 output rail.

V1 = the initial output

voltage of the DC-DC

V2 = the final output

voltage of the DC-DC

I2 = the load on the

DC-DC output

expressed in

Amperes.

TDCDC_SETTLE_buck — (C*(V1–

V2)/I2

— s

VDD_1P8 ripple Typical ripple based

on NXP

recommended

hardware

configuration and

typical loading (MCU

only; no extra loads

placed on DC-DC

outputs)

VDD_1P8ripple — 30 — mV

VDD_1P5 ripple Typical ripple based

on NXP

recommended

hardware

configuration and

typical loading (MCU

only; no extra loads

placed on DC-DC

outputs)

VDD_1P5ripple — 30 — mV

1. This is the steady state DC output power. Excessive transient current load from external device causes 1p8V and 1P5

output voltage unregulated temporary.

2. This is the frequency that is observed at LN and LP pins.

3. DC-DC reference frequency derives from the RF oscillator or the DC-DC internal oscillator.

4. The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.

5. In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For

example, if VDCDC_IN = 2.1 V, maximum VDD_1P8 is 2.05 V. If VDCDC_IN = 3.6 V, maximum VDD_1P8 is 3.5 V.

6. The output current specification in buck mode represents the maximum current the DC-DC converter can deliver. The

KW36A/35A/34A radio and MCU blocks current consumption is not excluded. The maximum output power of the DC-DC

converter is 140 mW when VDCDC_IN is below 2.7 V and 195 mW when VDCDC_IN is above 2.7 V. The available supply

current for external device depends on the energy consumed by the internal peripherals in KW36A/35A/34A.

7. When using DC-DC in low-power mode (pulsed mode), current load must be less than 1 mA.

8. User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case

minimum of 1.45 V is available as VDD_1P5_buck. VDD_1P5 must not be programmed higher than VDD_1P8.

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9. User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case

minimum of 1.55 V is available as VDD_1P5_buck. VDD_1P5 must not be programmed higher than VDD_1P8.

10. 1.5 V is intended to supply power to KW36A/35A/34A. It is not designed to supply power to an external device.

11. Turn on time is measured from the application of power (to DCDC_IN) till the DCDC_REG0[DCDC_STS_DC_OK] bit

is set. Code execution may begin before the DCDC_REG0[DCDC_STS_DC_OK] bit is set. The full device

specification is not guaranteed until the bit sets.

6.7 Ratings

6.7.1 Thermal handling ratings

Table 43. Thermal handling ratings

Symbol Description Min. Max. Unit Notes

TSTG Storage temperature –55 150 °C 1

TSDR Solder temperature, lead-free — 260 °C 2

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.7.2 Moisture handling ratings

Table 44. Moisture handling ratings

Symbol Description Min. Max. Unit Notes

MSL Moisture sensitivity level — 3 — 1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.7.3 ESD handling ratings

Table 45. ESD handling ratings

Symbol Description Min. Max. Unit Notes

VHBM Electrostatic discharge voltage, human body model –2000 +2000 V 1

VCDM Electrostatic discharge voltage, charged-device model 2

All pins except the corner pins –500 500 V

Corner pins only –750 750 V

ILAT Latch-up current at ambient temperature of 105 °C –100 +100 mA 3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

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2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

6.7.4 Voltage and current operating ratings

Table 46. Voltage and current operating ratings

Symbol Description Min. Max. Unit

VDD Digital supply voltage –0.3 3.8 V

IDD Digital supply current — 120 mA

VIO IO pin input voltage –0.3 VDD + 0.3 V

IDInstantaneous maximum current single pin limit (applies to

all port pins)

–25 25 mA

VDDA Analog supply voltage VDD – 0.3 VDD + 0.3 V

VIO_DCDC IO pins in the DC-DC voltage domain (DCDC_CFG and

PSWITCH)

GND VDCDC V

7 Pin Diagrams and Pin Assignments

7.1 KW36A Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control and Interrupt Module

is used to select the functionality for each GPIO pin. ALT0 is reserved for analog

functions on some GPIO pins. ALT1 – ALT9 are assigned to the available digital

functions on each GPIO pin. GPIO pins with a default of “disabled” are high impedance

after reset – their input and output buffers are disabled.

"Wett

able"

HVQ

"Wett

able"

HVQ

LQF

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

— 4 4 PTA16 DISABLED PTA16/

LLWU_P4

SPI1_

SOUT

LPUART1_

RTS_b

TPM0_

CH0

— 5 5 PTA17 DISABLED PTA17/

LLWU_P5

SPI1_SIN LPUART1_

CAN0_TX TPM_

CLKIN1

— 6 6 PTA18 DISABLED PTA18/

LLWU_P6

SPI1_SCK LPUART1_

CAN0_RX TPM2_

CH0

Pin Diagrams and Pin Assignments

72 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

"Wett

able"

HVQ

"Wett

able"

HVQ

LQF

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

— 7 7 PTA19 ADC0_SE5 ADC0_SE5 PTA19/

LLWU_P7

SPI1_

PCS0

LPUART1_

CTS_b

TPM2_

CH1

— 24 24 ADC0_DP0 ADC0_

DP0/

CMP0_IN0

ADC0_

DP0/

CMP0_IN0

— 25 25 ADC0_

DM0

ADC0_

DM0/

CMP0_IN1

ADC0_

DM0/

CMP0_IN1

— 41 41 PTC5 DISABLED PTC5/

LLWU_

P13/

RF_NOT_

ALLOWED

LPTMR0_

ALT2

LPUART0_

RTS_b

TPM1_

CH1

BSM_CLK

— 42 42 PTC6 DISABLED PTC6/

LLWU_

P14/

RF_

RFOSC_

I2C1_SCL LPUART0_

TPM2_

CH0

BSM_

FRAME

— 43 43 PTC7 DISABLED PTC7/

LLWU_P15

SPI0_

PCS2

I2C1_SDA LPUART0_

TPM2_

CH1

BSM_

DATA

1 48 48 PTC19 DISABLED PTC19/

LLWU_P3/

RF_

EARLY_

WARNING

SPI0_

PCS0

I2C0_SCL LPUART0_

CTS_b

BSM_CLK LPUART1_

CTS_b

2 1 1 PTA0 SWD_DIO PTA0 SPI0_

PCS1

TPM1_

CH0

SWD_DIO

3 2 2 PTA1 SWD_CLK PTA1 SPI1_

PCS0

TPM1_

CH1

SWD_CLK

4 3 3 PTA2 RESET_b PTA2 TPM0_

CH3

RESET_b

5 8 8 PSWITCH PSWITCH PSWITCH

6 9 9 DCDC_

CFG

DCDC_

CFG

DCDC_

CFG

7 9 10 VDCDC_IN VDCDC_IN VDCDC_IN

8 10 11 DCDC_LP DCDC_LP DCDC_LP

9 11 13 DCDC_

GND

DCDC_

GND

DCDC_

GND

10 12 12 DCDC_LN DCDC_LN DCDC_LN

11 13 14 VDD_

1P8OUT

VDD_

1P8OUT

VDD_

1P8OUT

12 14 — DCDC_LN DCDC_LN DCDC_LN

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 73

NXP Semiconductors

"Wett

able"

HVQ

"Wett

able"

HVQ

LQF

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

13 15 15 VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

14 16 16 PTB0 DISABLED PTB0/

LLWU_P8/

RF_

RFOSC_

I2C0_SCL CMP0_

OUT

TPM0_

CH1

CLKOUT CAN0_TX

15 17 17 PTB1 ADC0_

SE1/

CMP0_IN5

ADC0_

SE1/

CMP0_IN5

PTB1/

RF_

PRIORITY

DTM_RX I2C0_SDA LPTMR0_

ALT1

TPM0_

CH2

CMT_IRO CAN0_RX

16 18 18 PTB2 ADC0_

SE3/

CMP0_IN3

ADC0_

SE3/

CMP0_IN3

PTB2/

RF_NOT_

ALLOWED

DTM_TX TPM1_

CH0

17 19 19 PTB3 ADC0_

SE2/

CMP0_IN4

ADC0_

SE2/

CMP0_IN4

PTB3/

ERCLK32K

LPUART1_

RTS_b

CLKOUT TPM1_

CH1

RTC_

CLKOUT

18 20 20 VDD_0 VDD_0 VDD_0

19 21 21 PTB16 EXTAL32K EXTAL32K PTB16 LPUART1_

I2C1_SCL TPM2_

CH0

20 22 22 PTB17 XTAL32K XTAL32K PTB17 LPUART1_

I2C1_SDA TPM2_

CH1

BSM_CLK

21 23 23 PTB18 NMI_b ADC0_

SE4/

CMP0_IN2

PTB18 LPUART1_

CTS_b

I2C1_SCL TPM_

CLKIN0

TPM0_

CH0

NMI_b

22 26 26 VREFL/

VSSA

VREFL/

VSSA

VREFL/

VSSA

23 27 27 VREFH/

VREF_

OUT

VREFH/

VREF_

OUT

VREFH/

VREF_

OUT

24 28 28 VDDA VDDA VDDA

25 29 29 XTAL_OUT XTAL_OUT XTAL_OUT

26 30 30 EXTAL EXTAL EXTAL

27 31 31 XTAL XTAL XTAL

28 32 32 VDD_RF3 VDD_RF3 VDD_RF3

29 33 33 ANT ANT ANT

30 34 34 GANT GANT GANT

31 35 35 VDD_RF2 VDD_RF2 VDD_RF2

32 36 36 VDD_RF1 VDD_RF1 VDD_RF1

33 37 37 PTC1 DISABLED PTC1/

RF_

EARLY_

WARNING

I2C0_SDA LPUART0_

RTS_b

TPM0_

CH2

SPI1_SCK BSM_CLK

Pin Diagrams and Pin Assignments

74 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

"Wett

able"

HVQ

"Wett

able"

HVQ

LQF

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

34 38 38 PTC2 DISABLED PTC2/

LLWU_P10

TX_

SWITCH

I2C1_SCL LPUART0_

CMT_IRO DTM_RX SPI1_

SOUT

BSM_

FRAME

35 39 39 PTC3 DISABLED PTC3/

LLWU_P11

RX_

SWITCH

I2C1_SDA LPUART0_

TPM0_

CH1

DTM_TX SPI1_SIN CAN0_TX

36 40 40 PTC4 DISABLED PTC4/

LLWU_

P12/

BLE_RF_

ACTIVE

EXTRG_IN LPUART0_

CTS_b

TPM1_

CH0

BSM_

DATA

SPI1_

PCS0

CAN0_RX

37 44 44 VDD_1 VDD_1 VDD_1

38 45 45 PTC16 DISABLED PTC16/

LLWU_P0/

RF_

STATUS

SPI0_SCK I2C0_SDA LPUART0_

RTS_b

TPM0_

CH3

LPUART1_

RTS_b

39 46 46 PTC17 DISABLED PTC17/

LLWU_P1/

RF_EXT_

OSC_EN

SPI0_

SOUT

I2C1_SCL LPUART0_

BSM_

FRAME

DTM_RX LPUART1_

40 47 47 PTC18 DISABLED PTC18/

LLWU_P2

SPI0_SIN I2C1_SDA LPUART0_

BSM_

DATA

DTM_TX LPUART1_

41 49 49-64 Ground NA

7.2 KW36A Pinouts

KW36A device pinouts are shown in the figures below.

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 75

NXP Semiconductors

PTC18

PTC17

PTC16

VDD_1

PTC4

PTC3

PTC2

PTC1

VDD_RF1

VDD_RF2

DCDC_LN

VDD_1P8OUT

PTB17

PTB16

VDD_0

PTB3

PTB2

PTB1

PTB0

VDD_1P5OUT_PMCIN

GANT

ANT

VDD_RF3

XTAL

EXTAL

XTAL_OUT

VDDA

VREFH/VREF_OUT

VREFL/VSSA

PTB18

DCDC_LN

DCDC_GND

DCDC_LP

VDCDC_IN

DCDC_CFG

PSWITCH

PTA2

PTA1

PTA0

PTC19

*pin 41 is ground

Figure 20. 40-pin "Wettable" HVQFN pinout diagram

Pin Diagrams and Pin Assignments

76 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

DCDC_LN

DCDC_LP

VDCDC_IN

DCDC_CFG

PSWITCH

PTA19

PTA18

PTA17

PTA16

PTA2

PTA1

PTA0

PTC19

PTC18

PTC17

PTC16

VDD_1

PTC7

PTC6

PTC5

PTC4

PTC3

PTC2

PTC1

VDD_RF1

VDD_RF2

GANT

ANT

VDD_RF3

XTAL

EXTAL

XTAL_OUT

VDDA

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

VDD_0

PTB3

PTB2

PTB1

PTB0

VDD_1P5OUT_PMCIN

VDD_1P8OUT

DCDC_GND

ADC0_DP0

PTB18

PTB17

PTB16

49 50 51 52

53 54 55 56

57 58 59 60

61 62 63 64

*pin 49 - 64 are ground

Figure 21. 48-pin LQFN pinout diagram

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 77

NXP Semiconductors

DCDC_LN

DCDC_GND

DCDC_LP

PSWITCH

PTA19

PTA18

PTA17

PTA16

PTA2

PTA1

PTA0

PTC19

PTC18

PTC17

PTC16

VDD_1

PTC7

PTC6

PTC5

PTC4

PTC3

PTC2

PTC1

VDD_RF1

VDD_RF2

GANT

ANT

VDD_RF3

XTAL

EXTAL

XTAL_OUT

VDDA

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

VDD_0

PTB3

PTB2

PTB1

PTB0

VDD_1P5OUT_PMCIN

DCDC_LN

VDD_1P8OUT

ADC0_DP0

PTB18

PTB17

PTB16

*pin 49 is ground

DCDC_CFG/VDCDC_IN

Figure 22. 48-pin "Wettable" HVQFN pinout diagram

7.3 KW35A Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control and Interrupt Module

is used to select the functionality for each GPIO pin. ALT0 is reserved for analog

functions on some GPIO pins. ALT1 – ALT9 are assigned to the available digital

functions on each GPIO pin. GPIO pins with a default of “disabled” are high impedance

after reset – their input and output buffers are disabled.

Pin Diagrams and Pin Assignments

78 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

"Wett

able"

HVQ

"Wett

able"

HVQ

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

— 4 PTA16 DISABLED PTA16/

LLWU_P4

SPI1_

SOUT

TPM0_CH0

— 5 PTA17 DISABLED PTA17/

LLWU_P5

SPI1_SIN TPM_

CLKIN1

— 6 PTA18 DISABLED PTA18/

LLWU_P6

SPI1_SCK TPM2_CH0

— 7 PTA19 ADC0_SE5 ADC0_SE5 PTA19/

LLWU_P7

SPI1_PCS0 TPM2_CH1

— 24 ADC0_DP0 ADC0_

DP0/

CMP0_IN0

ADC0_

DP0/

CMP0_IN0

— 25 ADC0_DM0 ADC0_

DM0/

CMP0_IN1

ADC0_

DM0/

CMP0_IN1

— 41 PTC5 DISABLED PTC5/

LLWU_P13/

RF_NOT_

ALLOWED

LPTMR0_

ALT2

LPUART0_

RTS_b

TPM1_CH1 BSM_CLK

— 42 PTC6 DISABLED PTC6/

LLWU_P14/

RF_

RFOSC_

I2C1_SCL LPUART0_

TPM2_CH0 BSM_

FRAME

— 43 PTC7 DISABLED PTC7/

LLWU_P15

SPI0_PCS2 I2C1_SDA LPUART0_

TPM2_CH1 BSM_DATA

1 48 PTC19 DISABLED PTC19/

LLWU_P3/

RF_

EARLY_

WARNING

SPI0_PCS0 I2C0_SCL LPUART0_

CTS_b

BSM_CLK

2 1 PTA0 SWD_DIO PTA0 SPI0_PCS1 TPM1_CH0 SWD_DIO

3 2 PTA1 SWD_CLK PTA1 SPI1_PCS0 TPM1_CH1 SWD_CLK

4 3 PTA2 RESET_b PTA2 TPM0_CH3 RESET_b

5 8 PSWITCH PSWITCH PSWITCH

6 9 DCDC_

CFG

DCDC_

CFG

DCDC_

CFG

7 9 VDCDC_IN VDCDC_IN VDCDC_IN

8 10 DCDC_LP DCDC_LP DCDC_LP

9 11 DCDC_

GND

DCDC_

GND

DCDC_

GND

10 12 DCDC_LN DCDC_LN DCDC_LN

11 13 VDD_

1P8OUT

VDD_

1P8OUT

VDD_

1P8OUT

12 14 DCDC_LN DCDC_LN DCDC_LN

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 79

NXP Semiconductors

"Wett

able"

HVQ

"Wett

able"

HVQ

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

13 15 VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

14 16 PTB0 DISABLED PTB0/

LLWU_P8/

RF_

RFOSC_

I2C0_SCL CMP0_

OUT

TPM0_CH1 CLKOUT

15 17 PTB1 ADC0_SE1/

CMP0_IN5

ADC0_SE1/

CMP0_IN5

PTB1/

RF_

PRIORITY

DTM_RX I2C0_SDA LPTMR0_

ALT1

TPM0_CH2 CMT_IRO

16 18 PTB2 ADC0_SE3/

CMP0_IN3

ADC0_SE3/

CMP0_IN3

PTB2/

RF_NOT_

ALLOWED

DTM_TX TPM1_CH0

17 19 PTB3 ADC0_SE2/

CMP0_IN4

ADC0_SE2/

CMP0_IN4

PTB3/

ERCLK32K

CLKOUT TPM1_CH1 RTC_

CLKOUT

18 20 VDD_0 VDD_0 VDD_0

19 21 PTB16 EXTAL32K EXTAL32K PTB16 I2C1_SCL TPM2_CH0

20 22 PTB17 XTAL32K XTAL32K PTB17 I2C1_SDA TPM2_CH1 BSM_CLK

21 23 PTB18 NMI_b ADC0_SE4/

CMP0_IN2

PTB18 I2C1_SCL TPM_

CLKIN0

TPM0_CH0 NMI_b

22 26 VREFL/

VSSA

VREFL/

VSSA

VREFL/

VSSA

23 27 VREFH/

VREF_OUT

VREFH/

VREF_OUT

VREFH/

VREF_OUT

24 28 VDDA VDDA VDDA

25 29 XTAL_OUT XTAL_OUT XTAL_OUT

26 30 EXTAL EXTAL EXTAL

27 31 XTAL XTAL XTAL

28 32 VDD_RF3 VDD_RF3 VDD_RF3

29 33 ANT ANT ANT

30 34 GANT GANT GANT

31 35 VDD_RF2 VDD_RF2 VDD_RF2

32 36 VDD_RF1 VDD_RF1 VDD_RF1

33 37 PTC1 DISABLED PTC1/

RF_

EARLY_

WARNING

I2C0_SDA LPUART0_

RTS_b

TPM0_CH2 SPI1_SCK BSM_CLK

34 38 PTC2 DISABLED PTC2/

LLWU_P10

TX_

SWITCH

I2C1_SCL LPUART0_

CMT_IRO DTM_RX SPI1_

SOUT

BSM_

FRAME

35 39 PTC3 DISABLED PTC3/

LLWU_P11

RX_

SWITCH

I2C1_SDA LPUART0_

TPM0_CH1 DTM_TX SPI1_SIN

Pin Diagrams and Pin Assignments

80 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

"Wett

able"

HVQ

"Wett

able"

HVQ

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

36 40 PTC4 DISABLED PTC4/

LLWU_P12/

BLE_RF_

ACTIVE

EXTRG_IN LPUART0_

CTS_b

TPM1_CH0 BSM_DATA SPI1_PCS0

37 44 VDD_1 VDD_1 VDD_1

38 45 PTC16 DISABLED PTC16/

LLWU_P0/

RF_

STATUS

SPI0_SCK I2C0_SDA LPUART0_

RTS_b

TPM0_CH3

39 46 PTC17 DISABLED PTC17/

LLWU_P1/

RF_EXT_

OSC_EN

SPI0_

SOUT

I2C1_SCL LPUART0_

BSM_

FRAME

DTM_RX

40 47 PTC18 DISABLED PTC18/

LLWU_P2

SPI0_SIN I2C1_SDA LPUART0_

BSM_DATA DTM_TX

41 49 Ground NA

7.4 KW35A Pinouts

KW35A device pinouts are shown in the figures below.

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 81

NXP Semiconductors

PTC18

PTC17

PTC16

VDD_1

PTC4

PTC3

PTC2

PTC1

VDD_RF1

VDD_RF2

DCDC_LN

VDD_1P8OUT

PTB17

PTB16

VDD_0

PTB3

PTB2

PTB1

PTB0

VDD_1P5OUT_PMCIN

GANT

ANT

VDD_RF3

XTAL

EXTAL

XTAL_OUT

VDDA

VREFH/VREF_OUT

VREFL/VSSA

PTB18

DCDC_LN

DCDC_GND

DCDC_LP

VDCDC_IN

DCDC_CFG

PSWITCH

PTA2

PTA1

PTA0

PTC19

*pin 41 is ground

Figure 23. 40-pin "Wettable" HVQFN pinout diagram

Pin Diagrams and Pin Assignments

82 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

DCDC_LN

DCDC_GND

DCDC_LP

PSWITCH

PTA19

PTA18

PTA17

PTA16

PTA2

PTA1

PTA0

PTC19

PTC18

PTC17

PTC16

VDD_1

PTC7

PTC6

PTC5

PTC4

PTC3

PTC2

PTC1

VDD_RF1

VDD_RF2

GANT

ANT

VDD_RF3

XTAL

EXTAL

XTAL_OUT

VDDA

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

VDD_0

PTB3

PTB2

PTB1

PTB0

VDD_1P5OUT_PMCIN

DCDC_LN

VDD_1P8OUT

ADC0_DP0

PTB18

PTB17

PTB16

*pin 49 is ground

DCDC_CFG/VDCDC_IN

Figure 24. 48-pin "Wettable" HVQFN pinout diagram

7.5 KW34A Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control and Interrupt

Module is used to select the functionality for each GPIO pin. ALT0 is reserved for

analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available

digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high

impedance after reset – their input and output buffers are disabled.

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 83

NXP Semiconductors

"Wett

able"

HVQ

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

1 PTA0 SWD_DIO PTA0 SPI0_PCS1 TPM1_CH0 SWD_DIO

2 PTA1 SWD_CLK PTA1 SPI1_PCS0 TPM1_CH1 SWD_CLK

3 PTA2 RESET_b PTA2 TPM0_CH3 RESET_b

4 PTA16 DISABLED PTA16/

LLWU_P4

SPI1_SOUT TPM0_CH0

5 PTA17 DISABLED PTA17/

LLWU_P5

SPI1_SIN TPM_

CLKIN1

6 PTA18 DISABLED PTA18/

LLWU_P6

SPI1_SCK TPM2_CH0

7 PTA19 ADC0_SE5 ADC0_SE5 PTA19/

LLWU_P7

SPI1_PCS0 TPM2_CH1

8 PSWITCH PSWITCH PSWITCH

9 DCDC_CFG/

VDCDC_IN

DCDC_CFG/

VDCDC_IN

DCDC_CFG/

VDCDC_IN

10 DCDC_LP DCDC_LP DCDC_LP

11 DCDC_GND DCDC_GND DCDC_GND

12 DCDC_LN DCDC_LN DCDC_LN

13 VDD_

1P8OUT

VDD_

1P8OUT

VDD_

1P8OUT

14 DCDC_LN DCDC_LN DCDC_LN

15 VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

VDD_

1P5OUT_

PMCIN

16 PTB0 DISABLED PTB0/

LLWU_P8/

RF_

RFOSC_EN

I2C0_SCL CMP0_OUT TPM0_CH1 CLKOUT

17 PTB1 ADC0_SE1/

CMP0_IN5

ADC0_SE1/

CMP0_IN5

PTB1/

RF_

PRIORITY

DTM_RX I2C0_SDA LPTMR0_

ALT1

TPM0_CH2 CMT_IRO

18 PTB2 ADC0_SE3/

CMP0_IN3

ADC0_SE3/

CMP0_IN3

PTB2/

RF_NOT_

ALLOWED

DTM_TX TPM1_CH0

19 PTB3 ADC0_SE2/

CMP0_IN4

ADC0_SE2/

CMP0_IN4

PTB3/

ERCLK32K

CLKOUT TPM1_CH1 RTC_

CLKOUT

20 VDD_0 VDD_0 VDD_0

21 PTB16 EXTAL32K EXTAL32K PTB16 I2C1_SCL TPM2_CH0

22 PTB17 XTAL32K XTAL32K PTB17 I2C1_SDA TPM2_CH1 BSM_CLK

23 PTB18 NMI_b ADC0_SE4/

CMP0_IN2

PTB18 I2C1_SCL TPM_

CLKIN0

TPM0_CH0 NMI_b

24 ADC0_DP0 ADC0_DP0/

CMP0_IN0

ADC0_DP0/

CMP0_IN0

Pin Diagrams and Pin Assignments

84 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

"Wett

able"

HVQ

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

25 ADC0_DM0 ADC0_DM0/

CMP0_IN1

ADC0_DM0/

CMP0_IN1

26 VREFL/

VSSA

VREFL/

VSSA

VREFL/

VSSA

27 VREFH/

VREF_OUT

VREFH/

VREF_OUT

VREFH/

VREF_OUT

28 VDDA VDDA VDDA

29 XTAL_OUT XTAL_OUT XTAL_OUT

30 EXTAL EXTAL EXTAL

31 XTAL XTAL XTAL

32 VDD_RF3 VDD_RF3 VDD_RF3

33 ANT ANT ANT

34 GANT GANT GANT

35 VDD_RF2 VDD_RF2 VDD_RF2

36 VDD_RF1 VDD_RF1 VDD_RF1

37 PTC1 DISABLED PTC1/

RF_EARLY_

WARNING

I2C0_SDA LPUART0_

RTS_b

TPM0_CH2 SPI1_SCK BSM_CLK

38 PTC2 DISABLED PTC2/

LLWU_P10

TX_SWITCH I2C1_SCL LPUART0_

CMT_IRO DTM_RX SPI1_SOUT BSM_

FRAME

39 PTC3 DISABLED PTC3/

LLWU_P11

RX_

SWITCH

I2C1_SDA LPUART0_

TPM0_CH1 DTM_TX SPI1_SIN

40 PTC4 DISABLED PTC4/

LLWU_P12/

BLE_RF_

ACTIVE

EXTRG_IN LPUART0_

CTS_b

TPM1_CH0 BSM_DATA SPI1_PCS0

41 PTC5 DISABLED PTC5/

LLWU_P13/

RF_NOT_

ALLOWED

LPTMR0_

ALT2

LPUART0_

RTS_b

TPM1_CH1 BSM_CLK

42 PTC6 DISABLED PTC6/

LLWU_P14/

RF_

RFOSC_EN

I2C1_SCL LPUART0_

TPM2_CH0 BSM_

FRAME

43 PTC7 DISABLED PTC7/

LLWU_P15

SPI0_PCS2 I2C1_SDA LPUART0_

TPM2_CH1 BSM_DATA

44 VDD_1 VDD_1 VDD_1

45 PTC16 DISABLED PTC16/

LLWU_P0/

RF_STATUS

SPI0_SCK I2C0_SDA LPUART0_

RTS_b

TPM0_CH3

46 PTC17 DISABLED PTC17/

LLWU_P1/

RF_EXT_

OSC_EN

SPI0_SOUT I2C1_SCL LPUART0_

BSM_

FRAME

DTM_RX

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 85

NXP Semiconductors

"Wett

able"

HVQ

Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 ALT8 ALT9

47 PTC18 DISABLED PTC18/

LLWU_P2

SPI0_SIN I2C1_SDA LPUART0_

BSM_DATA DTM_TX

48 PTC19 DISABLED PTC19/

LLWU_P3/

RF_EARLY_

WARNING

SPI0_PCS0 I2C0_SCL LPUART0_

CTS_b

BSM_CLK

49 Ground NA

7.6 KW34A Pinouts

KW34A device pinouts are shown in the figure below.

Pin Diagrams and Pin Assignments

86 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

DCDC_LN

DCDC_GND

DCDC_LP

PSWITCH

PTA19

PTA18

PTA17

PTA16

PTA2

PTA1

PTA0

PTC19

PTC18

PTC17

PTC16

VDD_1

PTC7

PTC6

PTC5

PTC4

PTC3

PTC2

PTC1

VDD_RF1

VDD_RF2

GANT

ANT

VDD_RF3

XTAL

EXTAL

XTAL_OUT

VDDA

VREFH/VREF_OUT

VREFL/VSSA

ADC0_DM0

VDD_0

PTB3

PTB2

PTB1

PTB0

VDD_1P5OUT_PMCIN

DCDC_LN

VDD_1P8OUT

ADC0_DP0

PTB18

PTB17

PTB16

*pin 49 is ground

DCDC_CFG/VDCDC_IN

Figure 25. 48-pin "Wettable" HVQFN pinout diagram

7.7 Module Signal Description Tables

The following sections correlate the chip-level signal name with the signal name used

in the chapter of the module. They also briefly describe the signal function and

direction.

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 87

NXP Semiconductors

7.7.1 Core Modules

This section contains tables describing the core module signal descriptions.

Table 47. SWD Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

SWD_DIO SWD_DIO Serial Wire Debug Data

Input/Output1I/O

SWD_CLK SWD_CLK Serial Wire Clock2I

1. Pulled up internally by default

2. Pulled down internally by default

7.7.2 Radio Modules

This section contains tables describing the radio signals.

Table 48. Radio Module Signal Descriptions

Module Signal Name Pin Direction Pin Name Pin Description

ANT O ANT Antenna

BLE_RF_ACTIVE O BLE_RF_ACTIVE An output which is asserted prior to any Radio event

and remains asserted for the duration of the event.

BSM_CLK O BSM_CLK Bit Streaming Mode (BSM) clock signal. 1 MHz bit

rate clock. BSM_DATA and BSM_FRAME are

synchronized to BSM_CLK. External device should

capture BSM_FRAME and BSM_DATA on rising

edge of BSM_CLK.

BSM_DATA O BSM_DATA Serial Bluetooth LE packet bit stream, LSB-first.

Valid on rising edge of BSM_CLK.

BSM_FRAME O BSM_FRAME Framing signal to indicate the start of reception.

Active high.

DTM_RX I DTM_RX Direct Test Mode Receive

DTM_TX O DTM_TX Direct Test Mode Transmit

GANT I GANT Antenna ground

RF_STATUS O RF_STATUS An output which indicates when the Radio is in an

Rx or Tx event; software can also control this signal

directly.

RF_PRIORITY O RF_PRIORITY An output which indicates to the external WiFi

device that the Radio event is a high priority and it

needs access to the 2.4 GHz antenna.

RF_EARLY_WARNING O RF_EARLY_WARNING Bluetooth LE LL generated signal which can be

used to wake an external sensor to make a

measurement before a Bluetooth LE event.

RF_NOT_ALLOWED I RF_NOT_ALLOWED External signal which causes the internal Radio to

cease radio activity.

Table continues on the next page...

Pin Diagrams and Pin Assignments

88 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 48. Radio Module Signal Descriptions (continued)

Module Signal Name Pin Direction Pin Name Pin Description

RF_TX_CONF I RF_TX_CONF Signal from an external Radio which indicates the

availability of the 2.4 GHz antenna to the internal

Radio.

NOTE: This is a GPIO, not a dedicated PIN.

RX_SWITCH O RX_SWITCH Front End Module receive mode signal.

TX_SWITCH O TX_SWITCH Front End Module transmit mode signal.

Table 49. Radio Module Miscellaneous Pin Descriptions

Pin Name Pad Direction Pin Name Pin Description

RF_INT_OSC_EN I RF_RFOSC_EN External request to turn on the Radio's internal RF

oscillator.

RF_EXT_OSC_EN O RF_EXT_OSC_EN Internal request to turn on an External oscillator for

use by the internal Radio. The request can also be

from the SoC if it is using the RF oscillator as its

clock.

7.7.3 System Modules

This section contains tables describing the system signals.

Table 50. System Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

NMI_b — Non-maskable interrupt I

RESET_b — Reset bidirectional signal I/O

VDD_[1:0] VDD Power supply I

Ground VSS Ground I

VDD_RF[3:1] VDD_RF Radio power supply I

VDCDC_IN VDCDC_IN VDCDC_IN I

VDD_1P8OUT VDD_1P8 DC-DC 1.8 V Regulated

Output / Input in bypass

I/O

VDD_1P5OUT_PMCIN VDD_1P5/VDD_PMC DC-DC 1.5 V Regulated

Output / PMC Input in

bypass

I/O

PSWITCH PSWITCH DC-DC enable switch I

DCDC_CFG DCDC_CFG DC-DC switch mode select I

DCDC_LP DCDC_LP DC-DC inductor input

positive

I/O

Table continues on the next page...

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 89

NXP Semiconductors

Table 50. System Module Signal Descriptions (continued)

SoC Signal Name Module Signal Name Description I/O

DCDC_LN DCDC_LN DC-DC inductor input

negative

I/O

DCDC_GND DCDC_GND DC-DC ground I

Table 51. LLWU Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

LLWU_P[15:0] LLWU_P[15:0] Wake-up inputs I

7.7.4 Clock Modules

This section contains tables for Clock signal descriptions.

Table 52. Clock Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

EXTAL EXTAL 26 MHz/32 MHz External

clock/Oscillator input

XTAL XTAL 26 MHz/32 MHz Oscillator

input

XTAL_OUT XTAL_OUT 26 MHz/32 MHz Clock output O

XTAL_OUT_EN XTAL_OUT_ENABLE 26 MHz/32 MHz Clock output

enable for XTAL_OUT

EXTAL32K EXTAL32K 32 kHz External clock/

Oscillator input

XTAL32K XTAL32K 32 kHz Oscillator input I

CLKOUT CLKOUT Internal clocks monitor O

7.7.5 Analog Modules

This section contains tables for Analog signal descriptions.

Table 53. ADC0 Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

ADC0_DM0 DADM0 ADC Channel 0 Differential

Input Negative

Table continues on the next page...

Pin Diagrams and Pin Assignments

90 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 53. ADC0 Signal Descriptions (continued)

SoC Signal Name Module Signal Name Description I/O

ADC0_DP0 DADP0 ADC Channel 0 Differential

Input Positive

ADC0_SE[5:1] AD[5:1] ADC Channel 0 Single-ended

Input n

VREFH VREFSH Voltage Reference Select

High

VDDA VDDA Analog Power Supply I

VSSA VSSA Analog Ground I

Table 54. CMP0 Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

CMP0_IN[5:0] IN[5:0] Analog voltage inputs I

CMP0_OUT CMP0 Comparator output O

Table 55. VREF Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

VREF_OUT VREF_OUT Internally generated voltage

reference output

7.7.6 Timer Modules

This section contains tables describing timer module signals.

Table 56. TPM0 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

TPM_CLKIN[1:0] TPM_EXTCLK External clock I

TPM0_CH[3:0] TPM_CH[3:0] TPM channel I/O

Table 57. TPM1 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

TPM_CLKIN[1:0] TPM_EXTCLK External clock I

TPM1_CH[1:0] TPM_CH[1:0] TPM channel I/O

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 91

NXP Semiconductors

Table 58. TPM2 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

TPM_CLKIN[1:0] TPM_EXTCLK External clock I

TPM2_CH[1:0] TPM_CH[1:0] TPM channel I/O

Table 59. LPTMR0 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

LPTMR0_ALT[2:1] LPTMR0_ALT[2:1] Pulse counter input pin I

Table 60. RTC Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output O

7.7.7 Communication Interfaces

This section contains tables for the signal descriptions for the communication modules.

Table 61. SPI0 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

SPI0_PCS0 PCS0/SS Chip Select/Slave Select I/O

SPI0_PCS[2:1] PCS[2:1] Chip Select O

SPI0_SCK SCK Serial Clock I/O

SPI0_SIN SIN Data In I

SPI0_SOUT SOUT Data Out O

Table 62. SPI1 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

SPI1_PCS0 SPI1_PCS0 Chip Select/Slave Select I/O

SPI1_SCK SCK Serial Clock I/O

SPI1_SIN SIN Data In I

SPI1_SOUT SOUT Data Out O

Pin Diagrams and Pin Assignments

92 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 63. I2C0 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

I2C0_SCL SCL I2C serial clock line I/O

I2C0_SDA SDA I2C serial data line I/O

Table 64. I2C1 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

I2C1_SCL SCL I2C serial clock line I/O

I2C1_SDA SDA I2C serial data line I/O

Table 65. CAN0 Signal Descriptions (KW36 only)

SoC Signal Name Module Signal Name Description I/O

CAN0_RX CAN RX CAN Receive Pin I

CAN0_TX CAN TX CAN Transmit Pin O

Table 66. LPUART0 Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

LPUART0_CTS_b LPUART CTS Clear To Send I

LPUART0_RTS_b LPUART RTS Request To Send O

LPUART0_RX LPUART RxD Receive Data I

LPUART0_TX LPUART TxD Transmit Data1I/O

1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

transmit direction is configured for receive data

Table 67. LPUART1 Module Signal Descriptions (KW36 only)

SoC Signal Name Module Signal Name Description I/O

LPUART1_CTS_b LPUART CTS Clear To Send I

LPUART1_RTS_b LPUART RTS Request To Send O

LPUART1_RX LPUART RxD Receive Data I

LPUART1_TX LPUART TxD Transmit Data1I/O

1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or

transmit direction is configured for receive data

Pin Diagrams and Pin Assignments

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 93

NXP Semiconductors

7.7.8 Human-Machine Interfaces(HMI)

This section contains tables describing the HMI signals.

Table 68. GPIO Module Signal Descriptions

SoC Signal Name Module Signal Name Description I/O

PTA[19:16][2:0] PORTA19-16, 2-0 General Purpose Input/

Output

I/O

PTB[18:16][3:0] PORTB18-16, 3-0 General Purpose Input/

Output

I/O

PTC[19:16][7:1] PORTC19-16, 7-1 General Purpose Input/

Output

I/O

8 Package Information

8.1 Obtaining package dimensions

Package dimensions are available in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

document number of the drawing:

Table 69. Packaging Dimensions

If you want the drawing for this package Then use this document number

40-pin "Wettable" HVQFN (6x6) 98ASA01025D

48-pin LQFN (7x7) 98ASA00694D

48-pin "Wettable" HVQFN (7x7) 98ASA01307D

9 Part identification

9.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

Package Information

94 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

9.2 Format

Part numbers for this device have the following format:

Q KW## A FFF R T PP CC N

9.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Table 70. Part number fields descriptions

Field Description Values

Q Qualification status • M = Fully qualified, general market flow

• P = Prequalification

KW## Kinetis Wireless family • KW34

• KW35

• KW36

A Key attribute • A = Automotive Qualification

FFF Program flash memory size • 512 = 512 KB

T Temperature range (°C) • V = –40 to 105

• C = –40 to 85

PP Package identifier • HT = 48 LQFN (7 mm x 7 mm)

• FP = 40 "Wettable" HVQFN (6 mm x 6 mm)

• FT = 48 "Wettable" HVQFN (7 mm x 7 mm)

CC Maximum CPU frequency (MHz) • 4 = 48 MHz

N Packaging type • (Blank) = Tray

• R = Tape and reel

9.4 Example

This is an example part number:

MKW36A512VFT4

Part identification

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 95

NXP Semiconductors

10 Revision History Table 71. Revision History

Rev. No. Date Substantial Changes

Rev 8 05/2020 • Updated Tx output power to 5 dBm from 3.5 dBm throughout. Also preceded 5 dBM with a

plus "+" sign.

• Replaced VDD_XTAL with VDD_RF3.

• Appended the second row 'Supply current Rx On with DC-DC converter enable' with the

following text: VDD_1P5_buck=1.5 V in Receiver Feature Summary.

• In Top level Transmitter Specifications - Table 5 :

• Appended the rows for supply current Tx On with PRF and DC-DC converter enabled

for 0 dBM with VDD_1P5_buck=1.5 V.

• Added rows related to supply current Tx On with PRF = +3.5 dBm and 5dBm along

with associated footnotes.

• Updated symbol of Output RF Frequency to fRFout from fin.

• Added row for maximum RF Output Power; LDO-HF bumped along with an

associated footnote.

• Added Figure 5.

• Added Table 7. Also modified title of Table 6.

• Added VDD_1P5 specification in Voltage and current operating requirements.

• Added VPOR_VDD_1P5 specification in LVD and POR operating requirements

• Added VOH performance for normal drive pad at 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1 mA in

Voltage and current operating behaviors.

• Added Table 17. Also updated title of Table 16.

• Updated VCDM ratings in ESD handling ratings.

• Added VDD_1P5 symbol to "Bypass Mode Supply Voltage (RF and Analog)" in Table 41.

• In Table 42 :

• Updated specifications of DC-DC Converter Output Power. Added conditions,

VDCDC_IN above 2.7 V and below 2.7 V.

• Updated specifications of 1.8 V Output Current.

• Updated minimum value to 1.45 V in "1.5 V Voltage Output" for Pout<=+3.5 dBM.

Updated the corresponding footnote with the correct value of 1.45 V.

• Added a separate row for "1.5 V Voltage Output" for Pout=+5 dBM along with a

footnote.

• Updated maximum value of 1.5 V Output Current to 45.

Rev 7 09/2019 • Removed flash access control feature from Security Features.

• Added the following footnote to Table 14 : "The device was configured in buck mode auto-

start to perform the measurements. The DCDC_IN was powered with 3.0 V. VDD_1P8OUT

was configured to output 1.8 V and VDD_1P5OUT_PMCIN was configured to output 1.5 V."

• Added the following footnote to VLPS, LLSx and VLLSx modes: "DCDC configured in

pulsed mode." in Table 14.

• Added thermal attributes for 48-pin "Wettable" HVQFN package, and replaced standard

JESD51-2 with JESD51-2A in the footnotes in Thermal attributes.

• Removed "Flash timing specifications – program and erase" and "Flash high voltage current

behaviors" tables.

• Added DCDC internal oscillator row in Table 41.

• Updated Table 42 as follows:

• In Switching Frequency row, updated the Typical value to DCDC reference frequency

divided by 16 and added the following footnote to it: "DCDC reference frequency is

derived from the RF oscillator or the DCDC internal oscillator".

• Added VDD_1P8 ripple and VDD_1P5 ripple rows.

Table continues on the next page...

Revision History

96 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

Table 71. Revision History (continued)

Rev. No. Date Substantial Changes

• Updated introductory text beginning "The Port Control and Interrupt Module is used to select

the functionality for...." in KW36A Signal Multiplexing and Pin Assignments. Same update

done for KW35A and KW34A as well.

• Updated "DEFAULT" column to correct "DISABLED" status of PTA19, PTB1/2/3 pin names

in KW36/35/34 pinouts.

Rev 7

Draft B

04/2019 • Added "Top Line Marking" column to the Orderable parts details table.

• Removed "Galois counter mode (AES-GCM)" and "DES modes" features of LTC from

Security Features.

• Removed "Logic Input Voltage Low/High" rows from Table 2.

• Removed the following footnote from Table 13 : "Supported through the connectivity

software in its pre-defined Deep Sleep Modes.".

• Updated Typical value of IDD_RUN at 70 °C to 5.92 in Table 14.

• Added "48-pin Wettable HVQFN" column to Thermal attributes.

• Corrected name of vec_xtal32 to vec_extal32 in 32 kHz Oscillator Frequency Specifications.

• Updated minimum and maximum values of "1.5V Output Voltage" in Table 42. Also

specified the condition as "Consumed by radio".

• Corrected location of ground pins in 48-pin LQFN pinout diagram - Figure 21.

• Removed CAN0 and LPUART1 references from KW34A Signal Multiplexing and Pin

Assignments.

Rev 7

Draft A

11/2018 • Added following part numbers: MKW36A512VFT4, MKW35A512VFT4, and

MKW34A512VFT4

• Added 48 "Wettable" QFN package details including pin diagrams and assignments.

• Changed 40-pin "Wettable" QFN and 48-pin "Wettable" QFN to 40-pin "Wettable" HVQFN

and 48-pin "Wettable" HVQFN throughout.

• Applied new NXP Brand Guidelines for Bluetooth Low Energy.Removed references of BLE

and replaced with Bluetooth LE.

• Added the following footnote in Table 6 : "TX continuous wave power output at the RF pins

with the recommended matching components mounted on PCB.".

• Corrected maximum value of VDD_1P8 output in the footnote 6, in Table 42. DC-DC

Converter Specifications, from 3 V to 3.5 V.

• Removed silicon revision (R) field from Table 68. Part number fields descriptions.

Rev 6 09/2018 • Changed ARM to Arm and applied registered trademark to Cortex on first instance.

• Updated Related Resources table for Web release.

• Updated Introduction section to remove industrial details.

• Added space between value and unit throughout.

• Removed SPI Clock Rate row from Radio Operating Conditions.

• Added figure title to Figure 3 in the topic Transmit and PLL Feature Summary.

• Updated max values of IDD_STOP, IDD_LLS3/LLS2, IDD_VLLS0 (POR PO = ) in Table 13

• Updated Table 25 and Table 26.

• Updated Table 27 - Flash command timing specifications.

• Updated Table 28 - NVM reliability specifications.

• Backpage was also updated.

Rev 5 07/2018 • Updated title of the document to 'MKW36A/35A Data Sheet' from 'MKW35A/36A Data

Sheet'.

• Updated SoC name KW35A with KW36A/35A throughout.

• Replaced QFN with "Wettable" QFN throughout

• Added package drawings on front page and updated features under Multi-Standard Radio

section as follows: Modulation index: added 1.0 to the list.

• Updated Typical Rx Current and Typical Tx current values to 6.3 mA and 5.7 mA

respectively.

• Updated Low Power Mode (VLLS0) Current value to 258 nA from 182 nA.

• Replaced column name "Tier" with "Qualification" in this table.

Table continues on the next page...

Revision History

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 97

NXP Semiconductors

Table 71. Revision History (continued)

Rev. No. Date Substantial Changes

• Updated Introduction section.

• Removed Radio version number "V2.1" from Block Diagram.

• Updated Radio features, Microcontroller features, and System features.

• Appended "(Zero IF)" to Direct Conversion Receiver in Transceiver Description.

• Edited Key Specifications.

• Updated Receiver Sensitivity to –99 from –100 dBm in Radio features. Also added support

of 1 Mbps PHY to BLE link Layer hardware.

• Updated typical and minimum values in Table 3. Also updated footnote 7 to "BLE adjacent

and alternate selectivity performance is measured with modulated interference signals.".

• In Table 4 :

• updated and added receiver specifications with GFSK modulations, and

• updated footnote as follows: "Selectivity measured with an unmodulated blocker

except for GFSK BT=0.5, h=0.5 1mbps and GFSK BT=0.5, h=0.32 1mbps. The

desired signal is set at –85 dBm."

• Updated typical and maximum values in Table 5. Also updated footnote for TXH2 and TXH3

symbols as follows: "Harmonic Levels based on recommended 2 component match.

Transmit harmonic levels depend on the quality of matching components. Additional

harmonic margin using a 3rd matching component (1x shunt capacitor) is possible."

• Updated typical and maximum values in Table 13 and Table 14.

• Updated typical values in Table 16. Also added specifications of STOP and RUN modes of

radio state Tx (at +3.5 dBm).

• Updated 48-pin LQFN and 40-pin QFN values in Thermal attributes table. Removed thermal

metrics and kept thermal attributes RθJA and ΨJT. Also updated notes and added

information about how to use the thermal characterization parameter, ΨJT.

• Added following text in Reference Oscillator Specification : "The table below shows the

recommended crystal specifications. Note that these are recommendations.....". Also

updated 32M/26M typical values of Oscillator Startup Time to 500 μs.

• Updated typical and maximum values in Table 1

• Updated minimum, typical and maximum value of Temp sensor slope in Table 30

• Updated Table 1.

• Added a footnote under Buck Mode Supply Voltage in Table 41.

• Corrected spec name of Buck mode in DC-DC configuration to VDCDC_IN from VDDDCDC_IN

throughout.

• In Table 42,

• added a footnote for maximum value of DC-DC Converter Output Power,

• updated footnote example corresponding to '1.8V Output Voltage',

• updated maximum value in '1.8V Output Voltage' from "min(VDCDC_IN_buck, 3)" to

"min(VDCDC_IN_buck, 3.5)",

• added VDD_1P8 = 1.8V and VDD_1P5 = 1.5V conditions in 1.8V Output Current, and

• added the following information to the footnote corresponding to '1.5V Output

Voltage': "VDD_1P5 must not be programmed higher than VDD_1P8."

• Added VIO_DCDC row in Voltage and current operating ratings.

• Removed 48-pin LQFN pinout diagram and signal names from KW35A Signal Multiplexing

and Pin Assignments. Also updated signal name at pin 17 and pin 19 of 40 "Wettable" QFN

and 48 LQFN in ALT1 functionality to PTB3/ERCLK32K in KW36A Signal Multiplexing and

Pin Assignments and KW35A Signal Multiplexing and Pin Assignments.

Rev 4 10/2017 • BLE version 4.2 updated to 5.0.

• Updated maximum value of voltage range to 3.6 V.

• Updated Generic FSK modulation BT and receiver sensitivity from –100 dBm to –99 dBm.

• Added support of up to 26 devices by Whitelist and 8 private resolvable addresses in

hardware in the section Radio features.

• Updated number of GPIO digital pins in the 48-pin package to 25 in Peripheral features.

Table continues on the next page...

Revision History

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NXP Semiconductors

Table 71. Revision History (continued)

Rev. No. Date Substantial Changes

• Updated note text in Radio operating conditions as follows: "The recommended crystal

accuracy is ±40 ppm including initial accuracy, mechanical, temperature and aging factors."

• Updated maximum values in Power mode transition operating behaviors.

• Updated Typical values in Table 13 and Table 14.Also added the following note to the tables

for Run mode: "Radio is off".

• Minor updates in introductory text of Reference Oscillator Specification section. Also

updated typical value of TOSC to 680 μs in .

• Added 32 kHz Oscillator Frequency Specifications section.

• Updated Table 42 section.

• Added the following parameters: Switching Frequency, Half FET Threshold, Double

FET Threshold, DC-DC Conversion Efficiency, DCDC Settling Time for increasing

voltage and DCDC Settling Time for decreasing voltage.

• Updated Typ. value of the 'DCDC Turn on Time' parameter and added a footnote.

Rev 3 06/2017 Updated Typical values in Table 13 and Table 14.

Rev 2 03/2017 • Modified structure of the document to include orderable part numbers and Related

Resources table after the features list.

• Specified all supported part numbers on the front page.

• Specified the baudrate supported by FlexCAN in the features list.

• Updated value of minimum input voltage to 1.71 V and output voltage to 1.8 V from 2.7 V.

Also updated minimum voltage value in DCDC buck mode to 2.1 V from 2.7 V.

• Changed RSSI Range maximum value to 5 dBm in Table 3 and added the following

footnote: "With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input

losses.".

• Added Table 6 to show mapping relationship between TX_POWER and DBM. Also added

the corresponding graph.

• Added DCDC Inductor specifications in Table 41.

• Updated Table 42 :

• Removed repetitive fields from the table.

• Specified Typ. value of "DCDC Transition Operating Behavior" as 50 us.

• Updated footnote 3 as follows: "In Buck mode, the maximum VDD_1P8 output is the

minimum of either VDCDC_IN_BUCK minus 50 mV or 3 V. For example, if

VDCDC_IN = 1.85 V, maximum VDD_1P8 is 1.8 V. If VDCDC_IN = 4.2 V, maximum

VDD_1P8 is 3 V.".

• Replaced Laminate QFN with LQFN throughout.

• Added radio signals in Table 48.

• Added document numbers of the supported package drawings in Table 69.

• Added Part identification section.

Rev 1 01/2017 • Updated maximum supply voltage from 4.2 to 4.25 V.

• Corrected MBAN Channel numbering in Channel Plan for Bluetooth Low Energy.

• Corrected "Radio" description for VLLS1 and VLLS0 power modes in Table 8.

• Updated Section 9 Pin Diagrams and Pin Assignments.

• Corrected pin name from VDD_1P45OUT_PMCIN to VDD_1P5OUT_PMCIN

• Added ground pads in the pin diagrams

• Put Typ. values as TBDs in Table 14, Power consumption operating behaviors - Buck Mode.

• Added the following note in Diagram: Typical IDD_RUN operating behavior : "The results in

the following graphs are obtained using the device in Bypass mode."

• Put Typ. values as TBDs in Table 16, SoC Power Consumption.

• Added TOSC row in , Reference Crystal Specification.

• Added DCDC Transition Operating Behavior and DCDC Turn on Time in Table 42, DC-DC

Converter Specifications.

• Added the following note in Table 48 for the RF_TX_CONF pin: "This is a GPIO, not a

dedicated PIN."

Table continues on the next page...

Revision History

MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020 99

NXP Semiconductors

Table 71. Revision History (continued)

Rev. No. Date Substantial Changes

Rev 0 11/2016 Initial Internal Release

Revision History

100 MKW36A/35A/34A Data Sheet, Rev. 8, 05/2020

NXP Semiconductors

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