PESD3V3S2UT,215 - NXP - Datasheet.Support

DATA SH EET

Product data sheet

Supersedes data of 2003 Aug 20 2004 Apr 15

DISCRETE SEMICONDUCTORS

PESDxS2UT series

Double ESD protection diodes in

SOT23 package

2004 Apr 15 2

NXP Semiconductors Product data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

FEATURES

•Uni-directional ESD protec tion of up to two lines

•Max. peak pulse power: Ppp = 330 W at tp = 8/20 µs

•Low clamping voltage: V(CL)R = 20 V at Ipp = 18 A

•Ultra-lo w reverse leakage current: IRM < 700 nA

•ESD protection > 23 kV

•IEC 61000-4-2; level 4 (ESD)

•IEC 61000-4-5 (s urge); Ipp = 18 A at tp = 8/20 µs.

APPLICATIONS

•Computers and pe ripherals

•Communication syste ms

•Audio and video eq uipment

•High speed data lines

•Parallel ports.

DESCRIPTION

Uni-directional double ESD prote ction diodes in a SOT23

plastic pack ag e. Designed to protect up to two

transmission or da ta lines from ElectroStatic Di sc harge

(ESD) damage.

MARKING

Note

1. * = p : made in Hong Kong .

* = t : made in Malaysia.

* = W : made in China.

QUICK REFERENCE DATA

PINNING

TYPE NUMBER MARKING CODE(1)

PESD3V3S2UT *U9

PESD5V2S2UT *U1

PESD12VS2UT *U2

PESD15VS2UT *U3

PESD24VS2UT *U4

SYMBOL PARAMETER VALUE UNIT

VRWM reverse stand-off

voltage 3.3, 5.2, 12, 15

and 24 V

Cddiode capacitance

VR = 0 V;

f = 1 MHz

207, 152, 38, 32

and 23 pF

number of

protected lines 2

PIN DESCRIPTION

1cathode 1

2cathode 2

3common anode

sym022

001aaa49

Fig.1 Simplified outline (SOT23 ) and symbo l .

2004 Apr 15 3

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

ORDERING INFORMATION

LIMITING VALUES

In accordance with th e Absolute Maximum Rating System (IEC 60134).

Notes

1. Non-repetitive current pulse 8/20µ µs exponential decay waveform; see Fig.2.

2. Measured across either pins 1 and 3 or pins 2 and 3.

TYPE NUMBER PACKAGE

NAME DESCRIPTION VERSION

PESD3V3S2UT −plastic surface mounted package; 3 leads SOT23

PESD5V2S2UT

PESD12VS2UT

PESD15VS2UT

PESD24VS2UT

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

Ppp peak pulse power 8/20 µs pulse; notes 1 and 2

PESD3V3S2UT −330 W

PESD5V2S2UT −260 W

PESD12VS2UT −180 W

PESD15VS2UT −160 W

PESD24VS2UT −160 W

Ipp peak pulse current 8/20 µs pulse; notes 1 and 2

PESD3V3S2UT −18 A

PESD5V2S2UT −15 A

PESD12VS2UT −5 A

PESD15VS2UT −5 A

PESD24VS2UT −3 A

Tjjunction temperature −150 °C

Tamb operating ambient temperature −65 +150 °C

Tstg storage temperature −65 +150 °C

2004 Apr 15 4

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

ESD maximum ratings

Notes

1. Device stressed with ten non-repetitive ElectroStatic Discharge (ESD) pulses; see Fig.3.

2. Measured across either pins 1 and 3 or pins 2 and 3.

SYMBOL PARAMETER CONDITIONS VALUE UNIT

ESD electrostatic discharge

capability IEC 61000-4-2 (contact discharge);

notes 1 and 2

PESD3V3S2UT 30 kV

PESD5V2S2UT 30 kV

PESD12VS2UT 30 kV

PESD15VS2UT 30 kV

PESD24VS2UT 23 kV

HBM MIL-Std 883

PESDxS2UT series 10 kV

ESD standar ds compliance

ESD STANDARD CONDITIONS

IEC 61000-4-2 ; level 4 (ESD); see Fig.3 >15 kV (air); > 8 kV (contact)

HBM MIL-Std 883; class 3 >4 kV

handbook, halfpage

010

e−t

20 t (µs)

Ipp

(%)

120

MLE218

100 % Ipp; 8 µs

50 % Ipp; 20 µs

Fig.2 8/20 µs pulse waveform according to

IEC 61000-4-5.

001aaa19

Ipp

00 %

90 %

30 ns 60 ns

10 %

tr = 0.7 to 1 ns

Fig.3 ElectroStatic Discharge (ESD) pulse

waveform according to IEC 61000-4-2.

2004 Apr 15 5

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

ELECTRICAL CHARACTERISTIC S

Tj = 25 °C unless otherwise specified.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VRWM revers e stand-off voltage

PESD3V3S2UT − − 3.3 V

PESD5V2S2UT − − 5.2 V

PESD12VS2UT − − 12 V

PESD15VS2UT − − 15 V

PESD24VS2UT − − 24 V

IRM reverse leakage curre nt

PESD3V3S2UT VRWM = 3.3 V −0.7 2µA

PESD5V2S2UT VRWM = 5.2 V −0.15 1µA

PESD12VS2UT VRWM = 12 V −<0.02 1µA

PESD15VS2UT VRWM = 15 V −<0.02 1µA

PESD24VS2UT VRWM = 24 V −<0.02 1µA

VBR breakdown voltage IZ = 5 mA

PESD3V3S2UT 5.2 5.6 6.0 V

PESD5V2S2UT 6.4 6.8 7.2 V

PESD12VS2UT 14.7 15.0 15.3 V

PESD15VS2UT 17.6 18.0 18.4 V

PESD24VS2UT 26.5 27.0 27.5 V

Cddiode capacitance f = 1 MHz; VR = 0 V

PESD3V3S2UT −207 300 pF

PESD5V2S2UT −152 200 pF

PESD12VS2UT −38 75 pF

PESD15VS2UT −32 70 pF

PESD24VS2UT −23 50 pF

V(CL)R clamping voltage notes 1 and 2

PESD3V3S2UT Ipp = 1 A − − 7 V

Ipp = 18 A − − 20 V

PESD5V2S2UT Ipp = 1 A − − 9 V

Ipp = 15 A − − 20 V

PESD12VS2UT Ipp = 1 A − − 19 V

Ipp = 5 A − − 35 V

PESD15VS2UT Ipp = 1 A − − 23 V

Ipp = 5 A − − 40 V

PESD24VS2UT Ipp = 1 A − − 36 V

Ipp = 3 A − − 70 V

2004 Apr 15 6

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

Notes

1. Non-repetitive current pulse 8/20 µs exponential decay waveform; see Fig.2.

2. Measured either across pins 1 and 3 or pins 2 and 3.

Rdiff differential resistance

PESD3V3S2UT IR = 1 mA − − 400 Ω

PESD5V2S2UT IR = 1 mA − − 80 Ω

PESD12VS2UT IR = 1 mA − − 200 Ω

PESD15VS2UT IR = 1 mA − − 225 Ω

PESD24VS2UT IR = 0.5 mA − − 300 Ω

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

GRAPHICAL DATA

001aaa147

103

102

104

Ppp

(W)

tp (µs)

110

103

10 102

(1)

(2)

Fig.4 Peak pulse power dissipation as a function

of pulse time; typical values.

Tamb = 25 °C.

tp = 8/20 µs exponential decay waveform; see Fig.2.

(1) PESD3V3S2UT and PESD5V2S2UT.

(2) PESD12VS2UT, PESD15VS2UT, PESD24VS2UT

Tj (°C)

0 20015050 100

001aaa193

0.4

0.8

1.2

PPP

PPP(25°C)

Fig.5 Relative var iation of peak puls e power as a

function of junction temperature; typical

values.

2004 Apr 15 7

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

VR (V)

054231

001aaa148

120

160

200

240

(pF)

(1)

(2)

Fig.6 Diode capacitance as a function of reverse

voltage; typical values.

Tamb = 25 °C; f = 1 MHz.

(1) PESD3V3S2UT; VRWM = 3.3 V.

(2) PESD5V2S2UT; VRWM = 5 V.

VR (V)

0252010 155

001aaa149

(pF)

(1)

(3)

(2)

Fig.7 Diode capacitance as a function of reverse

voltage; typical values.

Tamb = 25 °C; f = 1 MHz.

(1) PESD12VS2UT; VRWM = 12 V.

(2) PESD15VS2UT; VRWM = 15 V.

(3) PESD24VS2UT; VRWM = 24 V.

2004 Apr 15 8

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

001aaa270

10−1

Tj (°C)

−100 150100050−50

IR(25˚C)

(1)

Fig.8 Relative variation of reverse leakage

current as a func tion of junction

temperature; typical values.

IR is less than 10 nA at 150 °C for:

PESD12V52UT; VRWM = 12 V.

PESD15VS2UT; VRWM = 15 V.

PESD24VS2UT; VRWM = 24 V.

(1) PESD3V3S2UT; VRWM = 3.3 V.

PESD5V2S2UT; VRWM = 5 V.

2004 Apr 15 9

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

001aaa49

450 Ω

50 Ω

Note 1: IEC61000-4-2 network

CZ = 150 pF; RZ = 330 Ω

D.U.T.: PESDxS2UT

RG 223/U

50 Ω coax

ESD TESTER 4 GHz DIGITAL

OSCILLOSCOPE

10×

ATTENUATOR

vertical scale = 200 V/div

horizontal scale = 50 ns/div vertical scale = 20 V/div

horizontal scale = 50 ns/div

vertical scale = 200 V/div

horizontal scale = 50 ns/div vertical scale = 10 V/div

horizontal scale = 50 ns/div

GND

unclamped +1 kV ESD voltage waveform

(IEC61000-4-2 network) clamped +1 kV ESD voltage waveform

(IEC61000-4-2 network)

unclamped −1 kV ESD voltage waveform

(IEC61000-4-2 network) clamped −1 kV ESD voltage waveform

(IEC61000-4-2 network)

note 1

PESD24VS2UT

PESD15VS2UT

PESD12VS2UT

PESD5V2S2UT

PESD3V3S2UT

Fig.9 ESD clamping test set-up an d waveforms.

2004 Apr 15 10

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

APPLICATION INFORMATION

The PESDxS2UT series is designed for uni-directional protection for up to two lines against damage caused by

ElectroStatic Discharge (ESD) and surge pulses. The PESDxS2UT series may be used on lines where the signal

polarities are below ground. PESDxS2UT series provide a surge capability of up to 330 W (Ppp) per line for an 8/20 µs

waveform.

Circuit board layout and protection device placement

Circuit board layout is critical for the suppression of ESD, Electrical Fast Transient (EFT) and surge transients. The

following guidelines are recommended:

•Place the PESDxS2UT as close as possible to the input terminal or connector.

•The path length between the PESDxS2UT and the protected line should be minimized.

•Keep parallel signal paths to a minimum.

•Avoid running protected conductors in parallel with unprotected conductors.

•Minimize all printed-circuit board conductive loops including po wer and ground loops.

•Minimize the length of transient return paths to ground .

•Avoid using shared return paths to a common gr ound point.

•Ground planes should be used whenev er possible. For multilayer printe d-circuit boards use ground vias.

001aaa49

PESDxS2UT

line 1 to be protected

unidirectional protection

of two lines bidirectional protection

of one line

line 2 to be protected

ground

PESDxS2UT

line 1 to be protecte

ground

Fig.10 Typical application: ESD protection of data lines.

2004 Apr 15 11

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

PACKAGE OUTLINE

UNIT A

max. b

cDE e

Qwv

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

04-11-04

06-03-16

IEC JEDEC JEITA

mm 0.1 0.48

0.38 0.15

0.09 3.0

2.8 1.4

1.2 0.95

1.9 2.5

2.1 0.55

0.45 0.1

0.2

DIMENSIONS (mm are the original dimensions)

0.45

0.15

SOT23 TO-236AB

detail X

0 1 2 mm

scale

1.1

0.9

Plastic surface-mounted package; 3 leads SOT2

2004 Apr 15 12

NXP Semiconductors Pr oduct data sheet

Double ESD protection diodes in SOT23

package PESDxS2UT series

DATA SHEET STATUS

Notes

1. Please consult the most recently issued document befor e initiating or co mpleting a design.

2. The product s ta tus of device(s) described in this do cument may have changed since this document was published

and may differ in case of multiple devices. The latest product status information is available on the Internet at

URL http://www.nxp.com.

DOCUMENT

STATUS(1) PRODUCT

STATUS(2) DEFINITION

Objective data sheet Development This document contains data from the objective specification for pro duct

development.

Preliminary data sheet Qualification This document contains data from the preliminary specification.

Product data sheet Production T his document contains the produc t s pecification.

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Limiting values ⎯ Stress above one or more limiting

values (as defined in the Absolute Maximum Ratings

System of IEC 60134) may cause permanent damage to

the device. Limiting values are stress ratin gs only and

operation of the device at these or any other conditions

above those given in the Characteristics sections of this

document is not implied. Exposure to limiting values for

extended periods may affect device reliability.

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This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal

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Printed in The Netherlands R76/03/pp13 Date of release: 2004 Apr 15 Document orde r number: 9397 750 12823