10/31/03
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AUTOMOTIVE MOSFET
PD - 94758
HEXFET® Power MOSFET
VDSS = 100V
RDS(on) = 26.5mΩ
ID = 36A
Specifically designed for Automotive applications,
this HEXFET® Power MOSFET utilizes the latest
processing techniques to achieve extremely low on-
resistance per silicon area. Additional features of
this design are a 175°C junction operating tempera-
ture, fast switching speed and improved repetitive
avalanche rating . These features combine to make
this design an extremely efficient and reliable device
for use in Automotive applications and a wide variety
of other applications.
S
D
G
Description
●Advanced Process Technology
●Ultra Low On-Resistance
●175°C Operating Temperature
●Fast Switching
●Repetitive Avalanche Allowed up to Tjmax
Features
IRF540Z
IRF540ZS
IRF540ZL
D2Pak
IRF540ZS
TO-220AB
IRF540Z TO-262
IRF540ZL
Absolute Maximum Ratings
Parameter Units
ID @ TC = 25°C Continuous Drai n Current, VGS @ 10V (Silicon Limited)
ID @ TC = 100°C Continuous Drai n Current, VGS @ 10V A
IDM
P
u
l
se
d
D
ra
i
n
C
urrent
c
PD @TC = 25°C Power Dissipation W
Linear Derating Fac t or W/°C
VGS Gate-to-Source Voltage V
EAS (Thermally limited)
Si
ng
l
e
P
u
l
se
A
va
l
anc
h
e
E
nergy
d
mJ
EAS (Tested )
Si
ng
l
e
P
u
l
se
A
va
l
anc
h
e
E
nergy
T
este
d
V
a
l
ue
h
IAR
A
va
l
anc
h
e
C
urrent
c
A
EAR
R
epet
i
t
i
ve
A
va
l
anc
h
e
E
nergy
g
mJ
TJ Operating Junction and
TSTG Storage Temperat ure Range °C
Soldering Temperat ure, for 10 sec onds
Mounting Torque, 6-32 or M 3 screw
i
Thermal Resistance Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 1.64 °C/W
RθCS Case-to-Si nk, Flat Greas ed Surface
i
0.50 –––
RθJA Junct i on-to-Ambient
i
––– 62
RθJA Junct i on-to-Ambient (P CB Mount)
j
––– 40
-55 to + 175
300 (1.6mm f rom case )
10 lbf
y
in (1.1N
y
m)
92
0.61
± 20
Max.
36
25
140
120
83
See Fig.12a, 12b, 15, 16
IRF540Z/S/L
2www.irf.com
S
D
G
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
V(BR)DSS Drai n-to-Source Breakdown Voltage 100 ––– ––– V
∆V(BR)DSS
/
∆TJ Breakdown Voltage Temp. Coeff i cient ––– 0.093 ––– V/°C
RDS(on) Static Drai n-t o -S ource On-Resis t ance ––– 21 26.5 mΩ
VGS(th) Gate Threshol d V ol tage 2.0 ––– 4.0 V
gfs Forward Transconductance 36 ––– ––– V
IDSS Drain-to-S ource Leakage Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leakage ––– ––– 200 nA
Gate-to-Source Reverse Leak age ––– ––– -200
QgTotal Gate Charge ––– 42 63
Qgs Gate-to-Source Charge ––– 9.7 ––– nC
Qgd Gate-to-Drain ("Miller") Charge ––– 15 –––
td(on) Turn-On Delay Time ––– 15 –––
trRise Time ––– 51 –––
td(off) Turn-Off Del ay Ti m e ––– 43 ––– ns
tfFall Time ––– 39 –––
LDInternal Drain I nductance ––– 4.5 ––– Between lead,
nH 6mm (0.25in.)
LSInternal Source Induct ance ––– 7.5 ––– from package
and center of di e contact
Ciss Input Capacit ance ––– 1770 –––
Coss Output Capacit ance ––– 180 –––
Crss Reverse Transfer Capacitance ––– 100 ––– pF
Coss Output Capacit ance ––– 730 –––
Coss Output Capacit ance ––– 110 –––
Coss eff. Effec t i ve Output Capac i tance ––– 170 –––
Source-Drain Ratin
s and Characteristics
Parameter Min. Typ. Max. Units
ISContinuous S ource Current ––– ––– 36
(Body Diode) A
ISM Pulsed S ource Current ––– ––– 140
(Body Diode)
c
VSD Diode Forward Voltage ––– ––– 1.3 V
trr Reverse Rec overy Time ––– 33 50 ns
Qrr Reverse Rec overy Charge ––– 41 62 nC
ton Forward Turn-On Time Intrinsic t urn-on t ime is negligible (t urn-on is dominat ed by LS+LD)
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
VGS = 0V, VDS = 80V, ƒ = 1.0MHz
VGS = 0V, VDS = 0V to 80V
f
VGS = 10V
e
VDD = 50V
ID = 22A
RG = 12 Ω
TJ = 25°C, IS = 22A, V GS = 0V
e
TJ = 25°C, IF = 22A, V DD = 50V
di/dt = 100A/µs
e
Conditions
VGS = 0V, ID = 250µA
Reference t o 25° C, ID = 1mA
VGS = 10V, ID = 22A
e
VDS = VGS, ID = 250µA
VDS = 100V, V GS = 0V
VDS = 100V, V GS = 0V, TJ = 125°C
MOSFET symbol
showing the
integral rev erse
p-n juncti on di ode.
VDS = 25V, I D = 22A
ID = 22A
VDS = 80V
Conditions
VGS = 10V
e
VGS = 0V
VDS = 25V
ƒ = 1.0MHz
VGS = 20V
VGS = -20V
IRF540Z/S/L
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Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Typical Forward Transconductance
Vs. Drain Current
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 25°C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
0 1 10 100
0.1 110 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (A)
60µs PULSE WIDTH
Tj = 175°C
4.5V
VGS
TOP 15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
4.0 5.0 6.0 7.0
VGS, Gate-to-Source Voltage (V)
1
10
100
1000
ID, Drain-to-Source Current (Α)
VDS = 25V
60µs PULSE WIDTH
TJ = 25°C
TJ = 175°C
0 1020304050
ID, Drain-t o-Source Current (A)
0
20
40
60
80
Gfs, Forward Transconductance (S)
TJ = 25°C
TJ = 175°C
VDS = 10V
380µs PULSE WIDTH
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Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drain-to-Source Voltage (V)
0
500
1000
1500
2000
2500
3000
C, Capacitance (pF)
Coss
Crss
Ciss
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
0 102030405060
QG Total Gate Charge (nC)
0
4
8
12
16
20
VGS, Gate-to-Source Voltage (V)
VDS= 80V
VDS= 50V
VDS= 20V
ID= 22A
FOR TEST CIRCUIT
SEE FIGURE 13
0.2 0.4 0.6 0.8 1.0 1.2 1.4
VSD, Source-toDrain Voltage (V)
0.1
1.0
10.0
100.0
1000.0
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
1 10 100 1000
VDS , Drain-toSource Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
Tc = 25°C
Tj = 175°C
Single Pulse
1msec
10msec
OPERATION IN T H IS AREA
LIM ITED BY RDS(on)
100µsec
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature Fig 10. Normalized On-Resistance
Vs. Temperature
25 50 75 100 125 150 175
TJ , Junction Temperature (°C)
0
10
20
30
40
ID , Drain Current (A)
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperature (°C)
0.5
1.0
1.5
2.0
2.5
3.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 22A
VGS = 10V
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Durati on (sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGL E PU LSE
( THERM AL R ESPO N SE )
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QG
QGS QGD
VG
Charge
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 14. Threshold Voltage Vs. Temperature
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
-75 -50 -25 025 50 75 100 125 150 175
TJ , Temperature ( °C )
1.5
2.0
2.5
3.0
3.5
4.0
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1K
VCC
DUT
0
L
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
20
40
60
80
100
120
140
160
180
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 8.3A
14A
BOTTOM20A
IRF540Z/S/L
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Fig 15. Typical Avalanche Current Vs.Pulsewidth
Fig 16. Maximum Avalanche Energy
Vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 15, 16:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a
temperature far in excess of Tjmax. This is validated for
every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is
not exceeded.
3. Equation below based on circuit and waveforms shown in
Figures 12a, 12b.
4. PD (ave) = Average power dissipation per single
avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for
voltage increase during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed
Tjmax (assumed as 25°C in Figure 15, 16).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see figure 11)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ Z thJC
Iav = 2DT/ [1.3·BV· Zth]
EAS (AR) = PD (ave)·tav
1.0E-08 1.0E-07 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
0.1
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs
avalanche pulsewidth, tav
assuming ∆Tj = 25°C due to
avalanche losses
0.01
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
10
20
30
40
50
60
70
80
90
100
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 10% Duty Cycle
ID = 20A
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Fig 17. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RG
D.U.T.
10V
+
-
VDD
Fig 18a. Switching Time Test Circuit
Fig 18b. Switching Time Waveforms
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TO-220AB Package Outline
Dimensions are shown in millimeters (inches)
LEAD ASSI GNM ENTS
1 - GATE
2 - DRAIN
3 - SOURCE
4 - DRAIN
- B -
1.32 (.052)
1.22 (.048)
3X 0.55 (.022 )
0.46 (.018 )
2.92 (.1 1 5)
2.64 (.1 0 4)
4.69 (.185)
4.20 (.165)
3X 0.93 (.037)
0.69 (.027)
4.06 (.160)
3.55 (.140)
1.15 (.045)
MIN
6.47 (.255)
6.10 (.240)
3.78 (.149)
3.54 (.139)
- A -
10. 54 (.41 5)
10. 29 (.40 5)
2.87 (.113)
2.62 (.103)
15.24 (.600)
14.84 (.584)
14.09 (.555)
13.47 (.530)
3X 1.40 (.055)
1.15 (.045)
2.54 (.100)
2X
0.36 (.014) M B A M
4
1 2 3
NOTES:
1 DIMENSIONING & T OLERANCING PER ANSI Y14.5M, 1982. 3 OUTLINE CONFORMS TO JEDEC OUTLINE TO-220AB.
2 CONTROLLING DIMENSION : INCH 4 HEATSINK & LEAD MEASUREMENTS DO NOT INCLUDE BURRS.
TO-220AB Part Marking Information
EXAMPLE:
IN THE ASSEMBLY LINE "C"
THIS IS AN IRF1010
LOT CODE 1789
ASS EMBLE D ON WW 19, 1997 PART NUMBER
ASSEMBLY
LOT CODE
DAT E CODE
YEAR 7 = 1997
LINE C
WEEK 19
LOGO
RECT IFIER
INTERNATIONAL
EXAMPLE: T HIS IS AN IRF1010
LOT CODE 1789
ASS EMBLE D ON WW 19, 1997
IN THE ASSEMBLY LINE "C"
INTERNATIONAL
RECTIFIER
LOGO
LOT CODE
PART NUMBER
DAT E CODE
For GB Production
IRF540Z/S/L
10 www.irf.com
D2Pak Part Marking Information
F 530S
T HIS IS AN IRF 530S WIT H
LOT CODE 8024
AS S E MBLE D ON WW 02, 2000
IN THE ASSEMBLY LINE "L"
ASSEMBLY
LOT CODE
INTERNATIONAL
RECT IF IER
LOGO
PART NUMBER
DAT E CODE
YEAR 0 = 2000
WEEK 02
LINE L
D2Pak Package Outline
Dimensions are shown in millimeters (inches)
DAT E CODE
IN THE ASSEMBLY LINE "L"
AS S E MB LE D ON WW 02, 2000
T HIS IS AN IRF 530S WIT H
LOT CODE 8024 INTERNATIONAL
LOGO
RECT IF IER
LOT CODE
PART NUMBER
F 530S
For GB Production
IRF540Z/S/L
www.irf.com 11
TO-262 Package Outline
Dimensions are shown in millimeters (inches)
TO-262 Part Marking Information
EXA
MPLE:THIS IS A
N IRL3103L
LO
T C
O
DE 1789
A
SSEMBLY
PA
RT NUM
BER
DA
TE C
O
DE
W
EEK 19
LINE C
LOT C
O
DE
YEA
R 7 = 1997
A
SSEMBLED ON W
W 19, 1997
IN THE A
SSEMBLY LINE "C
"LO
G
O
REC
TIFIER
INTERNA
TIO
NA
L
IGBT
1- GATE
2- COLLEC-
TOR
IRF540Z/S/L
12 www.irf.com
Data and specifications subject to change without notice.
This product has been designed and qualified for the Automotive [Q101]market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 10/03
TO-220AB package is not recommended for Surface Mount Application.
Repetitive rating; pulse width limited by
max. junction temperature. (See fig. 11).
Limited by TJmax, starting TJ = 25°C, L = 0.46mH
RG = 25Ω, IAS = 20A, VGS =10V. Part not
recommended for use above this value.
Pulse width ≤ 1.0ms; duty cycle ≤ 2%.
Coss eff. is a fixed capacitance that gives the
same charging time as Coss while VDS is rising
from 0 to 80% VDSS .
Notes:
Limited by TJmax , see Fig.12a, 12b, 15, 16 for typical repetitive
avalanche performance.
This value determined from sample failure population. 100%
tested to this value in production.
This is only applied to TO-220AB pakcage.
This is applied to D2Pak, when mounted on 1" square PCB (FR-
4 or G-10 Material). For recommended footprint and soldering
techniques refer to application note #AN-994.
D2Pak Tape & Reel Information
3
4
4
TRR
FEED DIRECTION
1.85 (.073)
1.65 (.065)
1.60 (.063)
1.50 (.059)
4.10 (. 1 61 )
3.90 (. 1 53 )
TRL
FEED DIRECTION
10.90 (. 429)
10.70 (. 421) 16.10 (. 634 )
15.90 (. 626 )
1.75 (.069)
1.25 (.049)
11.60 (.457)
11.40 (.449) 15.42 (.609)
15.22 (.601)
4.72 (.136)
4.52 (.178)
24.30 (.957)
23.90 (.941)
0.368 (. 01 45)
0.342 (. 01 35)
1.60 (.0 63)
1.50 (.0 59)
13.50 (.532)
12.80 (.504)
330.00
(14.173)
MAX.
27.40 (1.079)
23.90 (.941)
60.00 (2.362)
MIN.
30.40 (1.197)
MAX.
26.40 (1.039)
24.40 (.961)
NOTES :
1. COMFORMS TO EIA-418.
2. CONTROLLI NG DIMENSI O N: MILLIMETER.
3. DIMENSION MEASURED @ HUB.
4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/