K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
1M x 16 SDRAM
Revision 1.1
Jan 2003
512K x 16bit x 2 Banks
Synchronous DRAM
LVTTL
Samsung Electronics res erves the right to change products or specification with ou t notic e.
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
The K4S161622E is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Dual banks operation
• MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst Read Single-bit Write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle (2K/32ms)
GENERAL DESCRIPTIONFEATURES
FUNCTIONAL BLOCK DIAGRAM
512K x 16Bit x 2 Banks Synchronous DRAM
ORDERING INFORMATION
Part NO. MAX Freq. Interface Package
K4S161622E-TC55 183MHz
LVTTL 50
TSOP(II)
K4S161622E-TC60 166MHz
K4S161622E-TC70 143MHz
K4S161622E-TC80 125MHz
K4S161622E-TC10 100MHz
* Samsung Electronics reserves the right to change products or specification without notice.
Bank Select
Data Input Register
512K x 16
512K x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
Timing Register
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
VDD
DQ0
DQ1
VSSQ
DQ2
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
PIN CONFIGURATION (TOP VIEW)
VSS
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
DQ11
DQ10
VSSQ
DQ9
DQ8
VDDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
VSS
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
Pin Name Input Function
CLK System Clock Active on the positive going edge to sample all inputs.
CS Chip Select Disables or enables device operation by maski ng or enabling all input s except
CLK, CKE and L(U)DQM
CKE Clock Enable Masks system clock to freez e operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP Address Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, column address : CA0 ~ CA7
BA Bank Select Address Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE Write Enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
L(U)DQM Data Input/Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
DQ0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU No Connection/
Reserved for Future Use This pin is recommended to be left No Connection on the device.
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Value Unit
Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD1W
Short circuit current IOS 50 mA
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Note :
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)
Parameter Symbol Min Typ Max Unit Note
Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high votlage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL --0.4VIOL = 2mA
Input leakage current ILI -10 - 10 uA 3
Note :
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin Symbol Min Max Unit
Clock CCLK 24pF
RAS, CAS, WE, CS, CKE, L(U)DQM CIN 24pF
Address CADD 24pF
DQ0 ~ DQ15 COUT 35pF
1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
:
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitan ce added to power line at board.
Parameter Symbol Value Unit
Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF
Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF
1. VDD and VDDQ pins are separated each other.
All VDD pins are connected in chip. All VDDQ pins are connected in chip.
2. VSS and VSSQ pins are separated each other
All VSS pins are connected in chip. All VSSQ pins are connected in chip.
Note :
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4S161622E-TC**
Note :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)
Parameter Symbol Test Condition CAS
Latency
Version Unit Note
-55 -60 -70 -80 -10
Operating Current
(One Bank Active) ICC1 Burst Length =1
tRC≥tRC(min)
Io = 0 mA
3 120 115 105 95 85 mA 2
2--95 95 80
Precharge Standby Current
in power-down mode ICC2PCKE≤VIL(max), tCC = 15ns 2 mA
ICC2PS CKE & CLK≤VIL(max), tCC = ∞2
Precharge Standby Current
in non power-down mode
ICC2NCKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns 15 mA
ICC2NS CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable 5
Active Standby Current
in power-down mode ICC3PCKE≤VIL(max), tCC = 15ns 3 mA
ICC3PS CKE & CLK≤VIL(max), tCC = ∞3
Active Standby Current
in non power-down mode
(One Bank Active)
ICC3NCKE≥VIH(min), CS≥VIH(min), tCC = 15ns
Input signals are changed one time during 30ns 25 mA
ICC3NS CKE≥VIH(min), CLK≤VIL(max), tCC = ∞
Input signals are stable 15 mA
Operating Current
(Burst Mode) ICC4 Io = 0 mA
Page Burst 2Banks Activated
tCCD = 2CLKs
3 155 150 140 130 115 mA 2
2--115 115 100
Refresh Current ICC5 tRC≥tRC(min) 3 105 100 90 90 80 mA 3
2--90 90 80
Self Refresh Current ICC6 CKE≤0.2V 1 mA 4
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V, TA = 0 to 70°C)
Parameter Value Unit
Input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2
3.3V
1200Ω
870Ω
Output VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA
Vtt=1.4V
50Ω
Output Z0=50Ω
(Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit
50pF 50pF
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer . Refer to the following clock unit based AC conversion table
Notes :
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter Symbol Version Unit Note
-55 -60 -70 -80 -10
CAS Latency CL 3232323232CLK
CLK cycle time tCC(min) 5.5 10 6 10 7 10 8 10 10 12 ns
Row active to row active delay tRRD(min) 2CLK 1
RAS to CAS delay tRCD(min) 3332323222CLK 1
Row precharge time tRP(min) 3332323222CLK 1
Row active time tRAS(min) 7775756554CLK 1
tRAS(max) 100 us
Row cycle time tRC(min) 101010 7 10 7 9 7 7 6 CLK 1
Last data in to row precharge tRDL(min) 1 CLK 2, 5
Last data in to new col.address delay tCDL(min) 1CLK2
Last data in to burst stop tBDL(min) 1CLK2
Col. address to col. address delay tCCD(min) 1CLK
Mode Register Set cycle time tMRS(min) 2CLK
Number of valid output
data CAS Latency=3 2 ea 4
CAS Latency=2 1
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
Parameter Symbol -55 -60 -70 -80 -10 Unit Note
Min Max Min Max Min Max Min Max Min Max
CLK cycle time CAS Latency=3 tCC 5.5 1000 61000 71000 81000 10 1000 ns 1
CAS Latency=2 - - 10 10 12
CLK to valid
output delay CAS Latency=3 tSAC - 5 -5.5-5.5- 6 - 6ns 1, 2
CAS Latency=2 - 6 - 6 - 6 - 6 - 8
Output data tOH 2 - 2.5 - 2.5 - 2.5 - 2.5 - ns 2
CLK high pulse
width CAS Latency=3 tCH 2-2.5 -3-3-3.5-ns3
CAS Latency=2 3 3
CLK low pulse
width CAS Latency=3 tCL 2-2.5 -3-3-3.5-ns3
CAS Latency=2 3 3
Input setup time CAS Latency=3 tSS 1.5 -1.5 -1.75 -2-2.5-ns3
CAS Latency=2 2 2 2
Input hold time tSH 1-1-1-1-1- ns3
CLK to output in Low-Z tSLZ 1-1-1-1-1-ns2
CLK to output
in Hi-Z CAS Latency=3 tSHZ - 5 - 5.5 - 5.5 - 6 - 6 ns
CAS Latency=2 - 6 - 6 - 6 - 6 - 8
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J".
From the next generation, tRDL will be only 2CLK for every clock frequency.
Parameter Symbol Version Unit
-55 -60 -70 -80 -10
CLK cycle time tCC(min) 5.5 6 7 8 10 ns
Row active to row active delay tRRD(min) 11 12 14 16 20 ns
RAS to CAS delay tRCD(min) 16.5 18 20 20 20 ns
Row precharge time tRP(min) 16.5 18 20 20 20 ns
Row active time t RAS(min) 38.5 42 49 48 48 ns
tRAS(max) 100 us
Row cycle time tRC(min)55606970 70ns
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
SIMPLIFIED TRUTH TABLE
(V=V alid, X=Don′t Care, H=Logic High, L=Logic Low)
COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~ A0Note
Register Mode Register Set H X L L L L X OP CODE 1, 2
Refresh
Auto Refresh HHLL LHX X 3
Self
Refresh
Entry L 3
Exit L H LHHHXX3
HX XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Read &
Column Address Auto Precharge Disable HXLHLHXV
LColumn
Address
(A0~A7)
4
Auto Precharge Enable H 4, 5
Write &
Column Address Auto Precharge Disable HXLHLLXV
LColumn
Address
(A0~A7)
4
Auto Precharge Enable H 4, 5
Burst Stop H X L H H L X X 6
Precharge Bank Selection HXLLHLX
VL X
Both Banks X H
Clock Suspend or
Active Power Down Entry H L HX XXXX
LVVV
Exit L H X X X X X
Precharge Power Down Mode
Entry H L HX XXX
X
LHHH
Exit L H HX XXX
LVVV
DQM H V X 7
No Operation Command H X HX XXXX
LHHH
1. OP Code : Operand Code
A0 ~ A10/AP, BA : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued on ly at both banks precharge state.
4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A10/AP is "High" at row precharge, BA is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Note :
X
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function A10/AP
RFU A9
W.B.L A8A7
TM A6A5A4A3A2A1A0
CAS Latency BT Burst Length
A8A7A6A5A4A3A2A1A0BT = 0
Test Mode Type
Mode Register Set
Reserved
Reserved
Reserved
0
0
1
1
0
1
0
1
Write Burst Length
A9
0
1
Length
Burst
Single Bit
Latency
Reserved
-
2
3
Reserved
Reserved
Reserved
Reserved
CAS Latency
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Burst Type
0
1
BT = 1
Burst Length
Type
Sequential
Interleave 0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
Reserved
Reserved
Reserved
Full Page
1
2
4
8
Reserved
Reserved
Reserved
Reserved
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manne r to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now ready for normal o peration.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
Full Page Length : x4 (1024), x8 (512), x16 (256)
BA
RFU
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address Sequential Interleave
A1A0
0
0
1
1
0
1
0
1
0
1
2
3
1
2
3
0
2
3
0
1
3
0
1
2
0
1
2
3
1
0
3
2
2
3
0
1
3
2
1
0
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address Sequential Interleave
0
0
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2
3
4
5
6
7
0
1
4
5
6
7
0
1
2
3
6
7
0
1
2
3
4
5
A1A0A2
0
0
1
1
0
0
1
1
1
2
3
4
5
6
7
0
3
4
5
6
7
0
1
2
5
6
7
0
1
2
3
4
7
0
1
2
3
4
5
6
0
1
2
3
4
5
6
7
2
3
0
1
6
7
4
5
4
5
6
7
0
1
2
3
6
7
4
5
2
3
0
1
1
0
3
2
5
4
7
6
3
2
1
0
7
6
5
4
5
4
7
6
1
0
3
2
7
6
5
4
3
2
1
0
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
DEVICE OPERATIONS
ADDRESS INPUTS (A0 ~ A10/AP)
: In case x 4
The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 10 bit column
addresses are latched along with CAS, WE and BA during read
or write command.
: In case x 8
The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 9 bit column addresses
are latched along with CAS, WE and BA during read or write
command.
: In case x 16
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10/
AP). The 11 bit row addresses are latched along with RAS and
BA during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA during read or write
command.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin-
gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
POWER-UP
SDRAMs must be powered up and initialized in a pre-
defined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode reg-
ister.
cf.) Sequence of 4 & 5 is regardless of the order.
The device is now read y for normal operation.
CLOCK (CLK)
The clock input is used as the reference for all SDRAM opera-
tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro-
zen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle st ate and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + tSS" before the high going edge
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.
BANK ADDRESS (BA)
: In case x 4
This SDRAM is organized as two independent banks of
2,097,152 words x 4 bits memory arrays. The BA input is latched
at the time of assertion of RAS and CAS to select the bank to be
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.
: In case x 8
This SDRAM is organized as two independent banks of
1,048,576 words x 8 bits memory arrays. The BA input is latched
at the time of assertion of RAS and CAS to select the bank to be
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.
: In case x 16
This SDRAM is organized as two independent banks of 524,288
words x 16 bits memory arrays. The BA input is latched at the
time of assertion of RAS and CAS to select the bank to be used
for the operation. The bank select BA is latched at bank active,
read, write, mode register set and precharge operations.
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ A10/AP and BA in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode
register. T wo clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A0 ~ A2, burst type uses
A3, CAS latency (read latency from column address) uses A4 ~
A6, vendor specific options or test mode use A7 ~ A8, A10/AP
and BA. The write burst length is programmed using A9. A7 ~ A8,
A10/AP, BA must be set to low for normal SDRAM operation.
Refer to the table for specific codes for various burst length,
burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of tRCD(min) from the time
of bank activation. tRCD is an internal timing parameter of
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD(min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SDRAM has two
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of two banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before the other bank can be sensed
reliably. tRRD(min) specifies the minimum time required between
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be
active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS(min). Every SDRAM bank
activate command must satisfy tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on con-
secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read com-
mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com-
mand is determined by the mode register which is already pro-
grammed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of out-
puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserti ng low on CS, C AS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com-
pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM
OPERATION also.
DEVICE OPERATIONS (Continued)
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA of the
bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when both banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using pre-
charge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after both banks have satisfied tRAS(min)
requirement, performs precharge on both banks. At the end of
tRP after performing precharge to all the banks, both banks are
in idle state.
DEVICE OPERATIONS (Continued)
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh com-
mand can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by tRFC(min). The minimum number of
clock cycles required can be calculated by driving tRFC with
clock cycle time and them rounding up to the next higher integer.
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. Both banks will be in the
idle state at the end of auto refresh operation. The auto refresh
is the preferred refresh mode when the SDRAM is being used
for normal data transactions. The auto refresh cycle can be per-
formed once in 15.6us or a burst of 2048 auto refresh cycles
once in 32ms.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from both banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of t RFC before the SDRAM reaches idle state to
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 2048
auto refresh cycles immediately after exiting in self refresh
mode.
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
1) Clock Suspended During Write (BL=4)
1. CLOCK Suspend
WR
D0D1D2D3
D0D1D2D3
CLK
CMD
CKE
Internal
CKE
DQ(CL2)
DQ(CL3)
Masked by CKE
2) Clock Suspended During Read (BL=4)
D0
Not Written
1) Write Mask (BL=4)
2. DQM Operation
WR
D0D1D3
D0D1D3
CLK
CMD
DQM
DQ(CL2)
DQ(CL3)
Masked by DQM
2) Read Mask (BL=4)
RD
Q0Q2Q3
Q1Q2Q3
Masked by DQM
DQM to Data-in Mask = 0 DQM to Data-out Mask = 2
Hi-Z
Hi-Z
3) DQM with Clock Suspende d (Full Page Read) Note 2
RD
CLK
CMD
CKE
DQ(CL2)
DQ(CL3)
Q0Q4Q7Q8Q2
Q3Q6Q7Q1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
DQM
*Note : 1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and dat a-out.
BASIC FEATURE AND FUNCTION DESCRIPTIONS
RD
Q0Q1Q2
Q0Q1Q2Q3
Masked by CKE
Q3
Suspended Dout
Q6
Q5
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
1) Read interrupted by Read (BL=4)
3. CAS Interrupt (I)
CLK
CMD
ADD
Note 1
RD RD
A B
QA0QB1QB2QB3QB0
QA0QB1QB2QB3QB0
tCCD
Note 2
2) Write interrupted b y Wri te (BL=2) 3) Write interrupted by Re ad (BL=2)
WR WR
A B
tCCD Note 2
DA0DB1DB0
tCDL
Note 3
CLK
CMD
ADD
DQ
WR RD
A B
tCCD Note 2
tCDL
Note 3
DA0QB1QB0
DA0QB1QB0
DQ(CL2)
DQ(CL3)
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD : CAS to CAS delay. (=1CLK)
3. tCDL : Last data in to new column address del ay. (=1CLK)
DQ(CL2)
DQ(CL3)
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
D1D2
RD
D3
WR
D0
D1D2D3D0
D1D2D3D0
RD WR
RD WR
Hi-Z
Hi-Z
RD WR
Q0D1D2D3D0
Note 1
Hi-Z
(a) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
(b) CL=3, BL=4
CLK
i) CMD
DQM
DQ D1D2
RD
D3
WR
D0
D1D2D3D0
D1D2D3D0
RD WR
RD WR
D1D2D3
D0
RD WR
RD WR
D1D2D3D0
Hi-Z
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ Q0Note 1
Hi-Z
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
*Note : 2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only the other bank prechar ge of dual banks operation.
5. Wr ite Interrupted by Precha rge & DQM
D0D1D2
CLK
CMD
DQM
DQ
Masked by DQM
WR PRE
D3
Note 3
Note 2
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
*Note : 1. tRDL : Last dat a in to row precharge delay
2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respe c tively.
3. The row active command of the precharge bank can be issued after t RP from this point.
The new read/write command of the other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.
6. Precharge
D0D1D2
CLK
CMD
DQ
WR PRE
D3
1) Normal Write (BL=4 )
tRDL
Note 2
2) Normal Read (BL =4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD PRE
Q0Q1Q2Q3
Q0Q1Q2Q3
1
2
Note 2
7. Auto Precharge
D0D1D2
CLK
CMD
DQ
WR
D3
1) Normal Writ e ( B L=4 )
Note 3
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD
Q0Q1Q2Q3
Q0Q1Q2Q3
Note 3
Auto Precharge Starts
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
*Note : 1. tRDL : 1 CLK
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : Both banks precharge if necessary.
MRS can be issued only at both banks precharg e state.
8. Burst Stop & Interrupted by Precharge
D0D1D2
CLK
CMD
DQ
WR PRE
D3
1) Normal Write (BL=4 )
tRDL Note 1
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD PRE
Q0Q1
Q0Q1
1
2
Note 3
9. MRS
CLK
PRE
1) Mode Register Set
D0D1D2
CLK
CMD
DQ
WR STOP
D3
2) Write Burst Stop (BL=8)
DQM
4) Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RD STOP
Q0Q1
Q0Q1
1
2
Note 3
MRS ACT
Note 4
tRP tMRS = 2CLK
CMD
DQM
tBDL Note 2
D4D5
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
*Note : 1. Active power down : one or both banks active state.
2. Precharge power down : both banks prech arge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, both banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refre sh operation are perfomed internally.
After self re fr esh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refre sh exit command, any other command can not be accepted. Before/Af te r self refresh mode , burst
auto refresh cycle (2048 cycles) is recommended.
10. Clock Suspend Exit & Power Down Exit
CLK
CKE
CMD RD
1) Clock Suspend (=Active Power Do wn) Exit
tSS
CLK
CKE
CMD
2) Power Down (=Precharg e Power Down)
Note 1
Note 5
Internal
CLK
NOP
tSS
Note 2
Internal
CLK
11. Auto Refresh & Self Refresh
CLK
CMD
1) Auto Refresh & Self Refresh
CKE
PRE AR CMD
Note 4
tRP tRFC
¡ó
¡ó
¡ó
¡ó
CLK
CMD
2) Self Refresh
CKE
PRE SR CMD
Note 4
tRP tRFC
¡ó
¡ó
Note 6
Note 3
¡ó
ACT
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
12. About Burst Type Control
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page.At Full page wrap-around.
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Countin g
Every cycle Read/Write Co mmand with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Basic
MODE
Random
MODE
Sequential Counting
Interleave Counting
Random column Access
tCCD = 1 CLK
13. About Burst Length Control
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respec tively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Basic
MODE
Interrupt
MODE
1
2
RAS Interrupt
(Interrupted by Precharge)
At MRS A2,1,0 = "010".
At MRS A2,1,0 = "011 ".
At MRS A2,1,0 = "111".
Wrap arou nd mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.
4
8
Full Page
At MRS A9 = "1".
Read burst=1,2,4,8,full page Write burst=1
At auto precharge of write, tRAS should not be violate
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
BRSW
Burst Stop
CAS Interrupt
Random
MODE
Special
MODE
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
X
X
X
CA, A10/AP
RA
A10/AP
X
OP code
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
RA, RA10
X
X
X
X
CA, A10/AP
RA, RA10
X
X
X
X
CA
RA
A10/AP
FUNCTION TRUTH TABLE (TABLE 1)
Current
State CS RAS CAS WE BA ADDR ACTION Note
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Pre-
charging
NOP
NOP
ILLEGAL
ILLEGAL
Row (& Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
Begin Read ; latch CA ; determine AP
Begin Write ; latch CA ; determine AP
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRP
NOP --> Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRPL
X
X
X
BA
BA
BA
X
OP code
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
BA
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
H
L
X
H
H
L
H
L
X
H
H
L
H
H
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
X
H
L
X
H
L
2
2
4
5
5
2
2
3
2
3
3
2
3
2
2
2
2
2
4
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
FUNCTION TRUTH TABLE (TABLE 1)
Current
State CS RAS CAS WE BA ADDR ACTION Note
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
Row
Activating
Refreshing
ILLEGAL
NOP --> Row Active after t RCD
NOP --> Row Active after t RCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRFC
NOP --> Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after 2 clocks
NOP --> Idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
2
2
2
2
Mode
Register
Accessing
*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.
2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
Abbreviations : RA = Row Address BA = Bank Address
NOP = No Operation Command CA = Column Address AP = Auto Precharge
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
FUNCTION TRUTH TABLE (TABLE 2)
Current
State CS RAS CAS WE ADDR ACTION Note
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
OP Code
X
X
X
X
X
Self
Refresh
INVALID
Exit Self Refresh --> Idle after tRFC (ABI)
Exit Self Refresh --> Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mod e)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
6
6
7
7
8
8
8
9
9
All
Banks
Idle
*Note : 6. CKE low to high transition is asynchrono us.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setu p time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the both ban ks idle state.
9. Must be a legal command.
Abbreviations : ABI = All Banks Idle, RA = Row Address
CKE
(n-1)
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L
X
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
CKE
n
All
Banks
Precharge
Power
Down
Any State
other than
Listed
above
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
: Don't care
tRCD
*Note 1
tSS
tSH
tRP
tCCD
tSS
tSH
tRAC tSAC
tSLZ tOH
tSH
tSS
tSS
tSH
tSS tSH
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
A10/AP
DQ
WE
DQM
Row Active Read Write Read Row Active
Precharge
tCH
tCC tCL
tRAS
tRC
HIGH
tSH
tSH
tSS
tSS
*Note 2,3 *Note 2,3 *Note 4
*Note 4*Note 3*Note 3*Note 3
RbCcCbCaRa
BS BS BS BS BS BS
Ra Rb
QcDbQa
*Note 2,3*Note 2 *Note 2
tSS
tSH
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
*Note : 1. All inputs expect CKE & DQM can be don ¡Çt care when CS is high at the CLK high going edge.
2. Bank active & read/write are controlled by BA.
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.
BA
0
1
0
1
Operation
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
4. A10/AP and BA control bank precharge when precharge command is asserted.
A10/AP
BA
0
1
Active & Read/Write
Bank A
Bank B
BA
0
1
X
Precharge
Bank A
Bank B
Both Banks
A10/AP
0
0
1
0
1
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Power Up Sequence
: Don't care
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
A10/AP
DQ
WE
DQM
Precharge Auto Refresh Auto Refresh Mode Register Set
Row Active
RAa
RAa
(All Banks)
(A-Bank)
tRP tRC
High leve l is ne c essary
High-Z
High leve l is ne c essary
tRC
Key
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Read & Write Cycle at Same Bank @Burst Length=4
HIGH
Row Active
(A-Bank) Precharge
(A-Bank) Row Active
(A-Bank) Write
(A-Bank) Precharge
(A-Bank)
: Don't care
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output dat a
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z af ter the end of burst. (1, 2, 4, 8 & Full page bit burst wrap-around).
Read
(A-Bank)
*Note 1
tRC
tRCD
*Note 2
tRDL
tRDL
tSHZ *Note 4
tSHZ *Note 4
tOH
tRAC
*Note 3 tSAC
tSAC
tRAC
*Note 3
tOH
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
Ra Rb
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
Ra Ca0 Rb Cb0
WE
DQM
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Page Read & Write Cycle at Same Bank @Burst Length=4
HIGH
Row Active
(A-Bank) Read
(A-Bank) Write
(A-Bank) Precharge
(A-Bank)
: Don't care
*Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asse rti ng precharge
before end of burst. Input data after Row precharge cycle will be masked internall y.
Read
(A-Bank)
tRCD
*Note 2
tRDL
*Note 1 *Note 3
tCDL
Qa0 Qa1 Qb0 Qb1 Qb2
Qa0 Qa1 Qb0 Qb1
Dc0 Dc1 Dd0 Dd1
Dc0 Dc1 Dd0 Dd1
Write
(A-Bank)
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Ra Ca0 Cb0 Cc0 Cd0
Ra
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Page Read Cycle at Different Bank @Burst Length=4
HIGH
Row Active
(A-Bank) Row Active
(B-Bank) Read
(A-Bank) Read
(B-Bank)
: Don't care
*Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege.
2. To interrupt a burst read by row precharge, both the rea d and the precharge banks must be the same.
Read
(A-Bank)
*Note 2
*Note 1
Read
(B-Bank) Read
(A-Bank) Precharge
(A-Bank)
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
RAa RBb
RAa RBb
CAa CBb CBd
CAc CAe
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Page Write Cycle at Different Bank @Burst Length=4
HIGH
Row Active
(A-Bank) Row Active
(B-Bank) Write
(A-Bank)
Write
(B-Bank)
: Don't care
*Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge ban ks must be the same.
Write
(A-Bank)
tRDL
Precharge
(Both Banks)
tCDL
Write
(B-Bank)
*Note 1
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A10/AP
RAa CAa CBb CAc CBd
RAa
*Note 2
DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1
RBb
RBb
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Read & Write Cycle at Different Bank @Burst Length=4
HIGH
Row Active
(A-Bank) Write
(B-Bank)
Row Active
(A-Bank)
: Don't care
*Note : 1. tCDL shoul d be met to complete write.
Read
(A-Bank)
*Note 1
tCDL
Row Active
(B-Bank)
Precharge
(A-Bank) Read
(A-Bank)
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
QAc0 QAc1 QAc2
QAc0 QAc1
RAa CAa RBb CBb RAc CAc
RAcRAa RBb
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Read & Write Cycle with Auto Precharge I @Burst Length=4
HIGH
Row Active
(A-Bank)
: Don't care
*Note: * When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Row Active
(B-Bank)
Read with
Auto Pre
charge
(A-Bank)
Write with
Auto Precharge
(A-Bank)
Row Active
(A-Bank)
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Qa0 Qa1 Qb0 Qb1
Qa0 Qa1 Qb0 Qb1
Ra Rb Ca
Ra Rb
Ra
Cb
Qb2 Qb3
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank)*
Precharge
(B-Bank)
Ca
Ra
Da0 Da1
Da0 Da1
Qb2 Qb3
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Read & Write Cycle with Auto Precharge II @Burst Length=4
HIGH
Row Active
(A-Bank)
: Don't care
*Note : * Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
Read with
Auto Precharge
(A-Bank)
Auto Precharge
Start Point
(A-Bank)
Row Active
(B-Bank)
Read with
Auto Precharge
(B-Bank)
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Qa0 Qa1 Qa2 Qa3
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
Qb0 Qb1 Qb2 Qb3
Ra Ca
Ra
Cb
Rb
Rb
*
Auto Precharge
Start Point
(B-Bank)
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4
Row Active Clock
Suspension Read Write
DQM
: Don't care
Clock
Suspension
Read
*Note 1
tSHZ tSHZ
Write
DQM
Write
Read DQM
*Note : 1. DQM is needed to prevent bus contention.
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A10/AP
Ra Ca Cb Cc
Dc2Dc0Qb1Qb0
Qa3Qa2Qa1Qa0
Ra
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page
HIGH
Row Active
(A-Bank)
: Don't care
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto prech arge is impossible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 0. 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared care fully.
Refer the timing diagram of "Full page write burst stop cycle".
3. Burst stop is valid at every burst length.
*Note 2
Precha r ge
(A-Bank)
Burst StopRead
(A-Bank) Read
(A-Bank)
1
2
1
2
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
QAa0 QAa1 QAa2 QAa3 QAa4
QAa0 QAa1 QAa2 QAa3 QAa4
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
QAb0 QAb1 QAb2 QAb3 QAb4 QAb5
RAa CAa CAb
RAa
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page
Row Active
(A-Bank) Burst Stop Write
(A-Bank) Precharge
(A-Bank)
: Don't care
Write
(A-Bank)
*Note 2
tBDL
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossib le.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of tRDL.
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
HIGH
tRDL
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A10/AP
DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5
RAa CAa CAb
RAa
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Burst Read Single bit Write Cycle @Burst Length=2
HIGH
Row Active
(A-Bank) Row Active
(A-Bank)
Write with
Auto Precharge
(B-Bank)
: Don't care
*Note : 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regaredless of progra mmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Write
(A-Bank)
*Note 1
Row Active
(B-Bank) Read
(A-Bank)
Read with
Auto Precharge
(A-Bank)
Precharge
(A-Bank)
*Note 2
BA
A10/AP
CL=2
CL=3
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
DAa0
DAa0
QAb0 QAb1
QAb0 QAb1 DBc0
DBc0 QAd0 QAd1
QAd0 QAd1
RAa CAa RBb CAb RAc CBc CAd
RAcRAa RBb
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Active/Prech arge Power Down Mode @CAS Latency=2, Burst Length=4
Precharge
Power-down
Entry
: Don't care
*Note : 1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (32ms)
*Note 1
Precharge
tSS
*Note 2
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A10/AP
tSS
tSS
Ra Ca
Ra
Qa0 Qa1 Qa2
Row Active
Precharge
Power-down
Exit
Active
Power-down
Entry
Active
Power-down
Exit
Read
tSHZ
*Note 3
*Note 2
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∼∼
∼∼
∼∼
∼
∼
∼
∼
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∼
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
∼
∼
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Self Refresh Entry & Exit Cycle
Self Refresh Entry
: Don't care
*Note 1
*Note 7
Hi-Z Hi-Z
Self Refresh Exit Auto Refresh
tSS
*Note 2
*Note 3
*Note 4 tRCmin *Note 6
*Note 5
BA
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
A10/AP
*Note : TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart an d be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRC is required after CKE going high to complete self refresh exit.
7. 2K cycle of burst auto refresh is required be fore self refresh en try and af ter self refresh exi t if the system uses burst refresh.
∼
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∼
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼∼
∼∼
∼
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼∼
∼
∼
∼
∼
∼
∼
∼
CMOS SDRAM
012345678910 11 12 13 14 15 16 17 18 19
K4S161622E
Rev 0.2 Oct. '02
Mode Register Set Cycle
HIGH
MRS Auto Refresh
: Don't care
*Note : 1. CS, RAS, CAS , & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
New
Command New Command
Hi-Z Hi-Z
tRC
HIGH
MODE REGISTER SET CYCLE
* Both banks precharge should be complete d before Mode Register Set cycle and auto refresh cycle.
Auto Refresh Cycle
DQ
ADDR
CAS
RAS
CS
CKE
CLOCK
WE
DQM
Key Ra
*Note 3
*Note 1
*Note 2
0 1 2 3 4 5 6 7 8 9 10
∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼∼
∼
∼
∼
∼
∼∼
∼
∼
∼
∼
∼
∼
∼
K4S161622E CMOS SDRAM
Rev 1.1 Jan '03
0.075MAX
[ ]
#50 #26
#1 #25
11.76±0.20
(0.50)
0.125-0.035
+0.075
10.16
(10.76)
0.25 TYP
0~8°
0.10MAX
(0.875) 0.30 -0.05
+0.10 [0.80±0.08]
0.80TYP 0.05MIN
1.20MAX 1.00± 0.10
20.95 ± 0.10
Unit : Millimeters
50-TSOP2-400CF
PACKAGE DIMENSIONS
± 0.10
(0.50)
11.76 ± 0.20
0.35 -0.05
+0.10
