K4S161622E CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.1 Jan 2003 Samsung Electronics reserves the right to change products or specification without notice. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 512K x 16Bit x 2 Banks Synchronous DRAM FEATURES GENERAL DESCRIPTION * * * * The K4S161622E is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNGs high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * * * * * 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst Read Single-bit Write operation DQM for masking Auto & self refresh 15.6us refresh duty cycle (2K/32ms) ORDERING INFORMATION Part NO. MAX Freq. K4S161622E-TC55 183MHz K4S161622E-TC60 166MHz K4S161622E-TC70 143MHz K4S161622E-TC80 125MHz K4S161622E-TC10 100MHz Interface Package LVTTL 50 TSOP(II) FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register Bank Select Output Buffer 512K x 16 Sense AMP Row Decoder ADD Row Buffer Refresh Counter LDQM DQi Column Decoder Col. Buffer LCBR LRAS Address Register CLK 512K x 16 LWE Latency & Burst Length LCKE Programming Register LRAS LCBR LCAS LWE LWCBR LDQM Timing Register CLK CKE CS RAS CAS WE L(U)DQM * Samsung Electronics reserves the right to change products or specification without notice. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM PIN CONFIGURATION (TOP VIEW) VDD DQ0 DQ1 VSSQ DQ2 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ LDQM WE CAS RAS CS BA A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 VSS DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ N.C/RFU UDQM CLK CKE N.C A9 A8 A7 A6 A5 A4 VSS 50PIN TSOP (II) (400mil x 825mil) (0.8 mm PIN PITCH) PIN FUNCTION DESCRIPTION Pin Name Input Function CLK System Clock Active on the positive going edge to sample all inputs. CS Chip Select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and L(U)DQM CKE Clock Enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A10/AP Address Row / column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10, column address : CA0 ~ CA7 BA Bank Select Address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. RAS Row Address Strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. CAS Column Address Strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. WE Write Enable Enables write operation and row precharge. Latches data in starting from CAS, WE active. L(U)DQM Data Input/Output Mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. DQ0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins. VDD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic. VDDQ/VSSQ Data Output Power/Ground Isolated power supply and ground for the output buffers to provide improved noise immunity. N.C/RFU No Connection/ Reserved for Future Use This pin is recommended to be left No Connection on the device. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V TSTG -55 ~ +150 C Power dissipation PD 1 W Short circuit current IOS 50 mA Storage temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Symbol Min Typ Max Unit VDD, VDDQ 3.0 3.3 3.6 V VIH 2.0 3.0 VDDQ+0.3 V Input logic high votlage Note 1 Input logic low voltage VIL -0.3 0 0.8 V 2 Output logic high voltage VOH 2.4 - - V IOH = -2mA Output logic low voltage VOL - - 0.4 V IOL = 2mA ILI -10 - 10 uA 3 Input leakage current Note : 1. VIH (max) = 5.6V AC. The overshoot voltage duration is 3ns. : 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs. (VDD = 3.3V, TA = 23C, f = 1MHz, VREF =1.4V 200 mV) CAPACITANCE Pin Symbol Min Max Unit Clock CCLK 2 4 pF RAS, CAS, WE, CS, CKE, L(U)DQM CIN 2 4 pF Address CADD 2 4 pF DQ0 ~ DQ15 COUT 3 5 pF Symbol Value Unit Decoupling Capacitance between VDD and VSS CDC1 0.1 + 0.01 uF Decoupling Capacitance between VDDQ and VSSQ CDC2 0.1 + 0.01 uF DECOUPLING CAPACITANCE GUIDE LINE Recommended decoupling capacitance added to power line at board. Parameter Note : 1. VDD and VDDQ pins are separated each other. All VDD pins are connected in chip. All VDDQ pins are connected in chip. 2. VSS and VSSQ pins are separated each other All VSS pins are connected in chip. All VSSQ pins are connected in chip. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM DC CHARACTERISTICS (Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating Current (One Bank Active) Precharge Standby Current in power-down mode Symbol ICC1 Active Standby Current in non power-down mode (One Bank Active) Burst Length =1 tRCtRC(min) Io = 0 mA CAS Latency -55 3 -70 -80 -10 120 115 105 95 85 95 80 2 - -60 - 95 Unit Note mA 2 CKEVIL(max), tCC = 15ns 2 ICC2PS CKE & CLKVIL(max), tCC = 2 ICC2N CKEVIH(min), CSVIH(min), tCC = 15ns Input signals are changed one time during 30ns 15 ICC2NS CKEVIH(min), CLKVIL(max), tCC = Input signals are stable 5 ICC3P CKEVIL(max), tCC = 15ns 3 ICC3PS CKE & CLKVIL(max), tCC = 3 ICC3N CKEVIH(min), CSVIH(min), tCC = 15ns Input signals are changed one time during 30ns 25 mA ICC3NS CKEVIH(min), CLKVIL(max), tCC = Input signals are stable 15 mA Operating Current (Burst Mode) ICC4 Refresh Current ICC5 Io = 0 mA Page Burst 2Banks Activated tCCD = 2CLKs tRCtRC(min) mA mA mA 3 155 150 140 130 2 3 - ICC6 - 105 100 2 Self Refresh Current Version ICC2P Precharge Standby Current in non power-down mode Active Standby Current in power-down mode Test Condition CKE0.2V - - 115 115 115 100 90 90 80 90 90 80 1 mA 2 mA 3 mA 4 Note : 1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL. 2. Measured with outputs open. Addresses are changed only one time during tcc(min). 3. Refresh period is 32ms. Addresses are changed only one time during tcc(min). 4. K4S161622E-TC** Rev 1.1 Jan '03 K4S161622E CMOS SDRAM AC OPERATING TEST CONDITIONS (VDD = 3.3V0.3V, TA = 0 to 70C) Parameter Value Unit 2.4 / 0.4 V 1.4 V tr / tf = 1 / 1 ns 1.4 V Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition See Fig. 2 3.3V Vtt=1.4V 1200 50 VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Output Z0=50 50pF 870 50pF (Fig. 1) DC Output Load Circuit (Fig. 2) AC Output Load Circuit OPERATING AC PARAMETER (AC operating conditions unless otherwise noted) Parameter Version Symbol -55 -60 -70 -80 Unit -10 CAS Latency CL 3 2 3 2 3 2 3 2 3 2 CLK CLK cycle time tCC(min) 5.5 10 6 10 7 10 8 10 10 12 ns 2 Note Row active to row active delay tRRD(min) CLK 1 RAS to CAS delay tRCD(min) 3 3 3 2 3 2 3 2 2 2 CLK 1 Row precharge time tRP(min) 3 3 3 2 3 2 3 2 2 2 CLK 1 tRAS(min) 7 7 7 5 7 5 6 5 5 4 CLK 1 Row active time 100 tRAS(max) Row cycle time tRC(min) Last data in to row precharge tRDL(min) Last data in to new col.address delay tCDL(min) Last data in to burst stop CLK 1 1 CLK 2, 5 1 CLK 2 tBDL(min) 1 CLK 2 Col. address to col. address delay tCCD(min) 1 CLK Mode Register Set cycle time tMRS(min) 2 CLK Number of valid output data 10 10 10 7 10 us 7 CAS Latency=3 2 CAS Latency=2 1 9 7 7 6 ea 4 Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. Refer to the following clock unit based AC conversion table Rev 1.1 Jan '03 K4S161622E Parameter CMOS SDRAM Symbol Version -55 -60 -70 -80 Unit -10 CLK cycle time tCC(min) 5.5 6 7 8 10 ns Row active to row active delay tRRD(min) 11 12 14 16 20 ns RAS to CAS delay tRCD(min) 16.5 18 20 20 20 ns Row precharge time tRP(min) 16.5 18 20 20 20 ns Row active time tRAS(min) 38.5 42 49 48 48 ns Row cycle time tRC(min) 55 60 69 70 70 ns -80 -10 100 tRAS(max) us 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J". From the next generation, tRDL will be only 2CLK for every clock frequency. AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter -55 Symbol Min CLK cycle time CAS Latency=3 tCC CAS Latency=2 CLK to valid output delay CAS Latency=3 CAS Latency=3 CLK low pulse width CAS Latency=3 Input setup time tSAC tOH CLK high pulse width tCH CAS Latency=2 1000 tCL tSS 6 Max 1000 Min 7 Max 1000 10 Min 8 Max 1000 10 Min 10 Unit Note ns 1 ns 1, 2 Max 1000 12 - 5 - 5.5 - 5.5 - 6 - 6 - 6 - 6 - 6 - 6 - 8 2 - 2.5 - 2.5 - 2.5 - 2.5 - ns 2 - 3 - 3 - 3.5 - ns 3 - 3 - 3 - 3.5 - ns 3 - 2 - 2.5 - ns 3 2 - 2 1.5 2.5 3 - 3 CAS Latency=2 Min -70 - 3 CAS Latency=2 CAS Latency=3 Max - CAS Latency=2 Output data 5.5 -60 2.5 3 - 2 1.5 - 2 1.75 2 Input hold time tSH 1 - 1 - 1 - 1 - 1 - ns 3 CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - 1 - ns 2 - 5 - 5.5 - 5.5 - 6 - 6 - 6 - 6 - 6 - 6 - 8 CLK to output in Hi-Z CAS Latency=3 CAS Latency=2 tSHZ ns Note : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf)=1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM SIMPLIFIED TRUTH TABLE COMMAND Register Mode Register Set Auto Refresh Refresh CKEn-1 CKEn CS RAS CAS WE DQM H X L L L L X OP CODE L L L H X X H Entry Self Refresh Exit H BA L H L H H H H X X X X X L L H H X V H X L H L H X V Write & Column Address Auto Precharge Disable Auto Precharge Enable X L H L L X H X X L L H L H H L V H L Exit L H Entry H L Precharge Power Down Mode Exit Column Address (A0~A7) L L X X Both Banks Entry L Column Address (A0~A7) H H L DQM H No Operation Command H H H X X X L V V V X X X X H X X X L H H H H X X X L V V V X X H X X X L H H H 3 Row Address H Auto Precharge Enable Clock Suspend or Active Power Down 3 3 H Precharge 1, 2 X Auto Precharge Disable H Note 3 Read & Column Address Bank Selection A9~ A0 L Bank Active & Row Addr. Burst Stop A10/AP X V L X H 4 4, 5 4 4, 5 6 X X X X X X X V X X X 7 (V=Valid, X=Dont Care, H=Logic High, L=Logic Low) Note : 1. OP Code : Operand Code A0 ~ A10/AP, BA : Program keys. (@MRS) 2. MRS can be issued only at both banks precharge state. A new command can be issued after 2 clock cycle of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at both banks precharge state. 4. BA : Bank select address. If "Low" at read, write, row active and precharge, bank A is selected. If "High" at read, write, row active and precharge, bank B is selected. If A10/AP is "High" at row precharge, BA is ignored and both banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the assoiated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Rev 1.1 Jan '03 K4S161622E CMOS SDRAM MODE REGISTER FIELD TABLE TO PROGRAM MODES Register Programmed with MRS BA RFU Address Function A10/AP RFU A8 A9 W.B.L A6 A7 TM Test Mode A7 Type A6 A5 A4 Latency 0 0 Mode Register Set 0 0 0 0 1 Reserved 0 0 0 Reserved 0 1 Reserved 1 Write Burst Length A3 BT A2 Burst Type CAS Latency A8 1 A5 A4 CAS Latency A1 Burst Length A0 Burst Length Type A2 A1 A0 BT = 0 BT = 1 Reserved A3 0 Sequential 0 0 0 1 1 1 - 1 Interleave 0 0 1 2 2 1 0 2 0 1 0 4 4 0 1 1 3 0 1 1 8 8 1 0 0 Reserved 1 0 0 Reserved Reserved A9 0 Length 1 0 1 Reserved 1 0 1 Reserved Reserved Burst 1 1 0 Reserved 1 1 0 Reserved Reserved 1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved Full Page Length : x4 (1024), x8 (512), x16 (256) POWER UP SEQUENCE SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for all banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled. 2. RFU (Reserved for future use) should stay "0" during MRS cycle. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM BURST SEQUENCE (BURST LENGTH = 4) Initial Address A1 A0 Sequential Interleave 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 BURST SEQUENCE (BURST LENGTH = 8) A2 Initial Address A1 A0 Sequential Interleave 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 Rev 1.1 Jan '03 K4S161622E CMOS SDRAM DEVICE OPERATIONS CLOCK (CLK) ADDRESS INPUTS (A0 ~ A10/AP) The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge of the clock. The clock transitions must be monotonic between VIL and VIH. During operation with CKE high all inputs are assumed to be in a valid state (low or high) for the duration of set-up and hold time around positive edge of the clock in order to function well Q perform and ICC specifications. : In case x 4 CLOCK ENABLE (CKE) The clock enable(CKE) gates the clock onto SDRAM. If CKE goes low synchronously with clock (set-up and hold time are the same as other inputs), the internal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored from the next clock cycle after CKE goes low. When all banks are in the idle state and CKE goes low synchronously with clock, the SDRAM enters the power down mode from the next clock cycle. The SDRAM remains in the power down mode ignoring the other inputs as long as CKE remains low. The power down exit is synchronous as the internal clock is suspended. When CKE goes high at least "1CLK + tSS" before the high going edge of the clock, then the SDRAM becomes active from the same clock edge accepting all the input commands. The 21 address bits are required to decode the 2,097,152 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 10 bit column addresses are latched along with CAS, WE and BA during read or write command. : In case x 8 The 20 address bits are required to decode the 1,048,576 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 9 bit column addresses are latched along with CAS, WE and BA during read or write command. : In case x 16 The 19 address bits are required to decode the 524,288 word locations are multiplexed into 11 address input pins (A0 ~ A10/ AP). The 11 bit row addresses are latched along with RAS and BA during bank activate command. The 8 bit column addresses are latched along with CAS, WE and BA during read or write command. BANK ADDRESS (BA) NOP and DEVICE DESELECT : In case x 4 When RAS, CAS and WE are high, the SDRAM performs no operation (NOP). NOP does not initiate any new operation, but is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc. The device deselect is also a NOP and is entered by asserting CS high. CS high disables the command decoder so that RAS, CAS, WE and all the address inputs are ignored. This SDRAM is organized as two independent banks of 2,097,152 words x 4 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations. : In case x 8 This SDRAM is organized as two independent banks of 1,048,576 words x 8 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations. : In case x 16 This SDRAM is organized as two independent banks of 524,288 words x 16 bits memory arrays. The BA input is latched at the time of assertion of RAS and CAS to select the bank to be used for the operation. The bank select BA is latched at bank active, read, write, mode register set and precharge operations. POWER-UP SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. 1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us. 3. Issue precharge commands for both banks of the devices. 4. Issue 2 or more auto-refresh commands. 5. Issue a mode register set command to initialize the mode register. cf.) Sequence of 4 & 5 is regardless of the order. The device is now ready for normal operation. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM DEVICE OPERATIONS (Continued) MODE REGISTER SET (MRS) active to initiate sensing and restoring the complete row of The mode register stores the data for controlling the various dynamic cells is determined by tRAS(min). Every SDRAM bank activate command must satisfy tRAS(min) specification before a operating modes of SDRAM. It programs the CAS latency, burst type, burst length, test mode and various vendor specific options to make SDRAM useful for variety of different applications. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by asserting low on CS, RAS, CAS and WE (The SDRAM should be in active mode with CKE already high prior to writing the mode register). The state of address pins A0 ~ A10/AP and BA in the same cycle as CS, RAS, CAS and WE going low is the data written in the mode register. Two clock cycles is required to complete the write in the mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. The mode register is divided into various fields depending on the fields of functions. The burst length field uses A0 ~ A2, burst type uses A3, CAS latency (read latency from column address) uses A4 ~ A6, vendor specific options or test mode use A7 ~ A8, A10/AP and BA. The write burst length is programmed using A9. A7 ~ A8, A10/AP, BA must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. BANK ACTIVATE The bank activate command is used to select a random row in an idle bank. By asserting low on RAS and CS with desired row and bank address, a row access is initiated. The read or write operation can occur after a time delay of tRCD(min) from the time of bank activation. tRCD is an internal timing parameter of SDRAM, therefore it is dependent on operating clock frequency. The minimum number of clock cycles required between bank activate and read or write command should be calculated by dividing tRCD(min) with cycle time of the clock and then rounding off the result to the next higher integer. The SDRAM has two internal banks in the same chip and shares part of the internal circuitry to reduce chip area, therefore it restricts the activation of two banks simultaneously. Also the noise generated during sensing of each bank of SDRAM is high, requiring some time for power supplies to recover before the other bank can be sensed reliably. tRRD(min) specifies the minimum time required between activating different bank. The number of clock cycles required between different bank activation must be calculated similar to tRCD specification. The minimum time required for the bank to be precharge command to that active bank can be asserted. The maximum time any bank can be in the active state is determined by tRAS(max). The number of cycles for both tRAS(min) and tRAS(max) can be calculated similar to tRCD specification. BURST READ The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The burst read command is issued by asserting low on CS and CAS with WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number of clock cycles after the issue of burst read command. The burst length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column address of the active row. The address wraps around if the initial address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in the mode register. The output goes into high-impedance at the end of the burst, unless a new burst read was initiated to keep the data output gapless. The burst read can be terminated by issuing another burst read or burst write in the same bank or the other active bank or a precharge command to the same bank. The burst stop command is valid at every page burst length. BURST WRITE The burst write command is similar to burst read command and is used to write data into the SDRAM on consecutive clock cycles in adjacent addresses depending on burst length and burst sequence. By asserting low on CS, CAS and WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. The write burst can also be terminated by using DQM for blocking data and procreating the bank tRDL after the last data input to be written into the active row. See DQM OPERATION also. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM DEVICE OPERATIONS (Continued) DQM OPERATION AUTO REFRESH The DQM is used to mask input and output operations. It works similar to OE during read operation and inhibits writing during write operation. The read latency is two cycles from DQM and zero cycle for write, which means DQM masking occurs two cycles later in read cycle and occurs in the same cycle during write cycle. DQM operation is synchronous with the clock. The DQM signal is important during burst interruptions of write with read or precharge in the SDRAM. Due to asynchronous nature of the internal write, the DQM operation is critical to avoid unwanted or incomplete writes when the complete burst write is not required. Please refer to DQM timing diagram also. The storage cells of SDRAM need to be refreshed every 32ms to maintain data. An auto refresh cycle accomplishes refresh of a single row of storage cells. The internal counter increments automatically on every auto refresh cycle to refresh all the rows. An auto refresh command is issued by asserting low on CS, RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state and the device is not in power down mode (CKE is high in the previous cycle). The time required to complete the auto refresh operation is specified by tRFC(min). The minimum number of clock cycles required can be calculated by driving tRFC with PRECHARGE clock cycle time and them rounding up to the next higher integer. The precharge operation is performed on an active bank by The auto refresh command must be followed by NOP's until the asserting low on CS, RAS, WE and A10/AP with valid BA of the auto refresh operation is completed. Both banks will be in the bank to be precharged. The precharge command can be idle state at the end of auto refresh operation. The auto refresh asserted anytime after tRAS(min) is satisfied from the bank active is the preferred refresh mode when the SDRAM is being used command in the desired bank. tRP is defined as the minimum number of clock cycles required to complete row precharge is calculated by dividing tRP with clock cycle time and rounding up for normal data transactions. The auto refresh cycle can be performed once in 15.6us or a burst of 2048 auto refresh cycles once in 32ms. to the next higher integer. Care should be taken to make sure that burst write is completed or DQM is used to inhibit writing before precharge command is asserted. The maximum time any bank can be active is specified by tRAS(max). Therefore, each bank activate command. At the end of precharge, the bank enters the idle state and is ready to be activated again. Entry to Power down, Auto refresh, Self refresh and Mode register set etc. is possible only when both banks are in idle state. SELF REFRESH The self refresh is another refresh mode available in the SDRAM. The self refresh is the preferred refresh mode for data retention and low power operation of SDRAM. In self refresh mode, the SDRAM disables the internal clock and all the input buffers except CKE. The refresh addressing and timing are internally generated to reduce power consumption. AUTO PRECHARGE The self refresh mode is entered from both banks idle state by The precharge operation can also be performed by using auto precharge. The SDRAM internally generates the timing to satisfy tRAS(min) and "tRP" for the programmed burst length and CAS latency. The auto precharge command is issued at the same time as burst read or burst write by asserting high on A10/AP. If burst read or burst write by asserting high on A10/AP, the bank is left active until a new command is asserted. Once auto precahrge command is given, no new commands are possible to that particular bank until the bank achieves idle state. asserting low on CS, RAS, CAS and CKE with high on WE. BOTH BANKS PRECHARGE Both banks can be precharged at the same time by using precharge all command. Asserting low on CS, RAS, and WE with high on A10/AP after both banks have satisfied tRAS(min) requirement, performs precharge on both banks. At the end of tRP after performing precharge to all the banks, both banks are in idle state. Once the self refresh mode is entered, only CKE state being low matters, all the other inputs including the clock are ignored in order to remain in the self refresh mode. The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP's for a minimum time of tRFC before the SDRAM reaches idle state to begin normal operation. If the system uses burst auto refresh during normal operation, it is recommended to use burst 2048 auto refresh cycles immediately after exiting in self refresh mode. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM BASIC FEATURE AND FUNCTION DESCRIPTIONS 1. CLOCK Suspend 2) Clock Suspended During Read (BL=4) 1) Clock Suspended During Write (BL=4) CLK CMD WR RD CKE Masked by CKE Masked by CKE Internal CKE DQ(CL2) D0 D1 D2 D3 DQ(CL3) D0 D1 D2 D3 Q0 D Q01 Q2 Q3 Q0 Q1 Q2 Not Written Q3 Suspended Dout 2. DQM Operation 2) Read Mask (BL=4) 1) Write Mask (BL=4) CLK CMD WR RD DQM Masked by DQM DQ(CL2) D0 DQ(CL3) D0 D1 Masked by DQM Q0 D3 D1 Hi-Z Hi-Z D3 DQM to Data-in Mask = 0 Q2 Q3 Q1 Q2 Q3 DQM to Data-out Mask = 2 3) DQM with Clock Suspended (Full Page Read) Note 2 CLK CMD RD CKE DQM DQ(CL2) DQ(CL3) Q0 Hi-Z Hi-Z Q2 Q1 Hi-Z Hi-Z Q4 Q3 Hi-Z Hi-Z Q6 Q7 Q8 Q5 Q6 Q7 *Note : 1. CKE to CLK disable/enable = 1CLK. 2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L" 3. DQM masks both data-in and data-out. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 3. CAS Interrupt (I) Note 1 1) Read interrupted by Read (BL=4) CLK CMD RD RD ADD A B DQ(CL2) QA0 DQ(CL3) QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 tCCD Note 2 2) Write interrupted by Write (BL=2) 3) Write interrupted by Read (BL=2) CLK CMD WR WR tCCD Note 2 ADD A B DQ DA0 DB0 tCDL Note 3 WR RD tCCD A DB1 Note 2 B DQ(CL2) DA0 DQ(CL3) DA0 QB0 QB1 QB0 QB1 tCDL Note 3 *Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst. By "CAS Interrupt", to stop burst read/write by CAS access ; read and write. 2. tCCD : CAS to CAS delay. (=1CLK) 3. tCDL : Last data in to new column address delay. (=1CLK) Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 4. CAS Interrupt (II) : Read Interrupted by Write & DQM (a) CL=2, BL=4 CLK i) CMD RD WR DQM DQ ii) CMD D0 RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM Hi-Z DQ iii) CMD D0 RD WR DQM Hi-Z DQ iv) CMD D0 RD WR DQM Q0 DQ Hi-Z Note 1 D0 D3 (b) CL=3, BL=4 CLK i) CMD RD WR DQM DQ ii) CMD D0 RD D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 D3 D1 D2 WR DQM D0 DQ iii) CMD RD WR DQM D0 DQ iii) CMD RD WR DQM Hi-Z DQ iv) CMD D0 RD WR DQM DQ Q0 Hi-Z Note 1 D0 D3 *Note : 1. To prevent bus contention, there should be at least one gap between data in and data out. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 5. Write Interrupted by Precharge & DQM CLK CMD PRE WR Note 2 DQM DQ Note 3 D0 D1 D2 D3 Masked by DQM *Note : 2. To inhibit invalid write, DQM should be issued. 3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt but only the other bank precharge of dual banks operation. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 6. Precharge 1) Normal Write (BL=4) CLK CMD WR DQ D0 PRE D1 D2 D3 tRDL Note 2 2) Normal Read (BL=4) CLK CMD RD PRE 1 DQ(CL2) Q0 Q1 Q2 Q3 Q0 Q1 Q2 Note 2 DQ(CL3) Q3 2 7. Auto Precharge 1) Normal Write (BL=4) CLK CMD WR DQ D0 D1 D2 D3 Note 3 Auto Precharge Starts 2) Normal Read (BL=4) CLK CMD DQ(CL2) DQ(CL3) RD Q0 Q1 Q2 Q3 Q0 Q1 Q2 Q3 Note 3 Auto Precharge Starts *Note : 1. tRDL : Last data in to row precharge delay 2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respectively. 3. The row active command of the precharge bank can be issued after tRP from this point. The new read/write command of the other activated bank can be issued from this point. At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 8. Burst Stop & Interrupted by Precharge 1) Normal Write (BL=4) 2) Write Burst Stop (BL=8) CLK CLK CMD WR CMD PRE DQM WR STOP DQM DQ D0 D1 D2 DQ D3 tRDL D0 D1 D2 Note 1 D3 D4 tBDL 3) Read Interrupted by Precharge (BL=4) D5 Note 2 4) Read Burst Stop (BL=4) CLK CLK RD CMD PRE DQ(CL2) Q0 DQ(CL3) CMD Q1 Q0 RD STOP 1 DQ(CL2) Note 3 2 Q1 DQ(CL3) Q0 Q1 Q0 1 Note 3 Q1 2 9. MRS 1) Mode Register Set CLK Note 4 CMD MRS PRE tRP ACT tMRS = 2CLK *Note : 1. tRDL : 1 CLK 2. tBDL : 1 CLK ; Last data in to burst stop delay. Read or write burst stop command is valid at every burst length. 3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely. 4. PRE : Both banks precharge if necessary. MRS can be issued only at both banks precharge state. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 10. Clock Suspend Exit & Power Down Exit 1) Clock Suspend (=Active Power Down) Exit 2) Power Down (=Precharge Power Down) CLK CLK CKE CKE tSS Internal CLK tSS Internal CLK Note 1 CMD Note 2 NOP ACT CMD RD 11. Auto Refresh & Self Refresh 1) Auto Refresh & Self Refresh Note 3 CLK o Note 4 CMD Note 5 PRE AR CMD o CKE o tRP 2) Self Refresh tRFC o Note 6 CLK o Note 4 CMD PRE CMD SR CKE o tRP o tRFC *Note : 1. Active power down : one or both banks active state. 2. Precharge power down : both banks precharge state. 3. The auto refresh is the same as CBR refresh of conventional DRAM. No precharge commands are required after auto refresh command. During tRFC from auto refresh command, any other command can not be accepted. 4. Before executing auto/self refresh command, both banks must be idle state. 5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry. 6. During self refresh mode, refresh interval and refresh operation are perfomed internally. After self refresh entry, self refresh mode is kept while CKE is low. During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state. For the time interval of tRFC from self refresh exit command, any other command can not be accepted. Before/After self refresh mode, burst auto refresh cycle (2048 cycles) is recommended. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM 12. About Burst Type Control Basic MODE Random MODE Sequential Counting At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8) BL=1, 2, 4, 8 and full page.At Full page wrap-around. Interleave Counting At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8) BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting Random column Access tCCD = 1 CLK Every cycle Read/Write Command with random column address can realize Random Column Access. That is similar to Extended Data Out (EDO) Operation of conventional DRAM. 13. About Burst Length Control Basic MODE 1 At MRS A2,1,0 = "000". At auto precharge, tRAS should not be violated. 2 At MRS A2,1,0 = "001". At auto precharge, tRAS should not be violated. 4 At MRS A2,1,0 = "010". 8 At MRS A2,1,0 = "011". Full Page Special MODE BRSW Random MODE Burst Stop Interrupt MODE RAS Interrupt (Interrupted by Precharge) CAS Interrupt At MRS A2,1,0 = "111". Wrap around mode(Infinite burst length)should be stopped by burst stop, RAS interrupt or CAS interrupt. At MRS A9 = "1". Read burst=1,2,4,8,full page Write burst=1 At auto precharge of write, tRAS should not be violate tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively Using burst stop command, any burst length control is possible. Before the end of burst, Row precharge command of the same bank stops read/write burst with Row precharge. tRDL= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively. During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 1) Current State IDLE Row Active Read Write Read with Auto Precharge Write with Auto Precharge Precharging CS RAS CAS WE BA ADDR ACTION Note H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL 2 L H L X BA CA, A10/AP ILLEGAL 2 L L H H BA RA L L H L BA A10/AP L L L H X X L L L L OP code OP code H X X X X X NOP L H H H X X NOP L H H L X X ILLEGAL L H L H BA CA, A10/AP Begin Read ; latch CA ; determine AP L H L L BA CA, A10/AP Begin Write ; latch CA ; determine AP L L H H BA RA ILLEGAL L L H L BA A10/AP Precharge Row (& Bank) Active ; Latch RA NOP 4 Auto Refresh or Self Refresh 5 Mode Register Access 5 2 2 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New Read, Determine AP L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Term burst, Precharge timing for Reads L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Row Active) L H H H X X NOP (Continue Burst to End --> Row Active) L H H L X X Term burst --> Row active L H L H BA CA, A10/AP Term burst, New read, Determine AP 3 L H L L BA CA, A10/AP Term burst, New Write, Determine AP 3 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP Term burst, precharge timing for Writes 3 L L L X X X ILLEGAL H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA CA, A10/AP ILLEGAL L L H X BA RA, RA10 ILLEGAL L L L X X X ILLEGAL 2 H X X X X X NOP (Continue Burst to End --> Precharge) L H H H X X NOP (Continue Burst to End --> Precharge) L H H L X X ILLEGAL L H L X BA CA, A10/AP ILLEGAL L L H X BA RA, RA10 ILLEGAL L L L X X X ILLEGAL 2 H X X X X X NOP --> Idle after tRP L H H H X X NOP --> Idle after tRP L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP NOP --> Idle after tRPL 4 Rev 1.1 Jan '03 K4S161622E CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 1) Current State Row Activating Refreshing Mode Register Accessing CS RAS CAS WE BA ADDR ACTION Note L L L X X X ILLEGAL H X X X X X NOP --> Row Active after tRCD L H H H X X NOP --> Row Active after tRCD L H H L X X ILLEGAL 2 L H L X BA CA ILLEGAL 2 L L H H BA RA ILLEGAL 2 L L H L BA A10/AP ILLEGAL 2 L L L X X X ILLEGAL H X X X X X NOP --> Idle after tRFC L H H X X X NOP --> Idle after tRFC L H L X X X ILLEGAL L L H X X X ILLEGAL L L L X X X ILLEGAL H X X X X X NOP --> Idle after 2 clocks L H H H X X NOP --> Idle after 2 clocks L H H L X X ILLEGAL L H L X X X ILLEGAL L L X X X X ILLEGAL Abbreviations : RA = Row Address NOP = No Operation Command BA = Bank Address CA = Column Address AP = Auto Precharge *Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle. 2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the state of that bank. 3. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP). 5. Illegal if any bank is not idle. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM FUNCTION TRUTH TABLE (TABLE 2) Current State Self Refresh All Banks Precharge Power Down All Banks Idle Any State other than Listed above CKE (n-1) CKE n CS RAS CAS WE ADDR ACTION Note H X X X X X X L H H X X X X Exit Self Refresh --> Idle after tRFC (ABI) 6 L H L H H H X Exit Self Refresh --> Idle after tRFC (ABI) 6 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) H X X X X X X INVALID L H H X X X X Exit Power Down --> ABI L H L H H H X Exit Power Down --> ABI 7 L H L H H L X ILLEGAL 7 L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Low Power Mode) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down 8 H L L H H L X ILLEGAL 8 H L L H L X X ILLEGAL H L L L H H RA H L L L L H X H L L L L L OP Code INVALID Row (& Bank) Active Enter Self Refresh 8 Mode Register Access L L X X X X X NOP H H X X X X X Refer to Operations in Table 1 H L X X X X X Begin Clock Suspend next cycle 9 L H X X X X X Exit Clock Suspend next cycle 9 L L X X X X X Maintain Clcok Suspend Abbreviations : ABI = All Banks Idle, RA = Row Address *Note : 6. CKE low to high transition is asynchronous. 7. CKE low to high transition is asynchronous if restarts internal clock. A minimum setup time 1CLK + tSS must be satisfied before any command other than exit. 8. Power down and self refresh can be entered only from the both banks idle state. 9. Must be a legal command. Rev 1.1 Jan '03 K4S161622E CMOS SDRAM Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1 tCH 1 0 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 CLOCK tCL tCC HIGH CKE tRAS tRC *Note 1 tSH CS tRCD tRP tSS tSH RAS tSS tCCD tSH CAS tSH ADDR Ra tSS tSS Ca Cb Cc Rb tSH tSS *Note 2 *Note 2,3 *Note 2,3 BA BS BS BS A10/AP Ra *Note 3 *Note 2,3 *Note 4 BS *Note 3 tRAC BS *Note 3 *Note 4 Rb tSH tSAC Qa DQ *Note 2 BS Db tSLZ Qc tSS tOH tSH WE tSS tSS tSH DQM Row Active Read Write Read Row Active Precharge : Don't care Rev 0.2 Oct. '02 K4S161622E 0 1 CMOS SDRAM *Note : 1. All inputs expect CKE & DQM can be don Ct care when CS is high at the CLK high going edge. 2. Bank active & read/write are controlled by BA. 2 3 4 5 6 7 BA Active & Read/Write 0 Bank A 1 Bank B 8 9 10 11 12 13 14 15 16 17 18 19 3. Enable and disable auto precharge function are controlled by A10/AP in read/write command. A10/AP BA 0 1 Operation 0 Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. 4. A10/AP and BA control bank precharge when precharge command is asserted. A10/AP BA Precharge 0 0 0 1 Bank A Bank B 1 X Both Banks Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Power Up Sequence 0 1 2 3 4 6 7 8 9 10 11 12 13 CKE 5 CLOCK 14 15 16 17 18 19 High level is necessary CS tRP tRC tRC RAS CAS ADDR BA A10/AP DQM WE RAa High-Z DQ RAa Key High level is necessary Precharge (All Banks) Auto Refresh Auto Refresh Mode Register Set Row Active (A-Bank) : Don't care Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Read & Write Cycle at Same Bank @Burst Length=4 1 0 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE tRC *Note 1 CS tRCD RAS *Note 2 CAS ADDR Ra Ca0 Rb Cb0 BA A10/AP Ra Rb tOH DQ CL=2 Qa0 Qa1 Qa2 Qa3 Db0 Db1 Db2 Db3 tRAC *Note 3 tSAC tSHZ tRDL *Note 4 tOH CL=3 Qa0 Qa1 Qa2 Qa3 Db0 Db1 tRAC *Note 3 tSAC tSHZ Db2 Db3 tRDL *Note 4 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. Minimum row cycle times is required to complete internal DRAM operation. 2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok. 3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC 4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst wrap-around). Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Page Read & Write Cycle at Same Bank @Burst Length=4 1 0 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS tRCD RAS *Note 2 CAS ADDR Ra Ca0 Cb0 Cc0 Cd0 BA A10/AP Ra tRDL DQ CL=2 Qa0 CL=3 Qa1 Qb0 Qb1 Qb2 Dc0 Dc1 Dd0 Dd1 Qa0 Qa1 Qb0 Dc0 Dc1 Dd0 Dd1 Qb1 tCDL WE *Note 1 *Note 3 DQM Row Active (A-Bank) Read (A-Bank) Read (A-Bank) Write (A-Bank) Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. To write data before burst read ends, DQM should be asserted three cycle prior to write command to avoid bus contention. 2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written. 3. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Page Read Cycle at Different Bank @Burst Length=4 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE *Note 1 CS RAS *Note 2 CAS ADDR RAa CAa RBb CAc CBb CAe CBd BA A10/AP DQ RAa RBb QAa0 QAa1 QAa2 QAa3 CL=2 CL=3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QAa0 QAa1 QAa2 QAa3 QBd0 QBd1 QAe0 QAe1 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Read (B-Bank) Read (A-Bank) Read (B-Bank) Read (A-Bank) Precharge (A-Bank) Read (A-Bank) : Don't care *Note : 1. CS can be don't cared when RAS, CAS and WE are high at the clock high going dege. 2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Page Write Cycle at Different Bank @Burst Length=4 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS *Note 2 CAS ADDR RAa CAa RBb CBb CAc CBd BA A10/AP RAa DQ RBb DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1 tCDL tRDL WE *Note 1 DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Write (B-Bank) Write (A-Bank) Precharge (Both Banks) Write (B-Bank) : Don't care *Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data. 2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Read & Write Cycle at Different Bank @Burst Length=4 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa RBb CBb RAc CAc BA A10/AP RAa RBb RAc tCDL DQ CL=2 QAa0 QAa1 QAa2 QAa3 CL=3 QAa0 QAa1 QAa2 QAa3 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 *Note 1 QAc0 QAc1 QAc2 QAc0 QAc1 WE DQM Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Row Active (B-Bank) Write (B-Bank) Read (A-Bank) Row Active (A-Bank) : Don't care *Note : 1. tCDL should be met to complete write. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Read & Write Cycle with Auto Precharge I @Burst Length=4 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR Ra Rb Ra Rb Ca Ca Ra Cb BA A10/AP DQ Ra CL=2 Qa0 CL=3 Qa1 Qb0 Qb1 Qb2 Qb3 Qa0 Qa1 Qb0 Qb1 Qb2 Qb3 Da0 Da1 Da0 Da1 WE DQM Row Active (A-Bank) Read with Auto Pre charge (A-Bank) Row Active (B-Bank) Read without Auto precharge(B-Bank) Auto Precharge Start Point (A-Bank)* Precharge (B-Bank) Row Active (A-Bank) Write with Auto Precharge (A-Bank) : Don't care *Note: * When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation. - if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank auto precharge will start at B Bank read command input point . - any command can not be issued at A Bank during tRP after A Bank auto precharge starts. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Read & Write Cycle with Auto Precharge II @Burst Length=4 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR Ra Ca Cb Rb BA A10/AP DQ Rb Ra CL=2 Qa0 CL=3 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qb0 Qa3 Qb1 Qb2 Qb3 Qb0 Qb1 Qb2 Qb3 WE DQM * Row Active (A-Bank) Read with Auto Precharge (A-Bank) Auto Precharge Start Point (A-Bank) Row Active (B-Bank) Read with Auto Precharge (B-Bank) Auto Precharge Start Point (B-Bank) : Don't care *Note : * Any command to A-bank is not allowed in this period. tRP is determined from at auto precharge start point Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4 1 0 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 CLOCK CKE CS RAS CAS ADDR Ra Ca Cb Cc BA A10/AP Ra DQ Qa0 Qa1 Qa2 Qb0 Qa3 tSHZ Qb1 Dc0 Dc2 tSHZ WE *Note 1 DQM Row Active Read Clock Suspension Read Write DQM Read DQM Write DQM Write Clock Suspension : Don't care *Note : 1. DQM is needed to prevent bus contention. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page 1 0 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA A10/AP DQ RAa CL=2 1 1 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 *Note 2 CL=3 2 2 QAa0 QAa1 QAa2 QAa3 QAa4 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 WE DQM Row Active (A-Bank) Read (A-Bank) Burst Stop Read (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. About the valid DQs after burst stop, it is same as the case of RAS interrupt. Both cases are illustrated above timing diagram. See the label 0. 1, 2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of "Full page write burst stop cycle". 3. Burst stop is valid at every burst length. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page 1 0 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 18 19 CLOCK HIGH CKE CS RAS CAS ADDR RAa CAa CAb BA A10/AP RAa tBDL tRDL *Note 2 DQ DAa0 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 DAb4 DAb5 WE DQM Row Active (A-Bank) Write (A-Bank) Burst Stop Write (A-Bank) Precharge (A-Bank) : Don't care *Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible. 2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write. DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 3. Burst stop is valid at every burst length. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Burst Read Single bit Write Cycle @Burst Length=2 1 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 CLOCK *Note 1 HIGH CKE CS RAS *Note 2 CAS ADDR RAa CAa RBb CAb RAc CBc CAd BA A10/AP DQ RAa RBb CL=2 DAa0 CL=3 DAa0 RAc QAb0 QAb1 DBc0 QAb0 QAb1 QAd0 QAd1 DBc0 QAd0 QAd1 WE DQM Row Active (A-Bank) Row Active (B-Bank) Write (A-Bank) Read with Auto Precharge (A-Bank) Row Active (A-Bank) Read (A-Bank) Precharge (A-Bank) Write with Auto Precharge (B-Bank) : Don't care *Note : 1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set). At the BRSW Mode, the burst length at write is fixed to "1" regaredless of programmed burst length. 2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated. Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command, the next cycle starts the precharge. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4 1 2 3 4 5 6 7 8 tSS 11 12 13 14 15 16 17 18 19 tSS *Note 1 tSS *Note 2 *Note 2 CKE 10 9 0 CLOCK *Note 3 Ra A10/AP Ca BA Ra ADDR CAS RAS CS tSHZ DQ Precharge Power-down Entry Qa2 DQM Qa1 WE Qa0 Row Active Precharge Power-down Exit Active Power-down Entry Read Precharge Active Power-down Exit : Don't care *Note : 1. Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + tss prior to Row active command. 3. Can not violate minimum refresh specification. (32ms) Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Self Refresh Entry & Exit Cycle 2 3 4 5 6 7 *Note 2 8 9 10 11 12 13 14 15 16 17 18 19 1 0 CLOCK *Note 4 tRCmin *Note 1 *Note 6 *Note 3 CKE tSS RAS *Note 5 ADDR BA Hi-Z WE Self Refresh Entry DQM Hi-Z DQ A10/AP *Note 7 CAS CS Self Refresh Exit Auto Refresh : Don't care *Note : TO ENTER SELF REFRESH MODE 1. CS, RAS & CAS with CKE should be low at the same clcok cycle. 2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE. 3. The device remains in self refresh mode as long as CKE stays "Low". cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh. TO EXIT SELF REFRESH MODE 4. System colck restart and be stable before returning CKE high. 5. CS starts from high. 6. Minimum tRC is required after CKE going high to complete self refresh exit. 7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM Mode Register Set Cycle 0 1 2 3 4 5 Auto Refresh Cycle 6 7 8 09 110 2 11 3 12 4 13 514 HIGH CKE 6 15 7 16 8 17 9 18 10 19 CLOCK HIGH CS *Note 2 tRC RAS *Note 1 CAS Key Ra Hi-Z Hi-Z DQ *Note 3 ADDR WE DQM MRS New Command Auto Refresh New Command : Don't care * Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle. MODE REGISTER SET CYCLE *Note : 1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Rev 0.2 Oct. '02 K4S161622E CMOS SDRAM PACKAGE DIMENSIONS 50-TSOP2-400CF Unit : Millimeters 20.95 0.10 1.20MAX 0.20 (10.76) 0.125+0.075 -0.035 11.76 #25 (0.50) #1 11.760.20 #26 10.16 0.10 0.25 TYP #50 (0.50) 0~8 1.00 0.10 0.10MAX [ 0.075MAX ] (0.875) 0.30 +0.10 -0.05 0.35 +0.10 -0.05 0.80TYP [0.800.08] 0.05MIN Rev 1.1 Jan '03