PC860 PowerQUICC™ Processor
Fact Sheet
The MPC860 PowerQUICCTM is a versatile one-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications, excelling particularly in communications and networking products. The
PowerQUICCcan be described as a next-generation MC68360 QUICC for network and data communication applications,
providing higher performance in all areas of device operation including flexibility, extensions in capability, and
integration. The MPC860 PowerQUICC, like the MC68360 QUICC integrates two processing blocks. One block is the
Embedded PowerPC Core and the second block is a Communication Processor Module (CPM) that closely resembles the
MC68360 CPM. The CPM supports four serial communications controllers (SCCs) on the device; however, there are
actually eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI)
and one I2C interface. This dual-processor architecture provides lower power consumption than traditional architectures
because the CP off-loads peripheral tasks from the Embedded PowerPC Core.
PC860 Main Features
n32-bit Embedded PowerPC Core 66 to 80 MHz
nSystem Interface Unit (SIU)
nCommunication Processor Module (CPM)
-RISC microcontrollerhandling
communication tasks
-4 SCC’s with serial rate up to 10 Mbps
-Support for many LAN/WAN protocols
-ATM SAR support (SR version only)
PC860FS -Rev.1 –01/11
PowerPC
Core
Inst.
MMU
Inst.
Cache
Data
MMU
Data
Cache
Memory Controller
External
BIU
Internal
BIU
System Functions
Real Time clock
PCMCIA Interface
SIU
SIU
16 Serial
DMA’s
Virtual
IDMA
Parallel I / O
Baud Rate
Generators
Dual -
Port
RAM Interrupt
Controller 4
Timers
Parallel
Interface
Port 32-Bit RISC µController
& Program ROM
SCC
1SCC
2SCC
3SCC
4SMC
1
Serial Interface
Time Slot Assigner
SMC
2SPI
1SPI
2
Communication Processor Module
Communication Processor Module
nTechnical Specifications
-Embedded PowerPC Core providing 105 MIPS (using Dhrystone 2.1) at 80 MHz
-System Interface Unit (SIU)
Memory Controller
Real time clock
PCMCIA interface
System functions
Bus Interface Unit
-Advanced on-chip emulation debug mode
-Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
-Completely static low-power design
-Communication Processor Module
nPackaging
-357 pin PBGA package (25 x 25 mm)
nScreening
-PBGA upscreening base upon Atmel -Grenoble standards
-Full military range (Tc = -55°C + 125°)
-Industrial range (Tc = -40°C +125°C)
BP123 -38521 Saint-Egrève Cedex -France -Tel: +33 (0)4 76 58 30 00 -Fax: +33 (0)4 76 58 34 80
For additional information:
contact your local ATMEL-Grenoble representative
or visit our web site at http://www.atmel-grenoble.com
You may also contact the PowerPC technical hotline at std.hotline@atmel-grenoble.com
The PowerPC and PowerPC603e names and the PowerPC logotype are trademarks of
International Business Machines Corporation, used under license therefrom.
Package
ZP: PBGA
TS (X) PC860 MH MZP U C
Prefix
Prototype
Type
Version
MH: Ethernet Support
SR: Ethernet and ATM Support
Temperature range: Tc:
M: -55, +125°C
V: -40, +110°C
Revision level
Screening level
-- : Standard
U: Upscreening
U/T: Upscreening+ burn-in
40
B: rev B. 0 (MH version)
C: rev C.1 (MH version)
D: rev D4; (SR version
Max internal processor speed
40: 40 MHz
50: 50 MHz
66: 66 MHz (SR only)
80: 80 MHz (SR only ) tbc
PC860 PowerQUICC™ Processor
Fact Sheet
The MPC860 PowerQUICCTM is a versatile one-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications, excelling particularly in communications and networking products. The
PowerQUICCcan be described as a next-generation MC68360 QUICC for network and data communication applications,
providing higher performance in all areas of device operation including flexibility, extensions in capability, and
integration. The MPC860 PowerQUICC, like the MC68360 QUICC integrates two processing blocks. One block is the
Embedded PowerPC Core and the second block is a Communication Processor Module (CPM) that closely resembles the
MC68360 CPM. The CPM supports four serial communications controllers (SCCs) on the device; however, there are
actually eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI)
and one I2C interface. This dual-processor architecture provides lower power consumption than traditional architectures
because the CP off-loads peripheral tasks from the Embedded PowerPC Core.
PC860 Main Features
n32-bit Embedded PowerPC Core 66 to 80 MHz
nSystem Interface Unit (SIU)
nCommunication Processor Module (CPM)
-RISC microcontrollerhandling
communication tasks
-4 SCC’s with serial rate up to 10 Mbps
-Support for many LAN/WAN protocols
-ATM SAR support (SR version only)
PC860FS -Rev.1 –01/11
PowerPC
Core
Inst.
MMU
Inst.
Cache
Data
MMU
Data
Cache
Memory Controller
External
BIU
Internal
BIU
System Functions
Real Time clock
PCMCIA Interface
SIU
SIU
16 Serial
DMA’s
Virtual
IDMA
Parallel I / O
Baud Rate
Generators
Dual -
Port
RAM Interrupt
Controller 4
Timers
Parallel
Interface
Port 32-Bit RISC µController
& Program ROM
SCC
1SCC
2SCC
3SCC
4SMC
1
Serial Interface
Time Slot Assigner
SMC
2SPI
1SPI
2
Communication Processor Module
Communication Processor Module
nTechnical Specifications
-Embedded PowerPC Core providing 105 MIPS (using Dhrystone 2.1) at 80 MHz
-System Interface Unit (SIU)
Memory Controller
Real time clock
PCMCIA interface
System functions
Bus Interface Unit
-Advanced on-chip emulation debug mode
-Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
-Completely static low-power design
-Communication Processor Module
nPackaging
-357 pin PBGA package (25 x 25 mm)
nScreening
-PBGA upscreening base upon Atmel -Grenoble standards
-Full military range (Tc = -55°C + 125°)
-Industrial range (Tc = -40°C +125°C)
BP123 -38521 Saint-Egrève Cedex -France -Tel: +33 (0)4 76 58 30 00 -Fax: +33 (0)4 76 58 34 80
For additional information:
contact your local ATMEL-Grenoble representative
or visit our web site at http://www.atmel-grenoble.com
You may also contact the PowerPC technical hotline at std.hotline@atmel-grenoble.com
The PowerPC and PowerPC603e names and the PowerPC logotype are trademarks of
International Business Machines Corporation, used under license therefrom.
Package
ZP: PBGA
TS (X) PC860 MH MZP U C
Prefix
Prototype
Type
Version
MH: Ethernet Support
SR: Ethernet and ATM Support
Temperature range: Tc:
M: -55, +125°C
V: -40, +110°C
Revision level
Screening level
-- : Standard
U: Upscreening
U/T: Upscreening+ burn-in
40
B: rev B. 0 (MH version)
C: rev C.1 (MH version)
D: rev D4; (SR version
Max internal processor speed
40: 40 MHz
50: 50 MHz
66: 66 MHz (SR only)
80: 80 MHz (SR only ) tbc
PC860 PowerQUICC™ Processor
Fact Sheet
The MPC860 PowerQUICCTM is a versatile one-chip integrated microprocessor and peripheral combination that can be
used in a variety of controller applications, excelling particularly in communications and networking products. The
PowerQUICCcan be described as a next-generation MC68360 QUICC for network and data communication applications,
providing higher performance in all areas of device operation including flexibility, extensions in capability, and
integration. The MPC860 PowerQUICC, like the MC68360 QUICC integrates two processing blocks. One block is the
Embedded PowerPC Core and the second block is a Communication Processor Module (CPM) that closely resembles the
MC68360 CPM. The CPM supports four serial communications controllers (SCCs) on the device; however, there are
actually eight serial channels: four SCCs, two serial management controllers (SMCs), one serial peripheral interface (SPI)
and one I2C interface. This dual-processor architecture provides lower power consumption than traditional architectures
because the CP off-loads peripheral tasks from the Embedded PowerPC Core.
PC860 Main Features
n32-bit Embedded PowerPC Core 66 to 80 MHz
nSystem Interface Unit (SIU)
nCommunication Processor Module (CPM)
-RISC microcontrollerhandling
communication tasks
-4 SCC’s with serial rate up to 10 Mbps
-Support for many LAN/WAN protocols
-ATM SAR support (SR version only)
PC860FS -Rev.1 –01/11
PowerPC
Core
Inst.
MMU
Inst.
Cache
Data
MMU
Data
Cache
Memory Controller
External
BIU
Internal
BIU
System Functions
Real Time clock
PCMCIA Interface
SIU
SIU
16 Serial
DMA’s
Virtual
IDMA
Parallel I / O
Baud Rate
Generators
Dual -
Port
RAM Interrupt
Controller 4
Timers
Parallel
Interface
Port 32-Bit RISC µController
& Program ROM
SCC
1SCC
2SCC
3SCC
4SMC
1
Serial Interface
Time Slot Assigner
SMC
2SPI
1SPI
2
Communication Processor Module
Communication Processor Module
nTechnical Specifications
-Embedded PowerPC Core providing 105 MIPS (using Dhrystone 2.1) at 80 MHz
-System Interface Unit (SIU)
Memory Controller
Real time clock
PCMCIA interface
System functions
Bus Interface Unit
-Advanced on-chip emulation debug mode
-Data bus dynamic bus sizing for 8-, 16-, and 32-bit buses
-Completely static low-power design
-Communication Processor Module
nPackaging
-357 pin PBGA package (25 x 25 mm)
nScreening
-PBGA upscreening base upon Atmel -Grenoble standards
-Full military range (Tc = -55°C + 125°)
-Industrial range (Tc = -40°C +125°C)
BP123 -38521 Saint-Egrève Cedex -France -Tel: +33 (0)4 76 58 30 00 -Fax: +33 (0)4 76 58 34 80
For additional information:
contact your local ATMEL-Grenoble representative
or visit our web site at http://www.atmel-grenoble.com
You may also contact the PowerPC technical hotline at std.hotline@atmel-grenoble.com
The PowerPC and PowerPC603e names and the PowerPC logotype are trademarks of
International Business Machines Corporation, used under license therefrom.
Package
ZP: PBGA
TS (X) PC860 MH MZP U C
Prefix
Prototype
Type
Version
MH: Ethernet Support
SR: Ethernet and ATM Support
Temperature range: Tc:
M: -55, +125°C
V: -40, +110°C
Revision level
Screening level
-- : Standard
U: Upscreening
U/T: Upscreening+ burn-in
40
B: rev B. 0 (MH version)
C: rev C.1 (MH version)
D: rev D4; (SR version
Max internal processor speed
40: 40 MHz
50: 50 MHz
66: 66 MHz (SR only)
80: 80 MHz (SR only ) tbc
