Product Folder Order Now Support & Community Tools & Software Technical Documents TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 TPS748 1.5-A Low-Dropout Linear Regulator With Programmable Soft-Start 1 Features 3 Description * * * * * The TPS748 low-dropout (LDO) linear regulator provides an easy-to-use robust power management solution for a wide variety of applications. Userprogrammable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and wellsuited for powering many different types of processors and ASICs. The enable input and power good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing requirements of FPGAs, DSPs, and other applications with special start-up requirements. 1 * * * * * VOUT Range: 0.8 V to 3.6 V Ultralow VIN Range: 0.8 V to 5.5 V VBIAS Range 2.7 V to 5.5 V Low Dropout: 60 mV Typical at 1.5 A, VBIAS = 5 V Power Good (PG) Output Allows Supply Monitoring or Provides a Sequencing Signal for Other Supplies 2% Accuracy Over Line, Load, and Temperature Programmable Soft-Start Provides Linear Voltage Startup VBIAS Permits Low VIN Operation With Good Transient Response Stable With Any Output Capacitor 2.2 F Available in a Small, 3-mm x 3-mm x 1-mm VSON-10 and 5 x 5 QFN-20 Packages 2 Applications * * * * * FPGA Applications DSP Core and I/O Voltages Post-Regulation Applications Applications With Special Start-up Time or Sequencing Requirements Hot-Swap and Inrush Controls A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 F, and is fully specified for TJ = -40C to 125C. The TPS748 is offered in a small, 3-mm x 3-mm, VSON-10 package, yielding a highly compact, total solution size. The device is also available in a 5 x 5 QFN-20 package for compatibility with the TPS744. Device Information(1) PART NUMBER TPS748 PACKAGE BODY SIZE (NOM) VSON (10) 3.00 mm x 3.00 mm VQFN (20) 5.00 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. SPACE SPACE SPACE Typical Application Circuit (Adjustable) Turnon Response CSS = 0nF VIN IN CIN PG EN VBIAS TPS74801 R1 GND CSS VOUT CSS = 2.2nF VOUT OUT SS CBIAS CSS = 1nF 0.5V/div R3 BIAS COUT FB 1.2V R2 1V/div VEN 0V Time (1ms/div) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com Table of Contents 1 2 3 4 5 6 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 6.1 6.2 6.3 6.4 6.5 6.6 6.7 7 1 1 1 2 4 5 Absolute Maximum Ratings ...................................... 5 ESD Ratings ............................................................ 5 Recommended Operating Conditions....................... 5 Thermal Information .................................................. 6 Electrical Characteristics........................................... 7 Typical Characteristics IOUT = 50 mA ....................... 8 Typical Characteristics IOUT = 1 A .......................... 11 Detailed Description ............................................ 12 7.1 7.2 7.3 7.4 Overview ................................................................. Functional Block Diagram ....................................... Feature Description................................................. Device Functional Modes........................................ 12 12 12 13 7.5 Programming .......................................................... 14 8 Application and Implementation ........................ 16 8.1 Application Information............................................ 16 8.2 Typical Applications ................................................ 19 9 Power Supply Recommendations...................... 22 10 Layout................................................................... 23 10.1 Layout Guidelines ................................................. 23 10.2 Layout Example .................................................... 24 10.3 Estimating Junction Temperature ......................... 25 11 Device and Documentation Support ................. 27 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Device Support...................................................... Documentation Support ....................................... Receiving Notification of Documentation Updates Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 27 27 27 27 27 27 28 12 Mechanical, Packaging, and Orderable Information ........................................................... 28 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision K (February 2015) to Revision L Page * Added active pulldown to Functional Block Diagram ........................................................................................................... 12 * Added Equation 1 and corresponding description to Enable/Shutdown section.................................................................. 13 Changes from Revision J (January 2012) to Revision K Page * Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ................................................................................................. 1 * Changed part number as printed in document from TPS74801 to TPS748 ......................................................................... 1 * Changed SON-10 package references in document to VSON-10 ......................................................................................... 1 * Changed second paragraph of Description section .............................................................................................................. 1 * Changed pin descriptions throughout Pin Functions table .................................................................................................... 4 * Changed condition statement for Absolute Maximum Ratings .............................................................................................. 5 * Changed "free-air" to "junction" temperature in condition statement for Recommended Operating Conditions.................... 5 * Changed values for both packages in Thermal Information .................................................................................................. 6 * Changed test condition for output noise voltage from 0.001 F to 1 nF ................................................................................ 7 * Changed y-axis title in Figure 3 from abbreviation (IOUT) to text (Output Current) ................................................................. 8 * Changed y-axis title in Figure 4 from abbreviation (IOUT) to text (Output Current) ................................................................ 8 * Changed title for Figure 4 ...................................................................................................................................................... 8 * Changed y-axis and x-axis titles in Figure 5 from abbreviations to text................................................................................. 8 * Changed x-axis title in Figure 6 from abbreviation (VDC) to text (Dropout Voltage) .............................................................. 8 * Changed x-axis title in Figure 7 from abbreviation (VDO) to text (Dropout Voltage) .............................................................. 8 * Changed y-axis and x-axis titles in Figure 8 from abbreviations to text ................................................................................ 8 * Changed y-axis and x-axis titles in Figure 13 from abbreviations to text .............................................................................. 9 * Changed title for Figure 13 .................................................................................................................................................... 9 2 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 * Changed x-axis title in Figure 14 from abbreviation (IBIAS) to text (Bias Current) .................................................................. 9 * Changed Figure 24; added capacitor size indication for CSS .............................................................................................. 16 Changes from Revision I (November 2010) to Revision J * Page Changed TJ range in Absolute Maximum Ratings table......................................................................................................... 5 Changes from Revision H (October, 2010) to Revision I * Page Corrected equation for Table 2............................................................................................................................................. 15 Changes from Revision G (August, 2010) to Revision H * Page Corrected typo in Figure 38 .................................................................................................................................................. 25 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 3 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 5 Pin Configuration and Functions DRC Package 10-Pin VSON With Thermal Pad Top View NC NC NC OUT 4 3 2 1 IN 6 20 OUT IN 7 19 OUT IN 8 18 OUT PG 9 17 NC BIAS 10 16 FB 13 14 15 NC NC SS TPS74801 GND 12 EN 5 8 FB 7 SS 6 GND GND BIAS 4 IN Thermal Pad 11 PG 3 5 10 OUT 9 OUT IN 2 EN IN 1 RGW Package 20-Pin VQFN Top View Pin Functions PIN I/O DESCRIPTION 10 I Bias input voltage for error amplifier, reference, and internal control circuits. A 1-F or larger input capacitor is recommended for optimal performance. If IN is connected to BIAS, a 4.7-F or larger capacitor must be used. 5 11 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. FB 8 16 I Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. GND 6 12 -- IN 1, 2 5-8 I Input to the device. A 1-F or larger input capacitor is recommended for optimal performance. NC N/A 2-4, 13, 14, 17 -- No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. OUT 9, 10 1, 18-20 O Regulated output voltage. A small capacitor (total typical capacitance 2.2 F, ceramic) is needed from this pin to ground to assure stability. NAME VSON VQFN BIAS 4 EN Ground PG 3 9 O Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 k to 1 M should be connected from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary. SS 7 15 -- Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 s. -- Must be soldered to the ground plane for increased thermal performance. Internally connected to ground. Thermal pad 4 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 6 Specifications 6.1 Absolute Maximum Ratings At TJ = -40C to 125C, unless otherwise noted. All voltages are with respect to GND. (1) MIN MAX UNIT Input voltage VIN, VBIAS -0.3 6 V Enable voltage VEN -0.3 6 V Power good voltage VPG -0.3 6 V PG sink current IPG 0 1.5 mA Soft-start voltage VSS -0.3 6 V Feedback voltage VFB -0.3 6 V Output voltage VOUT -0.3 VIN + 0.3 V Maximum output current IOUT Internally limited Output short-circuit duration Continuous total power dissipation Temperature (1) Indefinite PDISS See Thermal Information Operating junction, TJ -40 150 Storage, Tstg -55 150 C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) 2000 Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) 500 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating junction temperature range (unless otherwise noted) VIN Input supply voltage VEN Enable supply voltage VBIAS (1) NOM MAX VOUT + 0.3 5.5 V 0 VIN 5.5 V (2) (2) VOUT + VDO (VBIAS) VOUT + 1.6 UNIT 5.5 V VOUT Output voltage 0.8 3.3 V IOUT Output current 0 1.5 COUT Output capacitor CIN Input capacitor (3) CBIAS Bias capacitor 0.1 TJ Operating junction temperature -40 (1) (2) (3) BIAS supply voltage MIN VOUT + VDO (VIN) 2.2 A F 1 F 1 F 125 C BIAS supply is required when VIN is below VOUT + 1.62 V. VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 F. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 5 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 6.4 Thermal Information TPS748 (2) THERMAL METRIC (1) Junction-to-ambient thermal resistance (3) RJA (4) RGW (VQFN) DRC (VSON) 20 PINS 10 PINS UNIT 35.6 44.2 C/W RJC(top) Junction-to-case (top) thermal resistance 33.3 50.3 C/W RJB Junction-to-board thermal resistance (5) 15 19.6 C/W JT Junction-to-top characterization parameter (6) 0.4 0.7 C/W 15.2 17.8 C/W 3.8 4.3 C/W (7) JB Junction-to-board characterization parameter RJC(bot) Junction-to-case (bottom) thermal resistance (8) (1) (2) (3) (4) (5) (6) (7) (8) 6 For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. Thermal data for the RGW and DRC packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations: (a) i. RGW: The exposed pad is connected to the PCB ground layer through a 4x4 thermal via array. . ii. DRC: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array. (b) i. RGW: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage. . ii. DRC: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage. (c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in x 3in copper area. To understand the effects of the copper area on thermal performance, see the Estimating Junction Temperature section of this data sheet. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain JA using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 6.5 Electrical Characteristics At VEN = 1.1 V, VIN = VOUT + 0.3 V, CBIAS = 0.1 F, CIN = COUT = 10 F, CNR = 1 nF, IOUT = 50 mA, VBIAS = 5.0 V, and TJ = -40C to 125C, unless otherwise noted. Typical values are at TJ = 25C. PARAMETER TEST CONDITIONS MIN TYP UNIT Input voltage range VBIAS BIAS pin voltage range VREF Internal reference (Adj.) TJ = 25C Output voltage range VIN = 5 V, IOUT = 1.5 A VREF Accuracy (1) 2.97 V VBIAS 5.5 V, 50 mA IOUT 1.5 A -2% VOUT(IOUT) Line regulation VOUT(nom) + 0.3 VIN 5.5 V 0.03 %/V VOUT Load regulation 50 mA IOUT 1.5 A 0.09 %/A VIN dropout voltage (2) IOUT = 1.5 A, VBIAS - VOUT(nom) 3.25 V (3) VOUT(VIN) VDO VBIAS dropout voltage VOUT + VDO MAX VIN (2) ICL Current limit IBIAS BIAS pin current ISHDN Shutdown supply current (IGND) IFB Feedback pin current Power-supply rejection (VIN to VOUT) PSRR Power-supply rejection (VBIAS to VOUT) 2.7 0.796 IOUT = 1.5 A, VIN = VBIAS VOUT = 80% x VOUT(nom) 0.8 0.5% -1 V 5.5 V 0.804 V 3.6 V 2% 60 165 mV 1.31 1.6 V 5.5 A 2 VEN 0.4 V 5.5 1 2 mA 1 50 A 0.150 1 A 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 60 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 30 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 50 300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V 30 dB dB Vn Output noise voltage 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF tSTR Minimum startup time RLOAD for IOUT = 1.0 A, CSS = open 200 s ISS Soft-start charging current VSS = 0.4 V 440 nA VEN(hi) Enable input high level VEN(lo) Enable input low level VEN(hys) Enable pin hysteresis VEN(dg) Enable pin deglitch time IEN Enable pin current VEN = 5 V VIT PG trip threshold VOUT decreasing VHYS PG trip hysteresis VPG(lo) PG output low voltage IPG = 1 mA (sinking), VOUT < VIT IPG(lkg) PG leakage current VPG = 5.25 V, VOUT > VIT TJ Operating junction temperature TSD Thermal shutdown temperature (1) (2) (3) 25 x VOUT 1.1 VRMS 5.5 0 V 0.4 V 50 mV 20 85 s 0.1 1 A 90 94 %VOUT 3 0.1 -40 Shutdown, temperature increasing 165 Reset, temperature decreasing 140 %VOUT 0.3 V 1 A 125 C C Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account. Dropout is defined as the voltage from VIN to VOUT when VOUT is 3% below nominal. 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 7 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 6.6 Typical Characteristics IOUT = 50 mA At TJ = 25C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 F, CBIAS = 4.7 F, and COUT = 10 F, unless otherwise noted. 0.20 0.5 0.15 0.4 Change in VOUT (%) Change in VOUT (%) 0.3 0.10 -40C 0.05 0 +25C -0.05 +125C -0.01 0.2 -40C 0.1 0 -0.1 +125C -0.2 +25C -0.3 -0.15 -0.4 -0.20 -0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0.5 5.0 1.0 1.5 2.0 VIN - VOUT (V) 2.5 3.0 3.5 4.0 VBIAS - VOUT (V) Figure 1. VIN Line Regulation Figure 2. VBIAS Line Regulation 0.5 1.2 0.4 0.3 Change in VOUT (%) Change in VOUT (%) 1.0 0.8 0.6 0.4 0.2 +125C 0.1 0 -40C +25C -0.1 -0.2 -0.3 0.2 -0.4 0 0 10 20 30 40 -0.5 0.05 50 0.5 Figure 3. Load Regulation 200 90 180 Dropout Voltage (mV) Dropout Voltage (mV) +125C 70 60 50 40 +25C 30 20 IOUT = 1.5A 160 140 120 +125C 100 +25C 80 60 40 -40C 10 -40C 20 0 0 0 0.5 1.0 1.5 1.0 Output Current (A) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VBIAS - VOUT (V) Figure 5. VIN Dropout Voltage vs IOUT and Temperature (TJ) 8 1.5 Figure 4. Load Regulation at Light Load 100 80 1.0 Output Current (A) Output Current (mA) Figure 6. VIN Dropout Voltage vs (VBIAS - VOUT) and Temperature (TJ) Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 Typical Characteristics IOUT = 50 mA (continued) At TJ = 25C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 F, CBIAS = 4.7 F, and COUT = 10 F, unless otherwise noted. 200 2000 160 Dropout Voltage (mV) Dropout Voltage (mV) 2200 IOUT = 0.5A 180 140 120 100 +25C 80 +125C 60 40 -40C 1800 1600 +125C 1400 1200 +25C 1000 -40C 800 20 600 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 4.5 0.5 90 80 IOUT = 0.1A IOUT = 1.5A 70 60 50 40 IOUT = 0.5A 30 VIN = 1.8V VOUT = 1.2V VBIAS = 5V CSS = 1nF 20 10 0 10 100 Power-Supply Rejection Ratio (dB) 90 Power-Supply Rejection Ratio (dB) 1.5 Figure 8. VBIAS Dropout Voltage vs IOUT and Temperature (TJ) Figure 7. VIN Dropout Voltage vs (VBIAS - VOUT) and Temperature (TJ) 80 70 IOUT = 100mA 60 50 40 30 VIN = 1.8V VOUT = 1.2V CSS = 1nF VBIAS = 5V 20 10 0 1k 10k 100k 1M 10M 10 100 Frequency (Hz) 70 1kHz 60 10kHz 50 40 100kHz 30 20 500kHz 10 0 0 0.25 0.50 0.75 1.00 1.25 1k 10k 100k 1M 10M 1.50 1.75 2.00 2.25 Figure 10. VIN PSRR vs Frequency Output Spectral Noise Density (mV/OHz) VOUT = 1.2V IOUT = 1.5A CSS = 1nF 80 IOUT = 1.5A Frequency (Hz) Figure 9. VBIAS PSRR vs Frequency 90 Power-Supply Rejection Ratio (dB) 1.0 Output Current (A) VBIAS - VOUT (V) 1 IOUT = 100mA VOUT = 1.2V CSS = 0nF 0.1 CSS = 10nF CSS = 1nF 0.01 100 VIN - VOUT (V) 1k 10k 100k Frequency (Hz) Figure 11. VIN PSRR vs (VIN - VOUT) Figure 12. Noise Spectral Density Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 9 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com Typical Characteristics IOUT = 50 mA (continued) At TJ = 25C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 F, CBIAS = 4.7 F, and COUT = 10 F, unless otherwise noted. 2.0 2.0 1.8 1.4 1.2 1.0 0.8 +25C -40C 0.6 1.4 1.2 +25C 1.0 0.8 0.6 0.4 0.4 0.2 0.2 0 -40C 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Output Current (A) VBIAS (V) Figure 13. BIAS Pin Current vs Output Current and Temperature (TJ) Figure 14. BIAS Pin Current vs VBIAS and Temperature (TJ) 1.0 500 VOL Low-Level PG Voltage (V) 475 450 ISS (nA) +125C 1.6 Bias Current (mA) Bias Current (mA) 1.8 +125C 1.6 425 400 375 350 325 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 300 -50 -25 0 25 50 75 100 125 0 2 4 Junction Temperature (C) 8 10 12 PG Current (mA) Figure 15. Soft-Start Charging Current (ISS) vs Temperature (TJ) Figure 16. Low-Level PG Voltage vs Current 4.0 VOUT = 0.8V 3.8 +125C 3.6 Current Limit (A) 6 3.4 3.2 3.0 -40C 2.8 +25C 2.6 2.4 2.2 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VBIAS - VOUT (V) Figure 17. Current Limit vs (VBIAS - VOUT) 10 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 6.7 Typical Characteristics IOUT = 1 A At TJ = 25C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 F, CBIAS = 4.7 F, and COUT = 10 F, unless otherwise noted. CSS = 1nF COUT = 10mF (Ceramic) COUT = 10mF (Ceramic) 100mV/div 100mV/div COUT = 2.2mF (Ceramic) 100mV/div CSS = 1nF 3.8V 5.0V 1V/div 1V/div 1V/ms 3.3V 1V/ms 1.8V Time (50ms/div) Time (50ms/div) Figure 18. VBIAS Line Transient Figure 19. VIN Line Transient COUT = 470mF (OSCON) CSS = 0nF 100mV/div COUT = 10mF (Ceramic) 100mV/div CSS = 1nF 0.5V/div VOUT CSS = 2.2nF COUT = 2.2mF (Ceramic) 100mV/div 1.2V 1.5A CSS = 1nF 1A/div 50mA 1V/div VEN 0V 1A/ms Time (50ms/div) Time (1ms/div) Figure 20. Output Load Transient Response Figure 21. Turnon Response VIN = VBIAS = VEN 1V/div VPG (500mV/div) VOUT Time (20ms/div) Figure 22. Power-Up/Power-Down Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 11 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 7 Detailed Description 7.1 Overview The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable with any capacitor type of value 2.2 F or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications. The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required by processor-intensive systems. 7.2 Functional Block Diagram IN Current Limit BIAS UVLO OUT V OUT 833 Thermal Limit 0.44 A R1 SS CSS Soft-Start Discharge 0.8-V Reference FB PG EN Hysteresis and Deglitch R2 0.9 x VREF GND 7.3 Feature Description 7.3.1 Enable/Shutdown The enable (EN) pin is active high and is compatible with standard digital signaling levels. VEN below 0.4 V turns the regulator off, while VEN above 1.1 V turns the regulator on. Unlike many regulators, the enable circuitry has hysteresis and deglitching for use with relatively slowly ramping analog signals. This configuration allows the TPS748 to be enabled by connecting the output of another supply to the EN pin. The enable circuitry typically has 50 mV of hysteresis and a deglitch circuit to help avoid on-off cycling as a result of small glitches in the VEN signal. The enable threshold is typically 0.8 V and varies with temperature and process variations. Temperature variation is approximately -1 mV/C; process variation accounts for most of the rest of the variation to the 0.4-V and 1.1-V limits. If precise turnon timing is required, a fast rise-time signal must be used to enable the TPS748. 12 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 Feature Description (continued) If not used, EN can be connected to either IN or BIAS. If EN is connected to IN, it should be connected as close as possible to the largest capacitance on the input to prevent voltage droops on that line from triggering the enable circuit. The TPS748 has an internal active pulldown circuit that connects the output to GND through an 833- resistor when the device is disabled. This resistor discharges the output with a time constant of: W 833 u RL * u COUT (c) 833 RL (1) 7.3.2 Power Good The power good (PG) pin is an open-drain output and can be connected to any 5.5-V or lower rail through an external pull-up resistor. This pin requires at least 1.1 V on VBIAS in order to have a valid output. The PG output is high-impedance when VOUT is greater than VIT + VHYS. If VOUT drops below VIT or if VBIAS drops below 1.9 V, the open-drain output turns on and pulls the PG output low. The PG pin also asserts when the device is disabled. The recommended operating condition of PG pin sink current is up to 1 mA, so the pull-up resistor for PG should be in the range of 10 k to 1 M. If output voltage monitoring is not needed, the PG pin can be left floating. 7.3.3 Internal Current Limit The TPS748 features a factory-trimmed current limit that is flat over temperature and supply voltage. The current limit allows the device to supply surges of up to 2 A and maintain regulation. The current limit responds in approximately 10 s to reduce the current during a short-circuit fault. The internal current limit protection circuitry of the TPS748 is designed to protect against overload conditions. It is not intended to allow operation above the rated current of the device. Continuously running the TPS748 above the rated current degrades device reliability. 7.3.4 Thermal Protection Thermal protection disables the output when the junction temperature rises to approximately 160C, allowing the device to cool. When the junction temperature cools to approximately 140C, the output circuitry is enabled. Depending on power dissipation, thermal resistance, and ambient temperature the thermal protection circuit may cycle on and off. This cycling limits the dissipation of the regulator, protecting it from damage as a result of overheating. Activation of the thermal protection circuit indicates excessive power dissipation or inadequate heatsinking. For reliable operation, junction temperature should be limited to 125C maximum. To estimate the margin of safety in a complete design (including heatsink), increase the ambient temperature until thermal protection is triggered; use worst-case loads and signal conditions. For good reliability, thermal protection should trigger at least 40C above the maximum expected ambient condition of the application. This condition produces a worst-case junction temperature of 125C at the highest expected ambient temperature and worst-case load. The internal protection circuitry of the TPS748 is designed to protect against overload conditions. It is not intended to replace proper heatsinking. Continuously running the TPS748 into thermal shutdown degrades device reliability. 7.4 Device Functional Modes 7.4.1 Normal Operation The device regulates to the nominal output voltage under the following conditions: * * * * The input voltage and bias voltage are both at least at the respective minimum specifications. The enable voltage has previously exceeded the enable rising threshold voltage and has not decreased below the enable falling threshold. The output current is less than the current limit. The device junction temperature is less than the maximum specified junction temperature. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 13 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com Device Functional Modes (continued) 7.4.2 Dropout Operation If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other conditions are met for normal operation, the device operates in dropout mode. In this condition, the output voltage is the same as the input voltage minus the dropout voltage. The transient performance of the device is significantly degraded because the pass device is in a triode state and no longer controls the current through the LDO. Line or load transients in dropout can result in large output voltage deviations. 7.4.3 Disabled The device is disabled under the following conditions: * The input or bias voltages are below the respective minimum specifications. * The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising threshold. * The device junction temperature is greater than the thermal shutdown temperature. Table 1 shows the conditions that lead to the different modes of operation. Table 1. Device Functional Mode Comparison PARAMETER OPERATING MODE VIN VEN Normal mode VIN > VOUT(nom) + VDO (VIN) Dropout mode VIN < VOUT(nom) + VDO (VIN) VIN < VIN(min) Disabled mode (any true condition disables the device) VBIAS IOUT TJ VEN > VEN(high) VBIAS VOUT + 1.6 V I OUT < ICL T J < 125C VEN > VEN(high) VBIAS < VOUT + 1.6 V -- TJ < 125C VEN < VEN(low) VBIAS < VBIAS(min) -- TJ > 165C 7.5 Programming 7.5.1 Programmable Soft-Start The TPS748 features a programmable, monotonic, voltage-controlled soft-start that is set with an external capacitor (CSS). This feature is important for many applications because it eliminates power-up initialization problems when powering FPGAs, DSPs, or other processors. The controlled voltage ramp of the output also reduces peak inrush current during start-up, minimizing start-up transient events to the input power bus. To achieve a linear and monotonic soft-start, the TPS748 error amplifier tracks the voltage ramp of the external soft-start capacitor until the voltage exceeds the internal reference. The soft-start ramp time depends on the softstart charging current (ISS), soft-start capacitance (CSS), and the internal reference voltage (VREF), and can be calculated using Equation 2: (VREF CSS) tSS = ISS (2) If large output capacitors are used, the device current limit (ICL) and the output capacitor may set the start-up time. In this case, the start-up time is given by Equation 3: (VOUT(NOM) COUT) tSSCL = ICL(MIN) where * * * VOUT(nom) is the nominal output voltage, COUT is the output capacitance, and ICL(min) is the minimum current limit for the device. (3) In applications where monotonic startup is required, the soft-start time given by Equation 2 should be set greater than Equation 3. 14 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 Programming (continued) The maximum recommended soft-start capacitor is 15 nF. Larger soft-start capacitors can be used and do not damage the device; however, the soft-start capacitor discharge circuit may not be able to fully discharge the softstart capacitor when enabled. Soft-start capacitors larger than 15 nF could be a problem in applications where it is necessary to rapidly pulse the enable pin and still require the device to soft-start from ground. CSS must be low-leakage; X7R, X5R, or C0G dielectric materials are preferred. Refer to Table 2 for suggested soft-start capacitor values. Table 2. Standard Capacitor Values for Programming the Soft-Start Time (1) tSS(s) = (1) CSS SOFT-START TIME Open 0.1 ms 270 pF 0.5 ms 560 pF 1 ms 2.7 nF 5 ms 5.6 nF 10 ms 10 nF 18 ms VREF x CSS 0.8V x CSS(F) = 0.44mA ISS where tSS(s) = soft-start time in seconds. Another option to set the start-up rate is to use a feedforward capacitor; see the Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator application report for more information. 7.5.2 Sequencing Requirements VIN, VBIAS, and VEN can be sequenced in any order without causing damage to the device. However, for the softstart function to work as intended, certain sequencing rules must be applied. Connecting EN to IN is acceptable for most applications, as long as VIN is greater than 1.1 V and the ramp rate of VIN and VBIAS is faster than the set soft-start ramp rate. There are several different start-up responses that are possible, but not typical: * * * * If the ramp rate of the input sources is slower than the set soft-start time, the output tracks the slower supply minus the dropout voltage until it reaches the set output voltage. If EN is connected to BIAS, the device soft-starts as programmed, provided that VIN is present before VBIAS. If VBIAS and VEN are present before VIN is applied and the set soft-start time has expired, then VOUT tracks VIN. If the soft-start time has not expired, the output tracks VIN until VOUT reaches the value set by the charging soft-start capacitor. Figure 23 shows the use of an RC-delay circuit to hold off VEN until VBIAS has ramped. This technique can also be used to drive EN from VIN. An external control signal can also be used to enable the device after VIN and VBIAS are present. VIN IN VOUT OUT R1 CIN BIAS TPS74801 FB EN SS COUT R2 R VBIAS CBIAS GND C CSS Figure 23. Soft-Start Delay Using an RC Circuit to Enable the Device Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 15 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The TPS74801 belongs to a family of low-dropout regulators that feature soft-start capability. These regulators use a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages. The use of an NMOS-pass FET offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS74801 to be stable with any capacitor type of value 2.2 F or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications. The TPS74801 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits startup inrush currents that may be caused by large capacitive loads. A power good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required by processor-intensive systems. 8.1.1 Adjusting the Output Voltage Figure 24 shows the typical application circuit for the TPS748 adjustable output device. VIN IN CIN 1 mF PG R3 BIAS EN VBIAS TPS74801 R1 SS CBIAS 1 mF VOUT OUT FB GND CSS 1 nF COUT 10 mF R2 ( VOUT = 0.8 1 + R1 R2 ) Figure 24. Typical Application Circuit for the TPS748 (Adjustable) 16 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 Application Information (continued) R1 and R2 can be calculated for any output voltage using the formula shown in Figure 24. Table 3 lists sample resistor values of common output voltages. In order to achieve the maximum accuracy specifications, R2 should be 4.99 k. Table 3. Standard 1% Resistor Values for Programming the Output Voltage (1) (1) R1 (k) R2 (k) VOUT (V) Short Open 0.8 0.619 4.99 0.9 1.13 4.53 1.0 1.37 4.42 1.05 1.87 4.99 1.1 2.49 4.99 1.2 4.12 4.75 1.5 3.57 2.87 1.8 3.57 1.69 2.5 3.57 1.15 3.3 VOUT = 0.8 x (1 + R1/R2). SPACE NOTE When VBIAS and VEN are present and VIN is not supplied, this device outputs approximately 50 A of current from OUT. Although this condition does not cause any damage to the device, the output current may charge up the OUT node if total resistance between OUT and GND (including external feedback resistors) is greater than 10 k. 8.1.2 Input, Output, and Bias Capacitor Requirements The device is designed to be stable for all available types and values of output capacitors 2.2 F. The device is also stable with multiple capacitors in parallel, which can be of any type or value. The capacitance required on the IN and BIAS pins strongly depends on the input supply source impedance. To counteract any inductance in the input, the minimum recommended capacitor for VIN is 1 F and minimum recommended capacitor for VBIAS is 0.1 F. If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for VBIAS is 4.7 F. Good quality, low ESR capacitors should be used on the input; ceramic X5R and X7R capacitors are preferred. These capacitors should be placed as close the pins as possible for optimum performance. 8.1.3 Transient Response The TPS748 was designed to have excellent transient response for most applications with a small amount of output capacitance. In some cases, the transient response may be limited by the transient response of the input supply. This limitation is especially true in applications where the difference between the input and output is less than 300 mV. In this case, adding additional input capacitance improves the transient response much more than just adding additional output capacitance would do. With a solid input supply, adding additional output capacitance reduces undershoot and overshoot during a transient event; refer to Figure 20 in the Typical Characteristics section. Because the TPS748 is stable with output capacitors as low as 2.2 F, many applications may then need very little capacitance at the LDO output. For these applications, local bypass capacitance for the powered device may be sufficient to meet the transient requirements of the application. This design reduces the total solution cost by avoiding the need to use expensive, high-value capacitors at the LDO output. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 17 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 8.1.4 Dropout Voltage The TPS748 offers very low dropout performance, making it well-suited for high-current, low VIN/low VOUT applications. The low dropout of the TPS748 allows the device to be used in place of a dc/dc converter and still achieve good efficiency. Equation 4 provides a quick estimate of the efficiency. VOUT IOUT V OUT at IOUT >> IQ Efficiency VIN VIN (IIN + IQ) (4) This efficiency provides designers with the power architecture for their applications to achieve the smallest, simplest, and lowest cost solutions. There are two different specifications for dropout voltage with the TPS748. The first specification (see Figure 25) is referred to as VIN Dropout and is used when an external bias voltage is applied to achieve low dropout. This specification assumes that VBIAS is at least 3.25 V (1) above VOUT, which is the case for VBIAS when powered by a 5.0-V rail with 5% tolerance and with VOUT = 1.5 V. If VBIAS is higher than VOUT +3.25 V (1), VIN dropout is less than specified. The second specification (illustrated in Figure 31) is referred to as VBIAS Dropout and applies to applications where IN and BIAS are tied together. This option allows the device to be used in applications where an auxiliary bias voltage is not available or low dropout is not required. Dropout is limited by BIAS in these applications because VBIAS provides the gate drive to the pass FET; therefore, VBIAS must be 1.6 V above VOUT. Because of this usage, IN and BIAS tied together become a highly inefficient solution that can consume large amounts of power. Pay attention not to exceed the power rating of the IC package. 8.1.5 Output Noise The TPS748 provides low output noise when a soft-start capacitor is used. When the device reaches the end of the soft-start cycle, the soft-start capacitor serves as a filter for the internal reference. By using a 1-nF soft-start capacitor, the output noise is reduced by half and is typically 30 VRMS for a 1.2-V output (10 Hz to 100 kHz). Further increasing CSS has little effect on noise. Because most of the output noise is generated by the internal reference, the noise is a function of the set output voltage. The RMS noise with a 1-nF soft-start capacitor is given in Equation 5: ( VN(mVRMS) = 25 mVRMS V )x V OUT(V) (5) The low output noise of the TPS748 makes it a good choice for powering transceivers, PLLs, or other noisesensitive circuitry. (1) 18 3.25 V is a test condition of this device and can be adjusted by referring to Figure 6. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 8.2 Typical Applications 8.2.1 FPGA I/O Supply at 1.5 V With a Bias Rail BIAS Reference IN VBIAS = 5V 5% VIN = 1.8V VOUT = 1.5V IOUT = 1.5A Efficiency = 83% OUT VOUT COUT FB Simplified Block Diagram Figure 25. Typical Application of the TPS748 Using an Auxiliary Bias Rail 8.2.1.1 Design Requirements This application powers the I/O rails of an FPGA , at VOUT(nom) = 1.5 V and IOUT(dc) = 1.5 A. The available external supply voltages are 1.8 V, 3.3 V and 5 V. 8.2.1.2 Detailed Design Procedure First, determine what supplies to use for the input and bias rails. A 1.8-V input can be stepped down to 1.5 V at 1.5 A if an external bias is provided, because the maximum dropout voltage is 165 mV if VBIAS is at least 3.25 V higher than VOUT. To achieve this voltage step, the bias rail is supplied by the 5-V supply. The approximation in Equation 4 estimates the efficiency at 83.3%. The output voltage then must be set to 1.5 V. As Table 3 describes, set R1 = 4.12 k and R2= 4.75 k to obtain the required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer to Input, Output, and Bias Capacitor Requirements for CIN = 1 F, CBIAS = 1 F, and COUT = 2.2 F. Use CSS = 1 nF for a typical 1.8-ms start-up time. Figure 25 shows a simplified version of the final circuit. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 19 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com Typical Applications (continued) 8.2.1.3 Application Curves CSS = 1nF COUT = 10mF (Ceramic) COUT = 10mF (Ceramic) 100mV/div 100mV/div COUT = 2.2mF (Ceramic) 100mV/div CSS = 1nF 3.8V 5.0V 1V/div 1V/div 1V/ms 3.3V 1V/ms 1.8V Time (50ms/div) Time (50ms/div) Figure 26. VBIAS Line Transient Figure 27. VIN Line Transient COUT = 470mF (OSCON) CSS = 0nF 100mV/div COUT = 10mF (Ceramic) 100mV/div CSS = 1nF 0.5V/div VOUT CSS = 2.2nF COUT = 2.2mF (Ceramic) 100mV/div 1.2V 1.5A CSS = 1nF 1A/div 1V/div VEN 0V 1A/ms 50mA Time (50ms/div) Time (1ms/div) Figure 28. Output Load Transient Response Figure 29. Turnon Response VIN = VBIAS = VEN 1V/div VPG (500mV/div) VOUT Time (20ms/div) Figure 30. Power-Up/Power-Down 20 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 Typical Applications (continued) 8.2.2 FPGA I/O Supply at 1.5 V Without a Bias Rail VIN BIAS Reference IN VBIAS = 3.3V 5% VIN = 3.3V 5V VOUT = 1.5V IOUT = 1.5A Efficiency = 45% OUT VOUT COUT FB Simplified Block Diagram Figure 31. Typical Application of the TPS748 Without an Auxiliary Bias Rail 8.2.2.1 Design Requirements The application powers the I/O rails of an FPGA, at VOUT(nom) = 1.5 V and IOUT(max) = 1.5 A. The only available rail is 3.3 V. The I/O pins are driven for only short durations with a 5% duty cycle, so thermal issues are not a concern. 8.2.2.2 Detailed Design Procedure There is only one available rail; therefore, the input supply and the bias supply are connected together on the 3.3-V input supply. The output voltage must be set to 1.5 V. As Table 3 describes, set R1 = 4.12 k and R2= 4.75 k to obtain the required output voltage. The minimum capacitor sizing is desired to reduce the total solution size footprint; refer to Input, Output, and Bias Capacitor Requirements for CIN = CBIAS = 4.7 F, and COUT = 2.2 F. Use CSS = 1 nF for a typical 1.8-ms start-up time. Figure 31 shows the TPS748 configured without a bias rail. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 21 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com Typical Applications (continued) 8.2.2.3 Application Curves 90 Power-Supply Rejection Ratio (dB) 2200 Dropout Voltage (mV) 2000 1800 1600 +125C 1400 1200 +25C 1000 -40C 800 80 IOUT = 0.1A 70 60 50 40 IOUT = 0.5A 30 VIN = 1.8V VOUT = 1.2V VBIAS = 5V CSS = 1nF 20 10 0 600 0 0.5 1.0 1.5 10 100 1k Figure 32. VBIAS Dropout Voltage vs IOUT and Temperature (TJ) 4.0 100k 1M 10M Figure 33. VBIAS PSRR vs Frequency VOUT = 0.8V 3.8 Current Limit (A) 10k Frequency (Hz) Output Current (A) CSS = 1nF +125C 3.6 IOUT = 1.5A COUT = 10mF (Ceramic) 100mV/div 3.4 3.2 COUT = 2.2mF (Ceramic) 100mV/div 3.0 -40C 2.8 +25C 5.0V 2.6 2.4 1V/div 2.2 1V/ms 3.3V 2.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Time (50ms/div) Figure 35. VBIAS Line Transient VBIAS - VOUT (V) Figure 34. Current Limit vs (VBIAS - VOUT) 9 Power Supply Recommendations The TPS748 is designed to operate from an input voltage up to 5.5 V, provided the bias rail is at least 1.62 V higher than the input supply and dropout requirements are met. The bias rail and the input supply should both provide adequate headroom and current for the device to operate normally. Connect a low output impedance power supply directly to the IN pin of the TPS748. This supply must have at least 1 F of capacitance near the IN pin for optimal performance. A supply with similar requirements must also be connected directly to the bias rail with a separate 1-F or larger capacitor. If the IN pin is tied to the bias pin, a minimum 4.7 F of capacitance is needed for performance. To increase the overall PSRR of the solution at higher frequencies, use a pi-filter or ferrite bead before the input capacitor. 22 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 10 Layout 10.1 Layout Guidelines An optimal layout can greatly improve transient performance, PSR, and noise. To minimize the voltage drop on the input of the device during load transients, the capacitance on IN and BIAS should be connected as close as possible to the device. This capacitance also minimizes the effects of parasitic inductance and resistance of the input source and can, therefore, improve stability. To achieve optimal transient performance and accuracy, the top side of R1 in Figure 24 should be connected as close as possible to the load. If BIAS is connected to IN, it is recommended to connect BIAS as close to the sense point of the input supply as possible. This connection minimizes the voltage drop on BIAS during transient conditions and can improve the turnon response. Knowing the device power dissipation and proper sizing of the thermal plane that is connected to the thermal pad is critical to avoiding thermal shutdown and ensuring reliable operation. Power dissipation of the device depends on input voltage and load conditions and can be calculated using Equation 6: PD = (VIN - VOUT) IOUT (6) Power dissipation can be minimized and greater efficiency can be achieved by using the lowest possible input voltage necessary to achieve the required output voltage regulation. On both the VSON (DRC) and QFN (RGW) packages, the primary conduction path for heat is through the exposed pad to the printed circuit board (PCB). The pad can be connected to ground or be left floating; however, it should be attached to an appropriate amount of copper PCB area to ensure the device does not overheat. The maximum junction-to-ambient thermal resistance depends on the maximum ambient temperature, maximum device junction temperature, and power dissipation of the device and can be calculated using Equation 7: (+125C - TA) RqJA = PD (7) Knowing the maximum RJA, the minimum amount of PCB copper area needed for appropriate heatsinking can be estimated using Figure 36. 140 DRC RGW 120 qJA (C/W) 100 80 60 40 20 0 0 Note: 1 2 4 5 7 3 6 Board Copper Area (in2) 8 9 10 JA value at board size of 9 in2 (that is, 3 in x 3i n) is a JEDEC standard. Figure 36. JA vs Board Size Figure 36 shows the variation of JA as a function of ground plane copper area in the board. It is intended only as a guideline to demonstrate the effects of heat spreading in the ground plane and should not be used to estimate actual thermal performance in real application environments. NOTE When the device is mounted on an application PCB, TI strongly recommends using JT and JB, as explained in Estimating Junction Temperature. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 23 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 10.2 Layout Example Input GND Plane IN NC NC NC OUT CIN 5 4 3 2 1 VIN Plane VOUT Plane IN 6 20 OUT IN 7 19 OUT IN 8 PG 9 17 NC BIAS 10 16 FB/ SNS 11 12 13 14 15 GND NC NC SS CBIAS 18 OUT Thermal Pad EN R(PULLUP) R1 COUT R1 and R2 should be connected close to the load, COUT should be as near to the LDO as possible R2 CSS Keep the ground planes on the same side of the PCB if possible to improve thermal disappation Output GND Plane (1) Denotes thermal vias (2) Denotes vias used for application purposes Figure 37. Layout Example (RGW Package) 24 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 10.3 Estimating Junction Temperature Using the thermal metrics JT and JB, as shown in the Thermal Information table, the junction temperature can be estimated with corresponding formulas (given in Equation 8). For backwards compatibility, an older JC,Top parameter is listed as well. YJT: TJ = TT + YJT * PD YJB: TJ = TB + YJB * PD (8) Where PD is the power dissipation shown by Equation 6, TT is the temperature at the center-top of the IC package, and TB is the PCB temperature measured 1 mm away from the IC package on the PCB surface (Figure 38). NOTE Both TT and TB can be measured on actual application boards using a thermo-gun (an infrared thermometer). For more information about measuring TT and TB, see the Using New Thermal Metrics application note, available for download at www.ti.com. TT on top of IC TB on PCB surface TB on PCB TT on top of IC 1mm 1mm (a) Example DRC (SON) Package Measurement (b) Example RGW (QFN) Package Measurement Figure 38. Measuring Points for TT and TB Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 25 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com Estimating Junction Temperature (continued) By looking at Figure 39, the new thermal metrics (JT and JB) have very little dependency on board size. That is, using JT or JB with Equation 8 is a good way to estimate TJ by simply measuring TT or TB, regardless of the application board size. 12 YJT and YJB (C/W) 10 YJB 8 DRC RGW 6 4 2 YJT 0 0 1 2 3 4 5 6 7 8 9 10 Board Copper Area (in2) Figure 39. JT and JB vs Board Size For a more detailed discussion of why TI does not recommend using JC(top) to determine thermal characteristics, see the Using New Thermal Metrics application report, available for download at www.ti.com. For further information, see the IC Package Thermal Metrics application report, also available on the TI website. 26 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 TPS748 www.ti.com SBVS074L - JANUARY 2007 - REVISED MARCH 2017 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support 11.1.1.1 Evaluation Modules An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TPS48. The TPS74801EVM-177 evaluation module (and related user's guide) can be requested at the Texas Instruments website through the product folders or purchased directly from the TI eStore. 11.1.1.2 Spice Models Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. A SPICE model for the TPS748 is available through the product folders under Tools & Software. 11.2 Documentation Support 11.2.1 Related Documentation For related documentation, see the following: * Using New Thermal Metrics * IC Package Thermal Metrics * Ultimate Regulation of with Fixed Output Versions of the TPS742xx, TPS743xx, and TPS744xx * Pros and Cons of Using a Feedforward Capacitor with a Low-Dropout Regulator * TPS74801EVM-177 Evaluation Module User Guide 11.3 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 11.4 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.5 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.6 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 27 TPS748 SBVS074L - JANUARY 2007 - REVISED MARCH 2017 www.ti.com 11.7 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 28 Submit Documentation Feedback Copyright (c) 2007-2017, Texas Instruments Incorporated Product Folder Links: TPS748 PACKAGE OPTION ADDENDUM www.ti.com 6-Mar-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS74801DRCR ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801DRCRG4 ACTIVE VSON DRC 10 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801DRCT ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801DRCTG4 ACTIVE VSON DRC 10 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 BTO TPS74801RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801RGWT ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 TPS74801RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 125 TPS 74801 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 6-Mar-2017 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF TPS74801 : * Automotive: TPS74801-Q1 NOTE: Qualified Version Definitions: * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS74801DRCR VSON DRC 10 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801DRCT VSON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 TPS74801RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 TPS74801RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jan-2018 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS74801DRCR VSON DRC 10 3000 367.0 367.0 35.0 TPS74801DRCT VSON DRC 10 250 210.0 185.0 35.0 TPS74801RGWR VQFN RGW 20 3000 367.0 367.0 35.0 TPS74801RGWT VQFN RGW 20 250 210.0 185.0 35.0 Pack Materials-Page 2 GENERIC PACKAGE VIEW DRC 10 VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. 4204102-3/M PACKAGE OUTLINE DRC0010J VSON - 1 mm max height SCALE 4.000 PLASTIC SMALL OUTLINE - NO LEAD 3.1 2.9 A B PIN 1 INDEX AREA 3.1 2.9 1.0 0.8 C SEATING PLANE 0.05 0.00 0.08 C 1.65 0.1 2X (0.5) EXPOSED THERMAL PAD (0.2) TYP 4X (0.25) 5 2X 2 6 11 SYMM 2.4 0.1 10 1 8X 0.5 PIN 1 ID (OPTIONAL) 10X SYMM 0.5 10X 0.3 0.30 0.18 0.1 0.05 C A B C 4218878/B 07/2018 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. www.ti.com EXAMPLE BOARD LAYOUT DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD (1.65) (0.5) 10X (0.6) 1 10 10X (0.24) 11 (2.4) SYMM (3.4) (0.95) 8X (0.5) 6 5 (R0.05) TYP ( 0.2) VIA TYP (0.25) (0.575) SYMM (2.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:20X 0.07 MAX ALL AROUND 0.07 MIN ALL AROUND EXPOSED METAL EXPOSED METAL SOLDER MASK OPENING METAL METAL UNDER SOLDER MASK NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK OPENING SOLDER MASK DEFINED SOLDER MASK DETAILS 4218878/B 07/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. www.ti.com EXAMPLE STENCIL DESIGN DRC0010J VSON - 1 mm max height PLASTIC SMALL OUTLINE - NO LEAD 2X (1.5) (0.5) SYMM EXPOSED METAL TYP 11 10X (0.6) 1 10 (1.53) 10X (0.24) 2X (1.06) SYMM (0.63) 8X (0.5) 6 5 (R0.05) TYP 4X (0.34) 4X (0.25) (2.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 11: 80% PRINTED SOLDER COVERAGE BY AREA SCALE:25X 4218878/B 07/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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