STD70N03L-1 - STMicroelectronics

June 2006 Rev 1 1/16

STD70N03L

STD70N03L-1

N-channel 30V - 0.0059Ω - 70A - DPAK / IPAK

STripFET™ III Power MOSFET

General features

■RDS(ON) * Qg industry’s benchmark

■Conduction losses reduced

■Switching losses reduced

■Low threshold device

Description

This product utilizes the latest advanced design

rules of ST’s proprietary STripFET™ technology.

This is suitable for the most demanding DC-DC

converter application where high efficiency is to

be achieved.

Applications

■Switching application

Internal schematic diagram

Type VDSS RDS(on) ID

STD70N03L 30V <0.0073Ω70A

STD70N03L-1 30V <0.0073Ω70A

DPAK IPAK

www.st.com

Order codes

Part number Marking Package Packaging

STD70N03L D70N03L DPAK Tape & reel

STD70N03L-1 D70N03L-1 IPAK Tube

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Contents

1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

5 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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1 Electrical ratings

Table 1. Absolute maximum ratings

Symbol Parameter Value Unit

VDS Drain-source voltage (VGS = 0) 30 V

VGS Gate-source voltage ± 20 V

ID Drain current (continuous) at TC = 25°C 70 A

IDDrain current (continuous) at TC = 100°C 50 A

IDM (1)

1. Pulse width limited by safe operating area

Drain current (pulsed) 280 A

PTOT Total dissipation at TC = 25°C 70 W

Derating factor 0.47 W/°C

EAS (2)

2. Starting Tj =25°C, Id = 30A, Vdd = 15V

Single pulse avalanche energy 300 mJ

Tstg

Operating junction temperature

Storage temperature -55 to 175 °C

Table 2. Thermal resistance

Symbol Parameter Value Unit

Rthj-case Thermal resistance junction-case Max 2.14 °C/W

Rthj-amb Thermal resistance junction-amb Max 100 °C/W

TlMaximum lead temperature for soldering purpose 275 °C

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2 Electrical characteristics

(TCASE=25°C unless otherwise specified)

Table 3. On/off states

Symbol Parameter Test condictions Min. Typ. Max. Unit

V(BR)DSS Drain-source

breakdown voltage ID = 250µA, VGS= 0 30 V

IDSS

Zero gate voltage drain

current (VGS = 0)

VDS = 20V,

VDS = 20V,Tc = 125°C

µA

IGSS

Gate body leakage

current(VDS = 0) VGS = ±20V ±100 nA

VGS(th) Gate threshold voltage VDS= VGS, ID = 250µA 1V

RDS(on) Static drain-source on

resistance

VGS= 10V, ID= 35A

VGS= 5V, ID= 35A

VGS= 10V, ID= 35A @Tj=125°C

VGS= 5V, ID= 35A @Tj=125°C

0.0059

0.007

0.0091

0.0108

0.0073

0.013

0.0113

0.0201

Ω

Table 4. Dynamic

Symbol Parameter Test condictions Min. Typ. Max. Unit

gfs (1)

1. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Forward

transconductance VDS =10V, ID = 15A 40 S

Ciss

Coss

Crss

Input capacitance

Output capacitance

Reverse transfer

capacitance

VDS =25V, f=1MHz, VGS=0

2200

380

Qgs

Qgd

Total gate charge

Gate-source charge

Gate-drain charge

VDD=15V, ID = 70A

VGS =5V

(see Figure 7)

15.7

8.3

3.4

21 nC

Qgls (2)

2. Gate charge for synchronous operation: see Appendix A: Power losses estimation

Third-quadrant gate

charge VDS <0V, VGS =10V 15 nC

RGGate input resistance f=1MHz Gate DC Bias =0 Test

signal level =20mV open drain 1.5 Ω

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Table 5. Switching times

Symbol Parameter Test condictions Min. Typ. Max. Unit

td(on)

td(off)

Turn-on delay time

Rise time

Turn-off delay time

Fall time

VDD=15V, ID=35A,

RG=4.7Ω, VGS=5V

(see Figure 13)

Table 6. Source drain diode

Symbol Parameter Test condictions Min Typ. Max Unit

ISD Source-drain current 70 A

ISDM(1)

1. Pulse width limited by safe operating area

Source-drain current (pulsed) 280 A

VSD (2)

2. Pulsed: pulse duration = 300µs, duty cycle 1.5%

Forward on voltage ISD=35A, VGS=0 1.3 V

trr

Qrr

IRRM

Reverse recovery time

Reverse recovery charge

Reverse recovery current

ISD = 70A,

di/dt=100A/µs,

VDD=20V, Tj=150°C

(see Figure 18)

3.2

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2.1 Electrical characteristics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance

Figure 3. Output characterisics Figure 4. Transfer characteristics

Figure 5. Transconductance Figure 6. Static drain-source on resistance

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Figure 7. Gate charge vs gate-source voltage Figure 8. Capacitance variations

Figure 9. Normalized gate threshold voltage

vs temperature

Figure 10. Normalized on resistance vs

temperature

Figure 11. Source-drain diode forward

characteristics

Figure 12. Normalized BVDSS vs temperature

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Test circuit STD70N03L - STD70N03L-1

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3 Test circuit

Figure 13. Switching times test circuit for

resistive load

Figure 14. Gate charge test circuit

Figure 15. Test circuit for inductive load

switching and diode recovery times

Figure 16. Unclamped inductive load test

circuit

Figure 17. Unclamped inductive waveform Figure 18. Switching time waveform

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Appendix A Power losses estimation

The power losses associated with the FETs in a synchronous buck converter can

be estimated using the equations shown in the table below. The formulas give a

good approximation, for the sake of performance comparison, of how different

pairs of devices affect the converter efficiency. However a very important

parameter, the wotking temperature, is not considered. The real device behavior is

really dependent on how the heat generated inside the devices is removed to allow

for a safer working junction temperature.

The low side (SW2) device requires:

●Ver y low RDS(on) to reduce conduction losses

●Small Qgls to reduce the gate charge losses

●Small Coss to reduce losses due to output capacitance

●Small Qrr to reduce losses on SW1 during its turn-on

●The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source

voltage to avoid the cross conduction phenomenon.

The high side (SW1) device requires:

●Small Rg and Lg to allow higher gate current peak and to limit the voltage

feedback on the gate

●Small Qg to have a faster commutation and to reduce gate charge losses

●Low RDS(on) to reduce the conduction losses

Figure 19. Buck converter

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Power losses estimation STD70N03L - STD70N03L-1

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High side switch (SW1) Low side swit c h (SW2)

Pconduction

Pswitching Zero voltage switching

Pdiode

Recovery Not applicable

Conduction Not applicable

Pgate(Qg)

PQoss

RDS on()IL

•δ•RDS on()IL

•1δ–()•

Vin Qgsth SW1()

Qgd SW1()

+()•fIL

----

••

in Qrr SW2()

•f•

VfSW2()

ILtdeadtime f•••

QgSW1()

Vgg

•f•Qgls SW2()

Vgg

•f•

Vin Qoss SW1()

•f•

--------------------------------------------------

Vin Qoss SW2()

•f•

--------------------------------------------------

Parameter Meaning

d Duty-cycle

Qgsth Post threshold gate charge

Qgls Third quadrant gate charge

Pconduction On state losses

Pswitching On-off transition losses

Pdiode Conduction and reverse recovery diode losses

Pgate Gate driver losses

PQoss Output capacitance losses

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4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a Lead-free second level interconnect . The category of

second level interconnect is marked on the package and on the inner box label, in

compliance with JEDEC Standard JESD97. The maximum ratings related to soldering

conditions are also marked on the inner box label. ECOPACK is an ST trademark.

ECOPACK specifications are available at: www.st.com

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Package mechanical data STD70N03L - STD70N03L-1

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DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.2 2.4 0.086 0.094

A1 0.9 1.1 0.035 0.043

A3 0.7 1.3 0.027 0.051

B 0.64 0.9 0.025 0.031

B2 5.2 5.4 0.204 0.212

B3 0.85 0.033

B5 0.3 0.012

B6 0.95 0.037

C 0.45 0.6 0.017 0.023

C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

E 6.4 6.6 0.252 0.260

G 4.4 4.6 0.173 0.181

H 15.9 16.3 0.626 0.641

L 9 9.4 0.354 0.370

L1 0.8 1.2 0.031 0.047

L2 0.8 1 0.031 0.039

1 3

= =

TO-251 (IPAK) MECHANICAL DATA

0068771-E

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DIM.

mm. inch

MIN. TYP MAX. MIN. TYP. MAX.

A 2.2 2.4 0.086 0.094

A1 0.9 1.1 0.035 0.043

A2 0.03 0.23 0.001 0.009

B 0.64 0.9 0.025 0.035

b4 5.2 5.4 0.204 0.212

C 0.45 0.6 0.017 0.023

C2 0.48 0.6 0.019 0.023

D 6 6.2 0.236 0.244

D1 5.1 0.200

E 6.4 6.6 0.252 0.260

E1 4.7 0.185

e 2.28 0.090

e1 4.4 4.6 0.173 0.181

H 9.35 10.1 0.368 0.397

L1 0.039

(L1) 2.8 0.110

L2 0.8 0.031

L4 0.6 1 0.023 0.039

R 0.2 0.008

V2 0° 8° 0° 8°

DPAK MECHANICAL DATA

0068772-F

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5 Packaging mechanical data

TAPE AND REEL SHIPMENT

DPAK FOOTPRINT

DIM. mm inch

MIN. MAX. MIN. MAX.

A 330 12.992

B1.5 0.059

C 12.8 13.2 0.504 0.520

D20.2 0.795

G 16.4 18.4 0.645 0.724

N50 1.968

T 22.4 0.881

BASE QTY BULK QTY

2500 2500

REEL MECHANICAL DATA

DIM. mm inch

MIN. MAX. MIN. MAX.

A0 6.8 7 0.267 0.275

B0 10.4 10.6 0.409 0.417

B1 12.1 0.476

D1.5 1.6 0.059 0.063

D1 1.5 0.059

E1.65 1.85 0.065 0.073

F 7.4 7.6 0.291 0.299

K0 2.55 2.75 0.100 0.108

P0 3.9 4.1 0.153 0.161

P1 7.9 8.1 0.311 0.319

P2 1.9 2.1 0.075 0.082

R40 1.574

W 15.7 16.3 0.618 0.641

TAPE MECHANICAL DATA

All dimensions are in millimeters

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6 Revision history

Table 7. Revision history

Date Revision Changes

29-Jun-2006 1First Release

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