74HC/HCT175 MSI QUAD D-TYPE FLIP-FLOP WITH RESET; POSITIVE-EDGE TRIGGER FEATURES TYPICAL Four edge-triggered D flip-flops SYMBOL | PARAMETER CONDITIONS UNIT @ Output capability: standard He HCT @ Icc category: MSI propagation delay tPHL CP to Qy, Gy, 17, | 16 | ns GENERAL DESCRIPTION MR to On, CL = 15 pF 15 | 19 | ms . : VeczoVv ! The 74HC/HCT175 are high-speed propagation delay Si-gate CMOS devices and are pin tPLH CP to Qn, On 7 16 | ns compatible with low power Schottky MR to Gy, 15 16 ns TTL (LSTTL). They are specified in frnax maximum clock frequency 83 54 MHz compliance with JEDEC standard no. 7A. The 74HC/HCT175 have four edge- C\ input capacitance 3.6 | 3.5 | pF triggered, D-type flip-fiops with eas wee : = power dissipation ene D inputs and both Q and Q Cpp capacitance per flip-flop notes 1 and 2 32 34 pF The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HiGH clock transition, is transferred to the corresponding output (Q,,) of the flip-flop. All Qy outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is usefui for applications where both the true and complement outputs are required and the clock and master reset are common to all storage elements, GND = 0 V: Tamb = 25 C; ty = te = 6 ns Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in uW): Pp = Cppx Vcc? x fj +2 (CL x Vcc? x fo) where: fj = input frequency in MHz CL = output load capacitance in pF fo = output frequency in MHz Vcc = supply voltage in V = (CL x Vcc? x fg) = sum of outputs 2. For HC the condition is Vj = GND to Vcc For HCT the condition is Vi = GND to Vec 1.5 V PACKAGE OUTLINES 16-lead DIL; plastic (SOT38Z). 16-lead mini-pack; plastic (S016; SOT109A). PIN DESCRIPTION PIN NO, SYMBOL NAME AND FUNCTION 1 MR master reset input (active LOW) 2,7, 10, 15 Qg to Og flip-flop outputs 3, 6,11, 14 Og to G3 complementary flip-flop outputs 4,5,12, 13 Dg to D3 data inputs 8 GND ground (0 V) 9 cP clock input (LOW-to-H1GH, edge-triggered} 16 Vec positive supply voltage U 2 cl wa Lo | 6] Yee 9 inte Po [2 jis} 3 D F agt2 Cc 44 = 2 [3] [14] 95 Sos +h w= a,-7 PS Po fa] Fa] 3 mols 175 1 5 |? aes [2] 2 alo, 2} | hs = = a, 3, [e] ra] Zi ole 2 |_1 4] fio] G2 139 ash a ~ Patt MR 15 GND cs [2] cP t 7293242 Bo hoa 7Z93241 7293243 Fig. 1 Pin configuration, Fig. 2 Logic symbol. Fig. 3 IEC logic symbol. Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. December 1990 74HC/HCT175 MSI 4 5 12 13 Dg F Do D3 Ltn abe D ae ip ak Jo oa jor FF ce ee Ff rer FF Ro | | aot | rol ] Ape a{ce] > | itm | i | Qo] {eg ay) {ay Ga] la, G3} Ja, 7293248 a] 2 el |7 ut Tio 40 Tas Fig. 4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES am | cp | op a a H = HIGH voltage ievel n h n h = HIGH voltage level one set-up time prior to the reset {clear} L x x L H L= LOW volte evel transition figs 1 = LOW voltage Jevel one set-up time prior to the l oad 1 Het yh Tw {et LOW-t0-HIGH CP transition toad 0 H t | L 4 x = LOwito HIGH CP transition Dg Dy D2 Ds Do Qa o a D Q D a cr FF ce FF cp FF ce Ff aot | | ao | aT | Rp o cp , t . | MA +D-feo y 72932465 Gy Oy a, a ao, o3 a3 Fig. 5 Logic diagram. 382 April 1985 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. Quad D-type flip-flop with reset; positive-edge trigger 74HC/HCT175 MSI DC CHARACTERISTICS FOR 74HC For the DC characteristics see chapter -HCMOS family characteristics, section Family specifications. Output capability: standard tec category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V;t, = t= 6 ns: Cy = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT | Vog | WAVEFORMS +25 ~40 to +85 | 40to +125 Vv min. | typ. | max. | min.| max. | min. | max. 55 | 175 220 265 2.0 tPHL/ _|_ Propagation delay 20 | 35 44 53 | ns 45 | Fig.6 PLH CP to Qn, On 16 | 30 37 45 6.0 . 50 | 150 190 225 2.0 tpHL/ _|_ Propagation delay 18 | 30 38 45 [ns | 45 | Figs tPLH MR to Op, Op 14 | 26 33 38 6.0 / 19 | 75 95 110 2.0 tTHL output transition time 7 15 19 22 ns 4.5 Fig. 6 tTLH 6 13 16 19 6.0 clock pulse width * a sO ve a Fie 6 ns . ig. tw HIGH or LOW 146 7 50 60 g0 | 19 100 120 2.0 tw master reset pulse width 16 7 20 24 ns 45 Fig. 8 Low 14.16 +7 20 6.0 removal time 5 33 5 5 2.0 - 45 | Fig.8 trem MR to CP 2 ar 2 " 60 cup time so | 3 100 120 2.0 set-up ti . t 16} 4 20 24 ns 4.5 | Fig.7 u Dp to CP 14/4 17 20 6.0 25 | 2 30 40 2.0 t hold time 5 0 6 8 ns 4.5 Fig. 7 h cP toD, 4 0 5 7 6.0 . 6.0 | 25 48 4.0 2.0 f maximum clock pulse 30 | 75 24 20 MHz | 4.5 | Fig.6 max frequency 35 | 89 28 24 6.0 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. December 1990 383 74HC/HCT175 MSI DC CHARACTERISTICS FOR 74HCT For the DC characteristics see chapter 'HCMOS family characteristics, section Family specifications. Output capability: standard lec category: MSI Note to HCT types The value of additional quiescent supply current (Alcc} for a unit load of 7 is given in the family specifications. To determine Alcc per input, multiply this value by the unit load coefficient shown in the table below. UNIT LOAD INPUT | COEFFICIENT MR 1.00 cP 0.60 Dn 0.40 AC CHARACTERISTICS FOR 74HCT GND = OV; t- = t= 6 ns; C, = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL} PARAMETER UNIT | Voc} WAVEFORMS +25 40to +85 | 40to +125 Vv min.| typ. | max.) min. | max. | min. | max. tPHL/ propagation delay 19 | 33 41 50 | ns 45 | Fig 6 tpLH CP to Q,, om propagation delay 22 48 57 | ns | 45 | Fig.8 PHL MR to O, 38 9 propagation delay 53 ins | 45 | Fig. 8 tpLH MIR to Op 19 | 35 44 g tTHL! output transition time 7 15 19 22 ns 4.5 Fig. 6 TTLH clock pulse width 12 30 ns 45 Fig. 6 tw HIGH or LOW 20 25 9 master reset pulse width 25 30 ns 45 Fig, 8 tw LOW 20/11 removal time - 5 ns | 4.5 | Fig. 8 trem MR to CP 6 10 5 g set-up time 20 24 ns 45 Fig. 7 tsu Dp to CP 16 5 hold time 5 ns 4.5 | Fig.7 th CP to Dp 5 | 0 5 q maximum clock pulse 49 20 17 MHz | 4.5 | Fig.6 fmax frequency 25 g 384 January 1986 Printed From CAPS XPert Version 1.2P This Material Copyrighted By Philips Semiconductors. Quad D-type flip-flop with reset; positive-edge trigger 74HC/HCT175 MSI AC WAVEFORMS cP INPUT j Vig!) ! \ e TpryL | be to H oy Q,, OUTPUT Vy hh O, OUTPUT 7293246. Fig, 6 Waveforms showing the clock (CP) to outputs (O,,, G,} propagation delays, the clock pulse width, output transition times and the maximum clock puise frequency. CP INPUT D,, INPUT Fig. 7 Waveforms showing the data set-up and hold times for the data input (Dp). Note to Fig. 7 The shaded areas indicate when the input is permitted to change for predictable output performance. Q,, OUTPUT fee Vat) G, OUTPUT TZ93247 MR INPUT \ CP INPUT Vy it [* tPHL Q, OUTPUT Vu? = TPL @, OUTPUT vail) 7293248 Fig. 8 Waveforms showing the master reset (MR) pulse width, the master reset to outputs (Qn, Gp) propagation delays and the master reset to clock (CP} removal time. Note to AC waveforms (1) HC: Vy = 50%; V, = GND to Vcc. HCT: Vpxq = 1.3 V; Vy = GND to 3V. Printed From CAPS XPert Version 1.2P March 1988 This Material Copyrighted By Philips Semiconductors. 385