1
FEATURES
DESCRIPTION
APPLICATIONS
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
COUT
CIN
CSS
VBIAS
CBIAS
VOUT
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
TPS74801
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..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
1.5A Low-Dropout Linear Regulator with Programmable Soft-Start
2
•V
OUT
Range: 0.8V to 3.6V
The TPS74801 low-dropout (LDO) linear regulator•Ultralow V
IN
Range: 0.8V to 5.5V
provides an easy-to-use robust power management•V
BIAS
Range 2.7V to 5.5V
solution for a wide variety of applications.•Low Dropout: 60mV typ at 1.5A, V
BIAS
= 5V
User-programmable soft-start minimizes stress on theinput power source by reducing capacitive inrush•Power Good (PG) Output Allows Supply
current on start-up. The soft-start is monotonic andMonitoring or Provides a Sequencing Signal
well-suited for powering many different types offor Other Supplies
processors and ASICs. The enable input and power•2% Accuracy Over Line/Load/Temperature
good output allow easy sequencing with external•Programmable Soft-Start Provides Linear
regulators. This complete flexibility permits the user toconfigure a solution that meets the sequencingVoltage Startup
requirements of FPGAs, DSPs, and other•V
BIAS
Permits Low V
IN
Operation with Good
applications with special start-up requirements.Transient Response
A precision reference and error amplifier deliver 2%•Stable with Any Output Capacitor ≥2.2 µF
accuracy over load, line, temperature, and process.•Available in a Small 3mm x 3mm x 1mm
The device is stable with any type of capacitorSON-10 and 5 x 5 QFN-20 Packages
greater than or equal to 2.2 µF, and is fully specifiedfrom – 40 ° C to +125 ° C. The TPS74801 is offered in asmall 3mm × 3mm SON-10 package, yielding a highlycompact, total solution size. It is also available in a 5•FPGA Applications
x 5 QFN-20 for compatibility with the TPS74401 .•DSP Core and I/O Voltages•Post-Regulation Applications•Applications with Special Start-Up Time orSequencing Requirements•Hot-Swap and Inrush Controls
Figure 1. Typical Application Circuit (Adjustable)
Figure 2. Turn-On Response
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2007 – 2009, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
DISSIPATION RATINGS
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
PRODUCT V
OUT
(2)
TPS748 xxyyyz XX is nominal output voltage (for example, 12 = 1.2V, 15 = 1.5V, 01 = Adjustable).
(3)
YYY is package designator.Zis package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIwebsite at www.ti.com .(2) Fixed output voltages from 0.8V to 3.3V are available; minimum order quantities may apply. Contact factory for details and availability.(3) For fixed 0.8V operation, tie FB to OUT.
At T
J
= – 40 ° C to +125 ° C, unless otherwise noted. All voltages are with respect to GND.
TPS74801 UNIT
V
IN
, V
BIAS
Input voltage range – 0.3 to +6 VV
EN
Enable voltage range – 0.3 to +6 VV
PG
Power good voltage range – 0.3 to +6 VI
PG
PG sink current 0 to +1.5 mAV
SS
Soft-start voltage range – 0.3 to +6 VV
FB
Feedback voltage range – 0.3 to +6 VV
OUT
Output voltage range – 0.3 to V
IN
+ 0.3 VI
OUT
Maximum output current Internally limitedOutput short-circuit duration IndefiniteP
DISS
Continuous total power dissipation See Dissipation Ratings TableT
J
Operating junction temperature range – 40 to +125 ° CT
STG
Storage junction temperature range – 55 to +150 ° C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly and functional operation of the device at these conditions is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.
T
A
< +25 ° C DERATING FACTORPACKAGE θ
JA
θ
JC
POWER RATING ABOVE T
A
= +25 ° C
DRC (SON) High-K
(1) (2)
52 ° C/W 4 ° C/W 1.92 W 19.2mW/ ° CRGW (QFN)
(3)
36.5 ° C/W 4 ° C/W 2.74W 27.4mW/ ° C
(1) The JEDEC High-K (2s2p) board design used to derive this data was a 3 inch x 3 inch multilayer board with 1-ounce internal power andground planes and 2-ounce copper traces on the top and bottom of the board(2) See the Layout Recommendations and Power Dissipation section for additional thermal information.(3) See Figure 34 for PCB layout description.
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ELECTRICAL CHARACTERISTICS
TPS74801
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..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
At V
EN
= 1.1V, V
IN
= V
OUT
+ 0.3V, C
BIAS
= 0.1 µF, C
IN
= C
OUT
= 10 µF, C
NR
= 1nF, I
OUT
= 50mA, V
BIAS
= 5.0V, and T
J
= – 40 ° C to+125 ° C, unless otherwise noted. Typical values are at T
J
= +25 ° C.
TPS74801
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
IN
Input voltage range V
OUT
+ V
DO
5.5 VV
BIAS
Bias pin voltage range 2.7 5.5 VV
REF
Internal reference (Adj.) T
J
= +25 ° C 0.796 0.8 0.804 VOutput voltage range V
IN
= 5V, I
OUT
= 1.5A V
REF
3.6 VV
OUT
2.97V ≤V
BIAS
≤5.5V,Accuracy
(1)
– 2 ± 0.5 2 %50mA ≤I
OUT
≤1.5AV
OUT
/V
IN
Line regulation V
OUT (NOM)
+ 0.3 ≤V
IN
≤5.5V 0.03 %/VV
OUT
/I
OUT
Load regulation 50mA ≤I
OUT
≤1.5A 0.09 %/AI
OUT
= 1.5A, 60 165 mVV
IN
dropout voltage
(2)
V
BIAS
– V
OUT (NOM)
≥3.25V
(3)V
DO
V
BIAS
dropout voltage
(2)
I
OUT
= 1.5A, V
IN
= V
BIAS
1.31 1.6 VI
CL
Current limit V
OUT
= 80% × V
OUT (NOM)
2.0 5.5 AI
BIAS
Bias pin current 1 2 mAShutdown supply currentI
SHDN
V
EN
≤0.4V 1 50 µA(I
GND
)I
FB
Feedback pin current – 1 0.150 1 µA1kHz, I
OUT
= 1.5A,
60V
IN
= 1.8V, V
OUT
= 1.5VPower-supply rejection
dB(V
IN
to V
OUT
)
300kHz, I
OUT
= 1.5A,
30V
IN
= 1.8V, V
OUT
= 1.5VPSRR
1kHz, I
OUT
= 1.5A,
50V
IN
= 1.8V, V
OUT
= 1.5VPower-supply rejection
dB(V
BIAS
to V
OUT
)
300kHz, I
OUT
= 1.5A,
30V
IN
= 1.8V, V
OUT
= 1.5V100Hz to 100kHz,Noise Output noise voltage 25 × V
OUT
µV
RMSI
OUT
= 1.5A, C
SS
= 0.001 µFt
STR
Minimum startup time R
LOAD
for I
OUT
= 1.0A, C
SS
= open 200 µsI
SS
Soft-start charging current V
SS
= 0.4V 440 nAV
EN, HI
Enable input high level 1.1 5.5 VV
EN, LO
Enable input low level 0 0.4 VV
EN, HYS
Enable pin hysteresis 50 mVV
EN, DG
Enable pin deglitch time 20 µsI
EN
Enable pin current V
EN
= 5V 0.1 1 µAV
IT
PG trip threshold V
OUT
decreasing 85 90 94 %V
OUT
V
HYS
PG trip hysteresis 3 %V
OUT
V
PG, LO
PG output low voltage I
PG
= 1mA (sinking), V
OUT
< V
IT
0.3 VI
PG, LKG
PG leakage current V
PG
= 5.25V, V
OUT
> V
IT
0.1 1 µAOperating junctionT
J
– 40 +125 ° Ctemperature
Shutdown, temperature increasing +165Thermal shutdownT
SD
° Ctemperature
Reset, temperature decreasing +140
(1) Adjustable devices tested at 0.8V; resistor tolerance is not taken into account.(2) Dropout is defined as the voltage from V
IN
to V
OUT
when V
OUT
is 3% below nominal.(3) 3.25V is a test condition of this device and can be adjusted by referring to Figure 8 .
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BLOCK DIAGRAM
Thermal
Limit
Soft-Start
Discharge
OUT VOUT
FB
PG
IN
BIAS
SS
EN Hysteresis
andDeglitch
Current
Limit
UVLO
0.44 Am
0.8V
Reference
0.9 ´VREF
GND
CSS
R1
R2
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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Table 1. Standard 1% Resistor Values for Programming the Output Voltage
(1)
R
1
(k Ω) R
2
(k Ω) V
OUT
(V)
Short Open 0.80.619 4.99 0.91.13 4.53 1.01.37 4.42 1.051.87 4.99 1.12.49 4.99 1.24.12 4.75 1.53.57 2.87 1.83.57 1.69 2.53.57 1.15 3.3
(1) V
OUT
= 0.8 × (1 + R
1
/R
2
).
Table 2. Standard Capacitor Values for Programming the Soft-Start Time
(1)
C
SS
SOFT-START TIME
Open 0.1ms270pF 0.5ms560pF 1ms2.7nF 5ms5.6nF 10ms0.01 µF 18ms
(1) t
SS
(s) = 0.8 × C
SS
(F)/4.4 × 10
– 7
.
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DEVICE INFORMATION
OUT
OUT
FB
SS
GND
10
9
8
7
6
IN
IN
PG
BIAS
EN
1
2
3
4
5
Thermal
Pad
IN
IN
IN
PG
BIAS
OUT
OUT
OUT
NC
FB
TPS74801
IN
EN 11
GND 12
NC 13
NC 14
SS 15
6
7
8
9
10
20
19
18
17
16
5
NC4
NC3
NC2
OUT1
GND
PIN DESCRIPTIONS
TPS74801
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..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
DRC PACKAGE RGW PACKAGE3mm x 3mm SON 5 x 5 QFN(TOP VIEW) (TOP VIEW)
NAME DRC (SON) RGW (QFN) DESCRIPTION
IN 1, 2 5-8 Input to the device.Enable pin. Driving this pin high enables the regulator. Driving this pin low putsEN 5 11
the regulator into shutdown mode. This pin must not be left unconnected.SS 7 15 Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time.If this pin is left unconnected, the regulator output soft-start ramp time is typically200 µs.BIAS 4 10 Bias input voltage for error amplifier, reference, and internal control circuits.Power Good pin. An open-drain, active-high output that indicates the status ofV
OUT
. When V
OUT
exceeds the PG trip threshold, the PG pin goes into ahigh-impedance state. When V
OUT
is below this threshold the pin is driven to aPG 3 9 low-impedance state. A pull-up resistor from 10k Ωto 1M Ωshould be connectedfrom this pin to a supply of up to 5.5V. The supply can be higher than the inputvoltage. Alternatively, the PG pin can be left unconnected if output monitoring isnot necessary.
Feedback pin. The feedback connection to the center tap of an external resistorFB 8 16
divider network that sets the output voltage. This pin must not be left floating.OUT 9, 10 1, 18-20 Regulated output voltage. A small capacitor (total typical capacitance ≥2.2 µF,ceramic) is needed from this pin to ground to assure stability.NC N/A 2-4, 13, 14, 17 No connection. This pin can be left floating or connected to GND to allow betterthermal contact to the top-side plane.GND 6 12 GroundThermal Pad — Should be soldered to the ground plane for increased thermal performance.
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TYPICAL CHARACTERISTICS
0.20
0.15
0.10
0.05
0
-0.05
-0.01
-0.15
-0.20
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
ChangeinV (%)
OUT
V V-
IN OUT (V)
5.0
+125 C°
+25 C°
- °40 C
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.5 1.0 1.5 2.0 2.5 3.0 3.5
ChangeinV (%)
OUT
V V-
BIAS OUT (V)
4.0
+125 C°+25 C°
- °40 C
1.2
1.0
0.8
0.6
0.4
0.2
0
010 20 30 40
ChangeinV (%)
OUT
I (mA)
OUT
50
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
0.05 0.5 1.0
ChangeinV (%)
OUT
I (A)
OUT
1.5
+125 C°
+25 C°- °40 C
100
90
80
70
60
50
40
30
20
10
0
00.5 1.0
V (V V )(mV)-
DO IN OUT
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
200
180
160
140
120
100
80
60
40
20
0
1.0 1.5 2.0 2.5 3.0 3.5 4.0
VDO IN
(V -VOUT)(mV)
VBIAS -VOUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =1.5A
OUT
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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At T
J
= +25 ° C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
V
IN
LINE REGULATION V
BIAS
LINE REGULATION
Figure 3. Figure 4.
LOAD REGULATION LOAD REGULATION
Figure 5. Figure 6.
V
IN
DROPOUT VOLTAGE vs V
IN
DROPOUT VOLTAGE vsI
OUT
AND TEMPERATURE (T
J
) (V
BIAS
– V
OUT
) AND TEMPERATURE (T
J
)
Figure 7. Figure 8.
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200
180
160
140
120
100
80
60
40
20
0
01.51.00.5 2.0 2.5 3.0 3.5 4.0
V (mV)
DO IN OUT
(V V )
-
V V-
BIAS OUT (V)
4.5
+125 C°
+25 C°
- °40 C
I =0.5A
OUT
2200
2000
1800
1600
1400
1200
1000
800
600
00.5 1.0
V (V -
DO BIAS V )(mV)
OUT
I (A)
OUT
1.5
+125 C°
+25 C°
- °40 C
90
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
V =5V
BIAS
C =1nF
SS
I =0.5A
OUT
I =0.1A
OUT I =1.5A
OUT
80
90
80
70
60
50
40
30
20
10
0
10 100 1k 10k 100k 1M
Power-SupplyRejectionRatio(dB)
Frequency(Hz)
10M
V =1.8V
IN
V =1.2V
OUT
C =1nF
SS
I =100mA
OUT
I =1.5A
OUT
90
80
70
60
50
40
30
20
10
0
00.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Power-SupplyRejectionRatio(dB)
V V-
IN OUT (V)
2.25
1kHz
10kHz
100kHz
500kHz
VOUT =1.2V
IOUT =1.5A
CSS =1nF
1
0.1
0.01
100 1k 10k
OutputSpectralNoiseDensity(mV/Ö)
Hz
Frequency(Hz)
100k
C =1nF
SS
C =0nF
SS
C =10nF
SS
I =100mA
OUT
V =1.2V
OUT
TPS74801
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..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
TYPICAL CHARACTERISTICS (continued)At T
J
= +25 ° C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
V
IN
DROPOUT VOLTAGE vs V
BIAS
DROPOUT VOLTAGE vs(V
BIAS
– V
OUT
) AND TEMPERATURE (T
J
) I
OUT
AND TEMPERATURE (T
J
)
Figure 9. Figure 10.
V
BIAS
PSRR vs FREQUENCY V
IN
PSRR vs FREQUENCY
Figure 11. Figure 12.
V
IN
PSRR vs (V
IN
– V
OUT
) NOISE SPECTRAL DENSITY
Figure 13. Figure 14.
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2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
00.2 0.4 0.6 0.8 1.0 1.2 1.4
I(mA)
BIAS
I (A)
OUT
1.6
+125 C°
+25 C°
- °40 C
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
I (mA)
BIAS
V (V)
BIAS
5.5
+125 C°
+25 C°
- °40 C
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
V Low-LevelPGVoltage(V)
OL
02 4 6 8 10 12
PGCurrent(mA)
4.0
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
CurrentLimit(A)
V V-
BIAS OUT (V)
5.0
+125 C°
+25 C°
- °40 C
V =0.8V
OUT
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
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TYPICAL CHARACTERISTICS (continued)At T
J
= +25 ° C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 50mA, V
EN
= V
IN
, C
IN
= 1 µF, C
BIAS
= 4.7 µF, and C
OUT
= 10 µF,unless otherwise noted.
BIAS PIN CURRENT vs BIAS PIN CURRENT vsI
OUT
AND TEMPERATURE (T
J
) V
BIAS
AND TEMPERATURE (T
J
)
Figure 15. Figure 16.
SOFT-START CHARGING CURRENT (I
SS
) vsTEMPERATURE (T
J
) LOW-LEVEL PG VOLTAGE vs CURRENT
Figure 17. Figure 18.
CURRENT LIMIT vs (V
BIAS
– V
OUT
)
Figure 19.
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TYPICAL CHARACTERISTICS
100mV/div
100mV/div
1V/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
5.0V
1V/ sm
3.3V
C =1nF
SS
100mV/div
1V/div
Time(50 s/div)m
C =10 F(Ceramic)
OUT m
3.8V
1V/ sm
1.8V
C =1nF
SS
100mV/div
100mV/div
1A/div
100mV/div
Time(50 s/div)m
C =2.2 F(Ceramic)
OUT m
C =10 F(Ceramic)
OUT m
1A/ sm
50mA
C =470 F(OSCON)OUT m
C =1nF
SS
1.5A
0.5V/div VOUT
VEN
1V/div
Time(1ms/div)
CSS =2.2nF
CSS =1nF
CSS =0nF
1.2V
0V
1V/div
Time(20ms/div)
V (500mV/div)
PG
VOUT
V =V =V
IN BIAS EN
TPS74801
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..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
At T
J
= +25 ° C, V
IN
= V
OUT(TYP)
+ 0.3V, V
BIAS
= 5V, I
OUT
= 1A, V
EN
= V
IN
= 1.8V, V
OUT
= 1.5V, C
IN
= 1 µF, C
BIAS
= 4.7 µF, andC
OUT
= 10 µF, unless otherwise noted.
V
BIAS
LINE TRANSIENT V
IN
LINE TRANSIENT
Figure 20. Figure 21.
OUTPUT LOAD TRANSIENT RESPONSE TURN-ON RESPONSE
Figure 22. Figure 23.
POWER-UP/POWER-DOWN
Figure 24.
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APPLICATION INFORMATION
INPUT, OUTPUT, AND BIAS CAPACITOR
TRANSIENT RESPONSE
VOUT
COUT
10 Fm
TPS74801
GND
EN
FB
IN PG
BIAS
SS
OUT
VIN
R1
R2
R3
CIN
1 Fm
CSS
VBIAS
CBIAS
1 Fm
V =0.8
OUT ´1+ R1
R2
)(
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
The TPS74801 belongs to a family of low dropout
REQUIREMENTSregulators that feature soft-start capability. Theseregulators use a low current bias input to power all The device is designed to be stable for all availableinternal control circuitry, allowing the NMOS pass types and values of output capacitors ≥2.2 µF. Thetransistor to regulate very low input and output device is also stable with multiple capacitors involtages. parallel, which can be of any type or value.
The use of an NMOS-pass FET offers several critical The capacitance required on the IN and BIAS pinsadvantages for many applications. Unlike a PMOS strongly depends on the input supply sourcetopology device, the output capacitor has little effect impedance. To counteract any inductance in theon loop stability. This architecture allows the input, the minimum recommended capacitor for V
INTPS74801 to be stable with any capacitor type of and V
BIAS
is 1 µF. If V
IN
and V
BIAS
are connected tovalue 2.2 µF or greater. Transient response is also the same supply, the recommended minimumsuperior to PMOS topologies, particularly for low V
IN
capacitor for V
BIAS
is 4.7 µF. Good quality, low ESRapplications. capacitors should be used on the input; ceramic X5Rand X7R capacitors are preferred. These capacitorsThe TPS74801 features a programmable
should be placed as close the pins as possible forvoltage-controlled soft-start circuit that provides a
optimum performance.smooth, monotonic start-up and limits startup inrushcurrents that may be caused by large capacitiveloads. A power good (PG) output is available to allowsupply monitoring and sequencing of other supplies.
The TPS74801 was designed to have excellentAn enable (EN) pin with hysteresis and deglitch
transient response for most applications with a smallallows slow-ramping signals to be used for
amount of output capacitance. In some cases, thesequencing the device. The low V
IN
and V
OUT
transient response may be limited by the transientcapability allows for inexpensive, easy-to-design, and
response of the input supply. This limitation isefficient linear regulation between the multiple supply
especially true in applications where the differencevoltages often present in processor-intensive
between the input and output is less than 300mV. Insystems.
this case, adding additional input capacitanceimproves the transient response much more than justFigure 25 illustrates the typical application circuit for
adding additional output capacitance would do. Withthe TPS74801 adjustable output device.
a solid input supply, adding additional outputcapacitance reduces undershoot and overshootduring a transient event; refer to Figure 22 in theTypical Characteristics section. Because theTPS74801 is stable with output capacitors as low as2.2 µF, many applications may then need very littlecapacitance at the LDO output. For theseapplications, local bypass capacitance for thepowered device may be sufficient to meet thetransient requirements of the application. This designreduces the total solution cost by avoiding the needto use expensive, high-value capacitors at the LDOoutput.Figure 25. Typical Application Circuit for theTPS74801 (Adjustable)
R
1
and R
2
can be calculated for any output voltageusing the formula shown in Figure 25 . Refer toTable 1 for sample resistor values of common outputvoltages. In order to achieve the maximum accuracyspecifications, R
2
should be ≤4.99k Ω.
10 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
DROPOUT VOLTAGE
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN
VIN
V =3.3V 5%
BIAS ±
V =3.3V 5V
V =1.5V
I =1.5A
Efficiency=45%
IN
OUT
OUT
±
COUT
PROGRAMMABLE SOFT-START
Reference
SimplifiedBlock Diagram
VOUT
OUT
BIAS
FB
IN V =5V 5%
BIAS ±
V =1.8V
V =1.5V
I =1.5A
Efficiency=83%
IN
OUT
OUT
COUT
t =
SS
(V C )´
REF SS
ISS
(1)
t =
SSCL
(V C )´
OUT(NOM) OUT
ICL(MIN)
(2)
TPS74801
www.ti.com
..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
The TPS74801 offers very low dropout performance,making it well-suited for high-current, low V
IN
/lowV
OUT
applications. The low dropout of the TPS74801allows the device to be used in place of a dc/dcconverter and still achieve good efficiency. Thisprovides designers with the power architecture fortheir application to achieve the smallest, simplest,and lowest cost solution.
There are two different specifications for dropoutvoltage with the TPS74801. The first specification(shown in Figure 26 ) is referred to as V
IN
Dropout andis used when an external bias voltage is applied toachieve low dropout. This specification assumes thatV
BIAS
is at least 3.25V
(1)
above V
OUT
, which is the
Figure 27. Typical Application of the TPS74801case for V
BIAS
when powered by a 5.0V rail with 5%
Without an Auxiliary Bias Railtolerance and with V
OUT
= 1.5V. If V
BIAS
is higher thanV
OUT
+3.25V
(1)
, V
IN
dropout is less than specified.
The TPS74801 features a programmable, monotonic,voltage-controlled soft-start that is set with anexternal capacitor (C
SS
). This feature is important formany applications because it eliminates power-upinitialization problems when powering FPGAs, DSPs,or other processors. The controlled voltage ramp ofthe output also reduces peak inrush current duringstart-up, minimizing start-up transient events to theinput power bus.
To achieve a linear and monotonic soft-start, theTPS74801 error amplifier tracks the voltage ramp ofthe external soft-start capacitor until the voltageexceeds the internal reference. The soft-start rampFigure 26. Typical Application of the TPS74801
time depends on the soft-start charging current (I
SS
),Using an Auxiliary Bias Rail
soft-start capacitance (C
SS
), and the internalreference voltage (V
REF
), and can be calculated usingThe second specification (shown in Figure 27 ) is
Equation 1 :referred to as V
BIAS
Dropout and applies toapplications where IN and BIAS are tied together.This option allows the device to be used inapplications where an auxiliary bias voltage is not
If large output capacitors are used, the device currentavailable or low dropout is not required. Dropout is
limit (I
CL
) and the output capacitor may set thelimited by BIAS in these applications because V
BIAS
start-up time. In this case, the start-up time is givenprovides the gate drive to the pass FET; therefore,
by Equation 2 :V
BIAS
must be 1.6V above V
OUT
. Because of thisusage, IN and BIAS tied together easily consumehuge power. Pay attention not to exceed the powerrating of the IC package.
where:
V
OUT(NOM)
is the nominal output voltage,C
OUT
is the output capacitance, andI
CL(MIN)
is the minimum current limit for the device.
In applications where monotonic startup is required,the soft-start time given by Equation 1 should be setgreater than Equation 2 .(1) 3.25V is a test condition of this device and can be adjusted byreferring to Figure 8 .
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): TPS74801
OUTPUT NOISE
SEQUENCING REQUIREMENTS
V ( V )=25m
N RMS xV (V)
OUT
mVRMS
V
( )
(3)
ENABLE/SHUTDOWN
POWER GOOD
TPS74801
GND SS
OUT
FB
EN
IN
BIAS
VIN VOUT
R2
R1
CSS
CIN
C
VBIAS
CBIAS
R
COUT
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
The maximum recommended soft-start capacitor is0.015 µF. Larger soft-start capacitors can be used and
The TPS74801 provides low output noise when ado not damage the device; however, the soft-start
soft-start capacitor is used. When the device reachescapacitor discharge circuit may not be able to fully
the end of the soft-start cycle, the soft-start capacitordischarge the soft-start capacitor when enabled.
serves as a filter for the internal reference. By using aSoft-start capacitors larger than 0.015 µF could be a
0.001 µF soft-start capacitor, the output noise isproblem in applications where it is necessary to
reduced by half and is typically 30 µV
RMS
for a 1.2Vrapidly pulse the enable pin and still require the
output (10Hz to 100kHz). Further increasing C
SS
hasdevice to soft-start from ground. C
SS
must be
little effect on noise. Because most of the outputlow-leakage; X7R, X5R, or C0G dielectric materials
noise is generated by the internal reference, theare preferred. Refer to Table 2 for suggested
noise is a function of the set output voltage. The RMSsoft-start capacitor values.
noise with a 0.001 µF soft-start capacitor is given inEquation 3 :
V
IN
, V
BIAS
, and V
EN
can be sequenced in any orderwithout causing damage to the device. However, forthe soft-start function to work as intended, certain The low output noise of the TPS74801 makes it asequencing rules must be applied. Connecting EN to good choice for powering transceivers, PLLs, or otherIN is acceptable for most applications, as long as V
IN
noise-sensitive circuitry.is greater than 1.1V and the ramp rate of V
IN
andV
BIAS
is faster than the set soft-start ramp rate. If theramp rate of the input sources is slower than the set
The enable (EN) pin is active high and is compatiblesoft-start time, the output tracks the slower supply
with standard digital signaling levels. V
EN
below 0.4Vminus the dropout voltage until it reaches the set
turns the regulator off, while V
EN
above 1.1V turns theoutput voltage. If EN is connected to BIAS, the device
regulator on. Unlike many regulators, the enablesoft-starts as programmed, provided that V
IN
is
circuitry has hysteresis and deglitching for use withpresent before V
BIAS
. If V
BIAS
and V
EN
are present
relatively slowly ramping analog signals. Thisbefore V
IN
is applied and the set soft-start time has
configuration allows the TPS74801 to be enabled byexpired, then V
OUT
tracks V
IN
. If the soft-start time has
connecting the output of another supply to the ENnot expired, the output tracks V
IN
until V
OUT
reaches
pin. The enable circuitry typically has 50mV ofthe value set by the charging soft-start capacitor.
hysteresis and a deglitch circuit to help avoid on-offFigure 28 shows the use of an RC-delay circuit to
cycling as a result of small glitches in the V
EN
signal.hold off V
EN
until V
BIAS
has ramped. This techniquecan also be used to drive EN from V
IN
. An external
The enable threshold is typically 0.8V and varies withcontrol signal can also be used to enable the device
temperature and process variations. Temperatureafter V
IN
and V
BIAS
are present.
variation is approximately – 1mV/ ° C; process variationaccounts for most of the rest of the variation to theNOTE: When V
BIAS
and V
EN
are present and V
IN
is
0.4V and 1.1V limits. If precise turn-on timing isnot supplied, this device outputs approximately 50 µA
required, a fast rise-time signal must be used toof current from OUT. Although this condition does not
enable the TPS74801.cause any damage to the device, the output currentmay charge up the OUT node if total resistance
If not used, EN can be connected to either IN orbetween OUT and GND (including external feedback
BIAS. If EN is connected to IN, it should beresistors) is greater than 10k Ω.
connected as close as possible to the largestcapacitance on the input to prevent voltage droops onthat line from triggering the enable circuit.
The power good (PG) pin is an open-drain output andcan be connected to any 5.5V or lower rail through anexternal pull-up resistor. This pin requires at least1.1V on V
BIAS
in order to have a valid output. The PGoutput is high-impedance when V
OUT
is greater thanV
IT
+ V
HYS
. If V
OUT
drops below V
IT
or if V
BIAS
dropsFigure 28. Soft-Start Delay Using an RC Circuit to
below 1.9V, the open-drain output turns on and pullsEnable the Device
the PG output low. The PG pin also asserts when the
12 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
LAYOUT RECOMMENDATIONS AND POWER
INTERNAL CURRENT LIMIT
THERMAL PROTECTION
P =(V V ) I- ´
D IN OUT OUT
(4)
R =
qJA
(+125 C T )° - A
PD
(5)
TPS74801
www.ti.com
..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
device is disabled. The recommended operatingcondition of PG pin sink current is up to 1mA, so the DISSIPATIONpull-up resistor for PG should be in the range of 10k Ω
An optimal layout can greatly improve transientto 1M Ω. If output voltage monitoring is not needed,
performance, PSRR, and noise. To minimize thethe PG pin can be left floating.
voltage drop on the input of the device during loadtransients, the capacitance on IN and BIAS should beconnected as close as possible to the device. Thiscapacitance also minimizes the effects of parasiticThe TPS74801 features a factory-trimmed, accurate
inductance and resistance of the input source andcurrent limit that is flat over temperature and supply
can, therefore, improve stability. To achieve optimalvoltage. The current limit allows the device to supply
transient performance and accuracy, the top side ofsurges of up to 2A and maintain regulation. The
R
1
in Figure 25 should be connected as close ascurrent limit responds in approximately 10 µs to
possible to the load. If BIAS is connected to IN, it isreduce the current during a short-circuit fault.
recommended to connect BIAS as close to the senseThe internal current limit protection circuitry of the
point of the input supply as possible. This connectionTPS74801 is designed to protect against overload
minimizes the voltage drop on BIAS during transientconditions. It is not intended to allow operation above
conditions and can improve the turn-on response.the rated current of the device. Continuously running
Knowing the device power dissipation and properthe TPS74801 above the rated current degrades
sizing of the thermal plane that is connected to thedevice reliability.
thermal pad is critical to avoiding thermal shutdownand ensuring reliable operation. Power dissipation ofthe device depends on input voltage and loadThermal protection disables the output when the
conditions and can be calculated using Equation 4 :junction temperature rises to approximately +160 ° C,allowing the device to cool. When the junctiontemperature cools to approximately +140 ° C, the
Power dissipation can be minimized and greateroutput circuitry is enabled. Depending on power
efficiency can be achieved by using the lowestdissipation, thermal resistance, and ambient
possible input voltage necessary to achieve thetemperature the thermal protection circuit may cycle
required output voltage regulation.on and off. This cycling limits the dissipation of the
On the SON (DRC) package, the primary conductionregulator, protecting it from damage as a result of
path for heat is through the exposed pad to theoverheating.
printed circuit board (PCB). The pad can beActivation of the thermal protection circuit indicates
connected to ground or be left floating; however, itexcessive power dissipation or inadequate
should be attached to an appropriate amount ofheatsinking. For reliable operation, junction
copper PCB area to ensure the device will nottemperature should be limited to +125 ° C maximum.
overheat. The maximum junction to ambient thermalTo estimate the margin of safety in a complete design
resistance depends on the maximum ambient(including heatsink), increase the ambient
temperature, maximum device junction temperature,temperature until thermal protection is triggered; use
and power dissipation of the device, and can beworst-case loads and signal conditions. For good
calculated using Equation 5 :reliability, thermal protection should trigger at least+40 ° C above the maximum expected ambientcondition of the application. This condition produces aworst-case junction temperature of +125 ° C at the
Knowing the maximum R
θJA
and system air flow, thehighest expected ambient temperature and
minimum amount of PCB copper area needed forworst-case load.
appropriate heatsinking can be calculated usingThe internal protection circuitry of the TPS74801 is
Figure 29 through Figure 31 .designed to protect against overload conditions. It isnot intended to replace proper heatsinking.Continuously running the TPS74801 into thermalshutdown degrades device reliability.
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): TPS74801
90
85
80
75
70
65
60
55
50
45
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
4-layer,0.062” FR4.
Viasare0.012” diameter,plated.
Top/Bottomlayersare2oz.copper.
Innerlayersare1oz.copper.
R =R R R
q q q qJA JC CS SA
+ +
TJ
TC
TS
TA
RqJC
RqCS
RqSA
0.062"
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
Figure 29. DRC (3 x 3 SON) PCB Layout and Corresponding R
θJA
Data, No Vias Under Thermal Pad
14 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
90
85
80
75
70
65
60
55
50
45
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
4-layer,0.062” FR4.
Viasare0.012” diameter,plated.
Top/Bottomlayersare2oz.copper.
Innerlayersare1oz.copper.
R =R R R
q q q qJA JC CS SA
+ +
TJ
TC
TS
TA
RqJC
RqCS
RqSA
0.062"
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
www.ti.com
..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
Figure 30. DRC (3 x 3 SON) PCB Layout and Corresponding R
θJA
Data, Vias Under Thermal Pad
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): TPS74801
90
85
80
75
70
65
60
55
50
45
40
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
PCBCrossSection PCBTopView
4-layer,0.062” FR4.
Viasare0.012” diameter,plated.
Top/Bottomlayersare2oz.copper.
Innerlayersare1oz.copper.
R =R R R
q q q qJA JC CS SA
+ +
TJ
TC
TS
TA
RqJC
RqCS
RqSA
0.062"
0.5in2
1.0in2
2.0in2
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
Figure 31. DRC (3 x 3 SON) PCB Layout and Corresponding R
θJA
Data, Top Layer Only
16 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
55
50
45
40
35
30
25
00.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
qJA (°C/W)
Area(in )
2
4.5
0LFM
150LFM
250LFM
TJ
RqJC
RqCS
RqSA
TC
TS
TA
4-layer.0.062” FR4
Viasare0.012” diameter,plated
Top/Bottomlayersare2oz.copper
Innerlayersare1oz.copper
0.062in.
RqJA = R +R +R
q q qJC CS SA
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
www.ti.com
..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
Figure 32. RGW (5 x 5 QFN) PCB Layout and Corresponding R
θJA
Data, Buried Thermal Plane, No ViasUnder Thermal Pad
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s): TPS74801
TJ
RqJC
RqCS
RqSA
TC
TS
TA
4-layer.0.062” FR4
Viasare0.012” diameter,plated
Top/Bottomlayersare2oz.copper
Innerlayersare1oz.copper
0.062in.
RqJA = R +R +R
q q qJC CS SA
50
45
40
35
30
25
20
00.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
Figure 33. RGW (5 x 5 QFN) PCB Layout and Corresponding R
θJA
Data, Buried Thermal Plane, Vias UnderThermal Pad
18 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
4-layer.0.062” FR4
Viasare0.012” diameter,plated
Top/Bottomlayersare2oz.copper
Innerlayersare1oz.copper
TJ
RqJC
RqCS
RqSA
TC
TS
TA
0.062in.
RqJA = R +R +R
q q qJC CS SA
90
80
70
60
50
40
30
00.5 1.0 1.5 2.0 2.5 3.0 3.5
qJA (°C/W)
Area(in )
2
4.0
0LFM
150LFM
250LFM
PCBCrossSection PCBTopView
0.5in2
1.0in2
2.0in2
TPS74801
www.ti.com
..................................................................................................................................................... SBVS074F – JANUARY 2007 – REVISED APRIL 2009
Figure 34. RGW (5 x 5 QFN) PCB Layout and Corresponding R
θJA
Data, Top Layer Thermal Plane
Copyright © 2007 – 2009, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): TPS74801
TPS74801
SBVS074F – JANUARY 2007 – REVISED APRIL 2009 .....................................................................................................................................................
www.ti.com
Revision History
Changes from Revision D (August 2008) to Revision E ................................................................................................ Page
•Added Revision History table ................................................................................................................................................. 1•Corrected y-axis of Figure 17 ................................................................................................................................................ 8•Deleted sentence about PG pin availability on device packages from Power Good section for clarification ...................... 12
20 Submit Documentation Feedback Copyright © 2007 – 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS74801
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS74801DRCR ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCRG4 ACTIVE SON DRC 10 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCT ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801DRCTG4 ACTIVE SON DRC 10 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWR ACTIVE VQFN RGW 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWRG4 ACTIVE VQFN RGW 20 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWT ACTIVE VQFN RGW 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS74801RGWTG4 ACTIVE VQFN RGW 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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PACKAGE OPTION ADDENDUM
www.ti.com 26-Jan-2010
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS74801DRCR SON DRC 10 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS74801DRCT SON DRC 10 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
TPS74801RGWR VQFN RGW 20 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
TPS74801RGWT VQFN RGW 20 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Dec-2009
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS74801DRCR SON DRC 10 3000 346.0 346.0 29.0
TPS74801DRCT SON DRC 10 250 190.5 212.7 31.8
TPS74801RGWR VQFN RGW 20 3000 346.0 346.0 29.0
TPS74801RGWT VQFN RGW 20 250 190.5 212.7 31.8
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Dec-2009
Pack Materials-Page 2
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