Wideband Synthesizer with Integrated VCO
ADF4350
Rev. A
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FEATURES
Output frequency range: 137.5 MHz to 4400 MHz
Fractional-N synthesizer and integer-N synthesizer
Low phase noise VCO
Programmable divide-by-1/-2/-4/-8/-16 output
Typical rms jitter: <0.4 ps rms
Power supply: 3.0 V to 3.6 V
Logic compatibility: 1.8 V
Programmable dual-modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
Switched bandwidth fast-lock mode
Cycle slip reduction
APPLICATIONS
Wireless infrastructure (W-CDMA, TD-SCDMA, WiMAX,
GSM, PCS, DCS, DECT)
Test equipment
Wireless LANs, CATV equipment
Clock generation
GENERAL DESCRIPTION
The ADF4350 allows implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers
if used with an external loop filter and external reference
frequency.
The ADF4350 has an integrated voltage controlled oscillator
(VCO) with a fundamental output frequency ranging from
2200 MHz to 4400 MHz. In addition, divide-by-1/2/4/8 or 16
circuits allow the user to generate RF output frequencies as low
as 137.5 MHz. For applications that require isolation, the RF
output stage can be muted. The mute function is both pin- and
software-controllable. An auxiliary RF output is also available,
which can be powered down if not in use.
Control of all the on-chip registers is through a simple 3-wire
interface. The device operates with a power supply ranging
from 3.0 V to 3.6 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
MUXOUT
CP
OUT
LD
SW
V
COM
TEMP
REF
IN
CLK
DATA
LE
AV
DD
SDV
DD
DV
DD
V
P
AGND
CE DGND CP
GND
SD
GND
A
GNDVCO
R
SET
V
VCO
V
TUNE
V
REF
RF
OUT
A+
RF
OUT
A–
RF
OUT
B+
RF
OUT
B–
VCO
CORE
PHASE
COMPARATOR
FL
O
SWITCH
CHARGE
PUMP
OUTPUT
STAGE
OUTPUT
STAGE
PDB
RF
MULTIPLEXER
MULTIPLEXER
10-BIT R
COUNTER
÷2
DIVIDER
×2
DOUBLER
FUNCTION
LATCH
DATA REGISTER
INTEGER
REG
N COUNTER
FRACTION
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
MODULUS
REG
MULTIPLEXER
LOCK
DETECT
÷1/2/4/8/16
ADF4350
07325-001
Figure 1.
ADF4350
Rev. A | Page 2 of 32
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Transistor Count........................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 9
Circuit Description......................................................................... 11
Reference Input Section............................................................. 11
RF N Divider............................................................................... 11
INT, FRAC, MOD, and R Counter Relationship.................... 11
INT N MODE ............................................................................. 11
R Counter .................................................................................... 11
Phase Frequency Detector (PFD) and Charge Pump............ 11
MUXOUT and LOCK Detect................................................... 12
Input Shift Registers................................................................... 12
Program Modes .......................................................................... 12
VCO.............................................................................................. 12
Output Stage................................................................................ 13
Register Maps .................................................................................. 14
Register 0 ..................................................................................... 18
Register 1 ..................................................................................... 18
Register 2 ..................................................................................... 18
Register 3 ..................................................................................... 20
Register 4 ..................................................................................... 20
Register 5 ..................................................................................... 20
Initialization Sequence .............................................................. 21
RF Synthesizer—A Worked Example ...................................... 21
Modulus....................................................................................... 21
Reference Doubler and Reference Divider ............................. 21
12-Bit Programmable Modulus................................................ 21
Cycle Slip Reduction for Faster Lock Times........................... 22
Spurious Optimization and Fast lock ...................................... 22
Fast-Lock Timer and Register Sequences ............................... 22
Fast Lock—An Example............................................................ 22
Fast Lock—Loop Filter Topology............................................. 23
Spur Mechanisms ....................................................................... 23
Spur Consistency and Fractional Spur Optimization ........... 24
Phase Resync............................................................................... 24
Applications Information.............................................................. 25
Direct Conversion Modulator .................................................. 25
Interfacing ................................................................................... 26
PCB Design Guidelines for a Chip Scale Package ................. 26
Output Matching........................................................................ 27
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 29
REVISION HISTORY
4/11—Rev. 0 to Rev. A
Changes to Typical rms Jitter in Features Section........................ 1
Changes to Specifications................................................................ 3
Changes Output Stage Section...................................................... 13
Changes to Figure 29...................................................................... 17
Changes to Fast Lock—An Example Section.............................. 22
Changes to Direct Conversion Modulator Section and
Figure 34 ......................................................................................... 25
Changes to ADuC70xx Interface Section and ADSP-BF527
Interface Section ............................................................................. 26
Changes to Output Matching Section and Table 7..................... 27
Added Table 8.................................................................................. 28
Changes to Ordering Guide .......................................................... 29
11/08—Revision 0: Initial Version
ADF4350
Rev. A | Page 3 of 32
SPECIFICATIONS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Operating
temperature range is −40°C to +85°C.
Table 1.
B Version
Parameter Min Typ Max
Unit Conditions/Comments
REFIN CHARACTERISTICS
Input Frequency 10 250 MHz For f < 10 MHz ensure slew rate > 21 V/μs
Input Sensitivity 0.7 AVDD V p-p Biased at AVDD/21
Input Capacitance 10 pF
Input Current ±60 μA
PHASE DETECTOR
Phase Detector Frequency2 32 MHz
CHARGE PUMP
ICP Sink/Source3 With RSET = 5.1 kΩ
High Value 5 mA
Low Value 0.312 mA
RSET Range 2.7 10
Sink and Source Current Matching 2 % 0.5 V ≤ VCP ≤ 2.5 V
ICP vs. VCP 1.5 % 0.5 V ≤ VCP ≤ 2.5 V
ICP vs. Temperature 2 % VCP = 2.0 V
LOGIC INPUTS
Input High Voltage, VINH 1.5 V
Input Low Voltage, VINL 0.6 V
Input Current, IINH/IINL ±1 μA
Input Capacitance, CIN 3.0 pF
LOGIC OUTPUTS
Output High Voltage, VOH DVDD − 0.4 V CMOS output chosen
Output High Current, IOH 500 μA
Output Low Voltage, VOL 0.4 V IOL = 500 μA
POWER SUPPLIES
AVDD 3.0 3.6 V
DVDD, VVCO, SDVDD, VP AVDD These voltages must equal AVDD
DIDD + AIDD4 21 27 mA
Output Dividers 6 to 24 mA Each output divide-by-2 consumes 6 mA
IVCO4 70 80 mA
IRFOUT4 21 26 mA RF output stage is programmable
Low Power Sleep Mode 7 1000 μA
RF OUTPUT CHARACTERISTICS
Maximum VCO Output Frequency 4400 MHz
Minimum VCO Output Frequency 2200 MHz Fundamental VCO mode
Minimum VCO Output Frequency
Using Dividers
137.5 MHz 2200 MHz fundamental output and divide by 16 selected
VCO Sensitivity 33 MHz/V
Frequency Pushing (Open-Loop) 1 MHz/V
Frequency Pulling (Open-Loop) 90 kHz Into 2.00 VSWR load
Harmonic Content (Second) −19 dBc Fundamental VCO output
Harmonic Content (Third) −13 dBc Fundamental VCO output
Harmonic Content (Second) −20 dBc Divided VCO output
Harmonic Content (Third) −10 dBc Divided VCO output
Minimum RF Output Power 5 −4 dBm Programmable in 3 dB steps
Maximum RF Output Power5 5 dBm
Output Power Variation ±1 dB
Minimum VCO Tuning Voltage 0.5 V
Maximum VCO Tuning Voltage 2.5 V
ADF4350
Rev. A | Page 4 of 32
B Version
Parameter Min Typ Max
Unit Conditions/Comments
NOISE CHARACTERISTICS
VCO Phase-Noise Performance6 −89 dBc/Hz 10 kHz offset from 2.2 GHz carrier
−114 dBc/Hz 100 kHz offset from 2.2 GHz carrier
−134 dBc/Hz 1 MHz offset from 2.2 GHz carrier
−148 dBc/Hz 5 MHz offset from 2.2 GHz carrier
−86 dBc/Hz 10 kHz offset from 3.3 GHz carrier
−111 dBc/Hz 100 kHz offset from 3.3 GHz carrier
−134 dBc/Hz 1 MHz offset from 3.3 GHz carrier
−145 dBc/Hz 5 MHz offset from 3.3 GHz carrier
−83 dBc/Hz 10 kHz offset from 4.4 GHz carrier
−110 dBc/Hz 100 kHz offset from 4.4 GHz carrier
−132 dBc/Hz 1 MHz offset from 4.4 GHz carrier
−145 dBc/Hz 5 MHz offset from 4.4 GHz carrier
Normalized Phase Noise Floor
(PNSYNTH)7
−220 dBc/Hz PLL Loop BW = 500 kHz
Normalized 1/f Noise (PN1_f)8 −111 dBc/Hz 10 kHz offset; normalized to 1 GHz
In-Band Phase Noise9 −97 dBc/Hz 3 kHz offset from 2113.5 MHz carrier
Integrated RMS Jitter10 0.5 ps
Spurious Signals Due to PFD Frequency −70 dBc
Level of Signal With RF Mute Enabled −40 dBm
1 AC coupling ensures AVDD/2 bias.
2 Guaranteed by design. Sample tested to ensure compliance.
3 ICP is internally modified to maintain constant loop gain over the frequency range.
4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; prescaler = 8/9; fREFIN = 100 MHz; fPFD = 25 MHz; fRF = 4.4 GHz.
5 Using 50 Ω resistors to VVCO, into a 50 Ω load. Power measured with auxiliary RF output disabled. The current consumption of the auxiliary output is the same as for the
main output.
6 The noise of the VCO is measured in open-loop conditions.
7 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider
value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N.
8 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF,
and at a frequency offset f is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL.
9 fREFIN = 100 MHz; fPFD = 25 MHz; offset frequency = 10 kHz; VCO frequency = 4227 MHz, output divide by two enabled. RFOUT = 2113.5 MHz; N = 169; loop BW = 40 kHz,
ICP = 313 μA; low noise mode. The noise was measured with an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.
10 fREFIN = 100 MHz; fPFD = 25 MHz; VCO frequency = 4400 MHz, RFOUT = 4400 MHz; N = 176; loop BW = 40 kHz, ICP = 313 μA; low noise mode. The noise was measured with
an EVAL-ADF4350EB1Z and the Agilent E5052A signal source analyzer.
ADF4350
Rev. A | Page 5 of 32
TIMING CHARACTERISTICS
AVDD = DVDD = VVCO = SDVDD = VP = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless
otherwise noted.
Table 2.
Parameter Limit (B Version) Unit Test Conditions/Comments
t1 20 ns min LE setup time
t2 10 ns min DATA to CLK setup time
t3 10 ns min DATA to CLK hold time
t4 25 ns min CLK high duration
t5 25 ns min CLK low duration
t6 10 ns min CLK to LE setup time
t7 20 ns min LE pulse width
CLK
DATA
LE
LE
DB31 (MSB) DB30 DB1
(CONTROL BIT C2)
DB2
(CONTROL BIT C3)
DB0 (LSB)
(CONTROL BIT C1)
t
1
t
2
t
3
t
7
t
6
t
4
t
5
07325-002
Figure 2. Timing Diagram
ADF4350
Rev. A | Page 6 of 32
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
AVDD to GND1 −0.3 V to +3.9 V
AVDD to DVDD −0.3 V to +0.3 V
VVCO to GND −0.3 V to +3.9 V
VVCO to AVDD −0.3 V to +0.3 V
Digital I/O Voltage to GND −0.3 V to VDD + 0.3 V
Analog I/O Voltage to GND −0.3 V to VDD + 0.3 V
REFIN to GND −0.3 V to VDD + 0.3 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
Maximum Junction Temperature 150°C
LFCSP θJA Thermal Impedance 27.3°C/W
(Paddle-Soldered)
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 40 sec
1 GND = AGND = DGND = 0 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
This device is a high-performance RF integrated circuit with an
ESD rating of <0.5 kV and is ESD sensitive. Proper precautions
should be taken for handling and assembly.
TRANSISTOR COUNT
24202 (CMOS) and 918 (bipolar)
ESD CAUTION
ADF4350
Rev. A | Page 7 of 32
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
CLK
2
DATA
3
LE
4
CE
5
SW
6
7
24
V
REF
23
V
COM
22
21
20
19
18
17
8
SDV
DD
ADF4350
TOP VIEW
(Not to Scale)
9
AGND
10
AV
DD
11
REF
IN
12
DGND
13
DV
DD
14
15
16
32
31
30
29
28
SD
GND
27
26
25
PIN 1
INDICATOR
V
P
CP
OUT
CP
GND
MUXOUT
R
SET
RF
OUT
A+
RF
OUT
B+
RF
OUT
B
RF
OUT
A
V
VCO
V
TUNE
A
GNDVCO
A
GNDVCO
TEM
P
PDB
RF
LD
A
GNDVCO
V
VCO
07325-003
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 CLK
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
2 DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs as the control bits. This input is a high
impedance CMOS input.
3 LE Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the three LSBs.
4 CE Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device depending on the status of the power-down bits.
5 SW Fast-Lock Switch. A connection should be made from the loop filter to this pin when using the fast-lock mode.
6 VP Charge Pump Power Supply. This pin is to be equal to AVDD. Decoupling capacitors to the ground plane are to
be placed as close as possible to this pin.
7 CPOUT Charge Pump Output. When enabled, this provides ±ICP to the external loop filter. The output of the loop filter is
connected to VTUNE to drive the internal VCO.
8 CPGND Charge Pump Ground. This is the ground return pin for CPOUT.
9 AGND Analog Ground. This is a ground return pin for AVDD.
10 AVDD Analog Power Supply. This pin ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane are
to be placed as close as possible to this pin. AVDD must have the same value as DVDD.
11, 18, 21 AGNDVCO VCO Analog Ground. These are the ground return pins for the VCO.
12 RFOUTA+ VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
13 RFOUTA− Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
14 RFOUTB+ Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
15 RFOUTB− Complementary Auxilliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
16, 17 VVCO Power Supply for the VCO. This ranges from 3.0 V to 3.6 V. Decoupling capacitors to the analog ground plane
should be placed as close as possible to these pins. VVCO must have the same value as AVDD.
19 TEMP
Temperature Compensation Output. Decoupling capacitors to the ground plane are to be placed as close as
possible to this pin.
20 VTUNE Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage.
ADF4350
Rev. A | Page 8 of 32
Pin No. Mnemonic Description
22 RSET Connecting a resistor between this pin and GND sets the charge pump output current. The nominal voltage
bias at the RSET pin is 0.55 V. The relationship between ICP and RSET is
SET
CP R
25.5
I=
where:
RSET = 5.1 kΩ
ICP = 5 mA
23 VCOM Internal Compensation Node Biased at Half the Tuning Range. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
24 VREF Reference Voltage. Decoupling capacitors to the ground plane should be placed as close as possible to this pin.
25 LD Lock Detect Output Pin. This pin outputs a logic high to indicate PLL lock. A logic low output indicates loss of PLL lock.
26 PDBRF RF Power-Down. A logic low on this pin mutes the RF outputs. This function is also software controllable.
27 DGND Digital Ground. Ground return path for DVDD.
28 DVDD Digital Power Supply. This pin should be the same voltage as AVDD. Decoupling capacitors to the ground plane
should be placed as close as possible to this pin.
29 REFIN Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and a dc equivalent input resistance of
100 kΩ. This input can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
30 MUXOUT
Multiplexer Output. This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
31 SDGND Digital Sigma-Delta (Σ-Δ) Modulator Ground. Ground return path for the Σ-Δ modulator.
32 SDVDD Power Supply Pin for the Digital Σ-Δ Modulator. Should be the same voltage as AVDD. Decoupling capacitors to
the ground plane are to be placed as close as possible to this pin.
33 EP Exposed Pad.
ADF4350
Rev. A | Page 9 of 32
TYPICAL PERFORMANCE CHARACTERISTICS
–150
–160
–140
–120
–100
–80
–130
–110
–90
–70
–60
–50
40
1k 10k 100k 1M 10M 100M
07325-028
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
Figure 4. Open-Loop VCO Phase Noise, 2.2 GHz
1k 10k 100k 1M 10M 100M
07325-029
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
–150
–160
–140
–120
–100
–80
–130
–110
–90
–70
–60
–50
40
Figure 5. Open-Loop VCO Phase Noise, 3.3 GHz
–140
–120
–100
–80
–130
–160
–150
–110
–90
–70
–60
–50
40
1k 10k 100k 1M 10M 100M
07325-030
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
Figure 6. Open-Loop VCO Phase Noise, 4.4 GHz
–170
–160
–150
–140
–130
–120
–110
–100
–90
70
–80
1k 10k 100k 1M 10M 100M
07325-031
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
FUND
DIV2
DIV4
DIV8
DIV16
Figure 7. Closed-Loop Phase Noise, Fundamental VCO and Dividers,
VCO = 2.2 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz
–170
–160
–150
–140
–130
–120
–110
–100
–90
70
–80
PHASE NOISE (dBc/Hz)
FUND
DIV2
DIV4
DIV8
DIV16
1k 10k 100k 1M 10M 100M
07325-032
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
Figure 8. Closed-Loop Phase Noise, Fundamental VCO and Dividers,
VCO = 3.3 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz
–170
–160
–150
–140
–130
–120
–110
–100
–90
70
–80
FUND
DIV2
DIV4
DIV8
DIV16
1k 10k 100k 1M 10M 100M
07325-033
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
Figure 9. Closed-Loop Phase Noise, Fundamental VCO and Dividers,
VCO = 4.4 GHz, PFD = 25 MHz, Loop Bandwidth = 40 kHz
ADF4350
Rev. A | Page 10 of 32
0
–20
–40
–60
–80
–100
–120
–140
–160
PHASE NOISE (dBc/Hz)
1k 10k
FREQUENCY (Hz)
100k 1M
07325-034
10M
Figure 10. Integer-N Phase Noise and Spur Performance. GSM900 Band,
RFOUT = 904 MHz, REFIN = 100 MHz, PFD = 800 kHz, Output Divide-by-4
Selected; Loop-Filter Bandwidth = 16 kHz, Channel Spacing = 200 kHz.
0
–20
–40
–60
–80
–100
–120
–140
–160
PHASE NOISE (dBc/Hz)
1k 10k
FREQUENCY (Hz)
100k 1M
07325-035
10M
Figure 11. Fractional-N Spur Performance; Low Noise Mode. W-CDMA Band,
RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2
Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz.
0
–20
–40
–60
–80
–100
–120
–140
–160
PHASE NOISE (dBc/Hz)
1k 10k
FREQUENCY (Hz)
100k 1M
07325-036
10M
Figure 12. Fractional-N Spur Performance. Low Spur Mode, W-CDMA Band
RFOUT = 2113.5 MHz, REFIN = 100 MHz, PFD = 25 MHz, Output Divide-by-2
Selected; Loop Filter Bandwidth = 40 kHz, Channel Spacing = 200 kHz
0
–20
–40
–60
–80
–100
–120
–140
–160
PHASE NOISE (dBc/Hz)
1k 10k
FREQUENCY (Hz)
100k 1M
07325-037
10M
Figure 13. Fractional-N Spur Performance. Low Noise Mode, RFOUT =
2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected;
Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz.
0
–20
–40
–60
–80
–100
–120
–140
–160
PHASE NOISE (dBc/Hz)
1k 10k
FREQUENCY (Hz)
100k 1M
07325-038
10M
Figure 14. Fractional-N Spur Performance. Low Spur Mode RFOUT =
2.591 GHz, REFIN = 105 MHz, PFD = 17.5 MHz, Output Divide-by-1 Selected.
Loop Filter Bandwidth = 20 kHz, Channel Spacing = 100 kHz (Note That
Fractional Spurs Are Removed and Only the Integer Boundary Spur Remains
in Low Spur Mode).
2.95
2.96
2.97
2.98
2.99
3.00
3.01
3.02
FREQUENCY (GHz)
CSR OFF
CSR ON
0 100 200 300
TIME (µs)
400 500 600
07325-039
Figure 15. Lock Time for 100 MHz Jump from 3070 MHz to 2970 MHz with
CSR On and Of f, PFD = 25 MHz, ICP = 313 μA, Loop Filter Bandwidth = 20 kHz
ADF4350
Rev. A | Page 11 of 32
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 16. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed, and SW1 and SW2 are
opened. This ensures that there is no loading of the REFIN pin
during power-down.
07325-005
BUFFER
TO R COUNTER
REF
IN
100k
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
Figure 16. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. The division ratio is determined by INT, FRAC and MOD
values, which build up this divider.
INT, FRAC, MOD, AND R COUNTER RELATIONSHIP
The INT, FRAC, and MOD values, in conjunction with the
R counter, make it possible to generate output frequencies
that are spaced by fractions of the PFD frequency. See the RF
Synthesizer—A Worked Example section for more information.
The RF VCO frequency (RFOUT) equation is
RFOUT = fPFD × (INT + (FRAC/MOD)) (1)
where RFOUT is the output frequency of external voltage
controlled oscillator (VCO).
INT is the preset divide ratio of the binary 16-bit counter
(23 to 65535 for 4/5 prescaler, 75 to 65,535 for 8/9 prescaler).
MOD is the preset fractional modulus (2 to 4095).
FRAC is the numerator of the fractional division (0 to MOD − 1).
fPFD = REFIN × [(1 + D)/(R × (1 + T))] (2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
T is the REFIN divide-by-2 bit (0 or 1).
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
FRAC
VALUE
MOD
REG
INT
REG
RF N DIVIDER N = INT + FRAC/MOD
FROM
VCO OUTPUT/
OUTPUT DIVIDERS TO PFD
N COUNTER
07325-006
Figure 17. RF INT Divider
INT N MODE
If the FRAC = 0 and DB8 in Register 2 (LDF) is set to 1, the
synthesizer operates in integer-N mode. The DB8 in Register 2
(LDF) should be set to 1 to get integer-N digital lock detect.
R COUNTER
The 10–bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock
to the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The phase frequency detector (PFD) takes inputs from the
R counter and N counter and produces an output proportional
to the phase and frequency difference between them. Figure 18
is a simplified schematic of the phase frequency detector. The
PFD includes a fixed delay element that sets the width of the
antibacklash pulse, which is typically 3 ns. This pulse ensures
there is no dead zone in the PFD transfer function, and gives a
consistent reference spur level.
U3
CLR2
Q2D2
U2
DOWN
UP
HIGH
HIGH
CP
–IN
N
CHARGE
PUMP
DELAY
CLR1
Q1D1
U1
07325-007
+I
Figure 18. PFD Simplified Schematic
ADF4350
Rev. A | Page 12 of 32
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4350 allows the user
to access various internal points on the chip. The state of
MUXOUT is controlled by M3, M2, and M1 (for details,
see Figure 26). Figure 19 shows the MUXOUT section in
block diagram form.
DGND
DV
DD
CONTROL
MUX
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
R COUNTER OUTPUT
N COUNTER OUTPUT
DGND
RESERVED
THREE-STATE OUTPUT
DV
DD
Figure 19. MUXOUT Schematic
INPUT SHIFT REGISTERS
The ADF4350 digital section includes a 10–bit RF R counter,
a 16–bit RF N counter, a 12-bit FRAC counter, and a 12–bit
modulus counter. Data is clocked into the 32–bit shift register
on each rising edge of CLK. The data is clocked in MSB first.
Data is transferred from the shift register to one of six latches
on the rising edge of LE. The destination latch is determined by
the state of the three control bits (C3, C2, and C1) in the shift
register. These are the 3 LSBs, DB2, DB1, and DB0, as shown
in Figure 2. The truth table for these bits is shown in Table 5.
Figure 23 shows a summary of how the latches are programmed.
Table 5. C3, C2, and C1 Truth Table
Control Bits
C3 C2 C1 Register
0 0 0 Register 0 (R0)
0 0 1 Register 1 (R1)
0 1 0 Register 2 (R2)
0 1 1 Register 3 (R3)
1 0 0 Register 4 (R4)
1 0 1 Register 5 (R5)
PROGRAM MODES
Tabl e 5 and Figure 23 through Figure 29 show how the program
modes are to be set up in the ADF4350.
A number of settings in the ADF4350 are double buffered.
These include the modulus value, phase value, R counter value,
reference doubler, reference divide-by-2, and current setting.
This means that two events have to occur before the part uses
a new value of any of the double buffered settings. First, the
new value is latched into the device by writing to the appropriate
register. Second, a new write must be performed on Register R0.
For example, any time the modulus value is updated, Register 0
(R0) must be written to, to ensure the modulus value is loaded
correctly. Divider select in Register 4 (R4) is also double buf-
fered, but only if DB13 of Register 2 (R2) is high.
VCO
The VCO core in the ADF4350 consists of three separate VCOs
each of which uses 16 overlapping bands, as shown in Figure 20,
to allow a wide frequency range to be covered without a large
VCO sensitivity (KV) and resultant poor phase noise and spu-
rious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic at power-up or whenever Register 0
(R0) is updated.
VCO and band selection take 10 PFD cycles × band select clock
divider value. The VCO VTUNE is disconnected from the output
of the loop filter and is connected to an internal reference voltage.
2.8
2.4
2.0
1.6
0.8
1.2
0.4
0
1800
2000
2200
2400
2600
2800
3000
3200
3400
3600
3800
4000
4200
4400
4600
07325-009
FREQUENCY (MHz)
V
TUNE
(V)
Figure 20. VTUNE vs. Frequency
The R counter output is used as the clock for the band select
logic. A programmable divider is provided at the R counter
output to allow division by 1 to 255 and is controlled by
Bits [BS8:BS1] in Register 4 (R4). When the required PFD
frequency is higher than 125 kHz, the divide ratio should be
set to allow enough time for correct band selection.
After band select, normal PLL action resumes. The nominal
value of KV is 33 MHz/V when the N-divider is driven from the
VCO output or this value divided by D. D is the output divider
value if the N-divider is driven from the RF divider output
(chosen by programming Bits [D12:D10] in Register 4 (R4).
The ADF4350 contains linearization circuitry to minimize
any variation of the product of ICP and KV to keep the loop
bandwidth constant.
ADF4350
Rev. A | Page 13 of 32
OUTPUT STAGE
The VCO shows variation of KV as the VTUNE varies within the
band and from band-to-band. It has been shown for wideband
applications covering a wide frequency range (and changing
output dividers) that a value of 33 MHz/V provides the most
accurate KV as this is closest to an average value. Figure 21
shows how KV varies with fundamental VCO frequency along
with an average value for the frequency band. Users may prefer
this figure when using narrowband designs.
The RFOUTA+ and RFOUTA− pins of the ADF4350 are connected
to the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 22. To allow the user to
optimize the power dissipation vs. the output power requirements,
the tail current of the differential pair is programmable by
Bits [D2:D1] in Register 4 (R4). Four current levels may be set.
These levels give output power levels of −4 dBm, −1 dBm, +2
dBm, and +5 dBm, respectively, using a 50 Ω resistor to AVDD
and ac coupling into a 50 Ω load. Alternatively, both outputs
can be combined in a 1 + 1:1 transformer or a 180° microstrip
coupler (see the Output Matching section). If the outputs are
used individually, the optimum output stage consists of a shunt
inductor to VVCO. The unused complementary output must
be terminated with a similar circuit to the used output.
80
70
60
50
40
30
20
10
0
2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6
07325-133
VCO SENSITIVITY (MHz/V)
FREQUENCY (GHz)
An auxiliary output stage exists on Pins RFOUTB+ and RFOUTB−
providing a second set of differential outputs which can be
used to drive another circuit, or which can be powered down
if unused. The auxiliary output must be used in conjunction
with the main RF output. It cannot be used with the main
output powered down.
Another feature of the ADF4350 is that the supply current to
the RF output stage can be shut down until the part achieves
lock as measured by the digital lock detect circuitry. This is
enabled by the mute till lock detect (MTLD) bit in Register 4 (R4).
Figure 21. KV vs. Frequency
In fixed frequency applications, the ADF4350 VTUNE may
vary with ambient temperature switching from hot to cold.
In extreme cases, the drift causes VTUNE to drop to a very low
level (<0.25 V) and can cause loss of lock. This becomes an
issue only at fundamental VCO frequencies less than 2.95 GHz
and at ambient temperatures below 0°C.
VCO
RF
OUT
A+ RF
OUT
A
BUFFER/
DIVIDE-BY-
1/2/4/8/16
07325-010
In cases such as these, if the ambient temperature decreases
below 0°C, the frequency needs to be reprogrammed (R0 updated)
to avoid VTUNE dropping to a level close to 0 V. Reprogramming
the part chooses a more suitable VCO band, and thus avoids
the low VTUNE issue. Any further temperature drops of more
than 20°C (below 0°C) also require further reprogramming.
Any increases in the ambient temperature do not require repro-
gramming.
Figure 22. Output Stage
ADF4350
Rev. A | Page 14 of 32
REGISTER MAPS
07325-011
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0N16 N15 N14 N13 N12 N11 N10 N9
RESERVED
16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC) CONTROL
BITS
N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 PR1 P12 P11 P10 P9
12-BIT PHASE VALUE (PHASE) 12-BIT MODULUS VALUE (MOD) CONTROL
BITS
P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)
CSR
RDIV2
REFERENCE
DOUBLER
CHARGE
PUMP
CURRENT
SETTING
10-BIT R COUNTER CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)
CONTROL
BITS
12-BIT CLOCK DIVIDER VALUE
LDP
PD
POLARITY
PD
CP THREE-
STATE
COUNTER
RESET
OUTPUT
POWER
CLK
DIV
MODE
DBR 1
1
DBR = DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
2
DBB = DOUBLE BUFFERED BITS—BUFFERED BY THE WRITE TO REGISTER 0, IF AND ONLY IF DB13 OF REGISTER 2 IS HIGH.
RESERVED
LDF
RESERVED
RESERVED
REGISTER 4
VCO POWER
DOWN
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
CONTROL
BITS
8-BIT BAND SELECT CLOCK DIVIDER VALUE
RF OUTPUT
ENABLE
LD PIN
MODE
AUX OUTPUT
ENABLE
AUX OUTPUT
SELECT
MTLD
DIVIDER
SELECT
FEEDBACK
SELECT
REGISTER 0
REGISTER 1
REGISTER 2
REGISTER 3
REGISTER 5
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000000D15D140110000000000000000C3(1)C2(0)C1(1)
CONTROL
BITS
RESERVED
RESERVED
DBB 2
DOUBLE BUFF
RESERVED
RESERVED
DBR
1
DBR
1
DBR
1
DBR
1
DBR
1
AUX
OUTPUT
POWER
RESERVED
RESERVED
RESERVED
PRESCALER
LOW
NOISE AND
LOW SPUR
MODES MUXOUT
Figure 23. Register Summary
ADF4350
Rev. A | Page 15 of 32
07325-012
N16N15...N5N4N3N2N1 INTEGER VALUE (INT)
00...00000 NOT ALLOWED
00...00001 NOT ALLOWED
00...00010 NOT ALLOWED
.......... ...
00...10110 NOT ALLOWED
00...10111 23
00...11000 24
.......... ...
11...11101 65533
11...11110 65534
11...11111 65535
F12 F11 .......... F2 F1 FRACTIONAL VALUE (FRAC)
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 ......... 1 1 4095
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0N16 N15 N14 N13 N12 N11 N10 N9
RESERVED
16-BIT INTEGER VALUE (INT) 12-BIT FRACTIONAL VALUE (FRAC)
CONTROL
BITS
N8 N7 N6 N5 N4 N3 N2 N1 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 C3(0) C2(0) C1(0)
INTmin = 75 with prescaler = 8/9
Figure 24. Register 0 (R0)
0
7325-013
P12 P11 .......... P2 P1 PHASE VALUE (PHASE)
0 0 .......... 0 0 0
0 0 .......... 0 1 1 (RECOMMENDED)
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 PR1 P12 P11 P10 P9
12-BIT PHASE VALUE (PHASE) 12-BIT MODULUS VALUE (MOD)
CONTROL
BITS
P8 P7 P6 P5 P4 P3 P2 P1 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 C3(0) C2(0) C1(1)
RESERVED
M12 M11 ..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
M2 M1 INTERPOLATOR MODULUS (MOD)
00 102
00 113
.. ...
.. ...
.. ...
1 1 0 0 4092
1 1 0 1 4093
1 1 1 0 4094
1 1 1 1 4095
PRESCALER
P1 PRESCALER
04/5
18/9
DBR DBR
Figure 25. Register 1 (R1)
ADF4350
Rev. A | Page 16 of 32
07325-014
RD2 REFERENCE
DOUBLER
0DISABLED
1 ENABLED
RD1 REFERENCE DIVIDE BY 2
0DISABLED
1 ENABLED
CP4 CP3 CP2 CP1
ICP (mA)
5.1k
00000.31
00010.63
00100.94
00111.25
01001.56
01011.88
01102.19
01112.50
10002.81
10013.13
10103.44
10113.75
11004.06
11014.38
11104.69
11115.00
R10 R9 ..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
R2 R1 R DIVIDER (R)
00 011
00 102
.. ...
.. ...
.. ...
11 001020
11 011021
11 101022
11 111023
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 L2 L1 M3 M2 M1 RD2 RD1 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 D1 CP4 CP3 CP2 CP1 U6 U5 U4 U3 U2 U1 C3(0) C2(1) C1(0)
RDIV2 DBR
REFERENCE
DOUBLER DBR
CHARGE
PUMP
CURRENT
SETTING
10-BIT R COUNTER DBR
CONTROL
BITS
LDP
PD
POLARITY
POWER-DOWN
CP THREE-
STATE
COUNTER
RESET
LDF
MUXOUT
DOUBLE BUFF
U5 LDP
0 10ns
16ns
U4 PD POLARITY
0NEGATIVE
1 POSITIVE
U3 POWER DOWN
0DISABLED
1 ENABLED
U2 CP
THREE-STATE
0DISABLED
1 ENABLED
U1 COUNTER
RESET
0DISABLED
1 ENABLED
D1 DOUBLEBUFFER
R4 DB22-20
0DISABLED
1 ENABLED
U6 LDF
0 FRAC-N
1INT-N
RESERVED
M3 M2 M1 OUTPUT
0 0 0 THREE-STATE OUTPUT
00 1DV
DD
01 0DGND
0 1 1 R DIVIDER OUTPUT
1 0 0 N DIVIDER OUTPUT
1 0 1 ANALOG LOCK DETECT
1 1 0 DIGITAL LOCK DETECT
1 1 1 RESERVED
L1 L2 NOISE MODE
00LOWNOISEMODE
0 1 RESERVED
1 0 RESERVED
11LOWSPURMODE
LOW
NOISE AND
LOW SPUR
MODES
Figure 26. Register 2 (R2)
07325-015
C2 C 1 CLOCK DIVIDER MODE
0 0 CLOCK DIVIDER OFF
0 1 FAST-LOCK ENABLE
1 0 RESYNC ENABLE
1 1 RESERVED
D12 D11 .......... D2 D1 CLOCK DIVIDER VALUE
0 0 .......... 0 0 0
0 0 .......... 0 1 1
0 0 .......... 1 0 2
0 0 .......... 1 1 3
. . .......... . . .
. . .......... . . .
. . .......... . . .
1 1 .......... 0 0 4092
1 1 .......... 0 1 4093
1 1 .......... 1 0 4094
1 1 .......... 1 1 4095
CSR
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 0 0 0 F1 0 C2 C1 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(0) C2(1) C1(1)
CONTROL
BITS12-BIT CLOCK DIVIDER VALUE
CLK
DIV
MODE
RESERVED
F1 CYCLE SLIP
REDUCTION
0DISABLED
1 ENABLED
RESERVED
00
RESERVED
Figure 27. Register 3 (R3)
ADF4350
Rev. A | Page 17 of 32
07325-016
BS8 BS7 ..........
..........
..........
..........
..........
..........
..........
..........
..........
..........
BS2 BS1 BAND SELECT CLOCK DIVIDER (R)
00 011
00 102
.. ...
.. ...
.. ...
1 1 0 0 252
1 1 0 1 253
1 1 1 0 254
11 11255
D3 RF OUT
0 DISABLED
1 ENABLED
OUTPUT
POWER
VCO POWER-
DOWN
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
0 0 0 0 0 0 0 0 D13 D12 D11 D10 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 D9 D8 D7 D6 D5 D4 D3 D2 D1 C3(1) C2(0) C1(0)
CONTROL
BITS
8-BIT BAND SELECT CLOCK DIVIDER VALUE
RF OUTPUT
ENABLE
AUX
OUTPUT
POWER
AUX OUTPUT
ENABLE
AUX OUTPUT
SELECT
MTLD
DIVIDER
SELECT
FEEDBACK
SELECT
RESERVED
D2 D1 OUTPUT POWER
00-4
01-1
10+2
11+5
D5 D4 AUX OUTPUT POWER
00-4
01-1
10+2
11+5
D6 AUX OUT
0 DISABLED
1 ENABLED
D7
AUX OUTPUT
SELECT
0
FUNDAMENTAL
1
DIVIDED OUTPUT
D8 MUTE TILL
LOCK DETECT
0 MUTE DISABLED
1 MUTE ENABLED
D9 VCO
POWER-DOWN
0VCO POWERED UP
1 VCO POWERED DOWN
D12 D11 RF DIVIDER SELECT
00 ÷1
00 ÷2
01 ÷4
01 ÷8
D10
0
1
0
1
10 ÷160
D13 FEEDBACK
SELECT
0
FUNDAMENTAL
1
DIVIDED
DBB
Figure 28. Register 4 (R4)
07325-017
LD PIN
MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
00000000D15D140110000000000000000C3(1)C2(0)C1(1)
CONTROL
BITSRESERVEDRESERVED
RESERVED
D1 5 D1 4 LOCK DETECT PIN OPERATION
00LOW
0 1 DIGITAL LOCK DETECT
10LOW
11HIGH
RESERVED
Figure 29. Register 5 (R5)
ADF4350
Rev. A | Page 18 of 32
REGISTER 0
Control Bits
With Bits [C3:C1] set to 0, 0, 0, Register 0 is programmed.
Figure 24 shows the input data format for programming this
register.
16-Bit INT Value
These sixteen bits set t