© Semiconductor Components Industries, LLC, 2012
July, 2012 Rev. 12
1Publication Order Number:
MC74HC174A/D
MC74HC174A
Hex D Flip-Flop with
Common Clock and Reset
HighPerformance SiliconGate CMOS
The MC74HC174A is identical in pinout to the LS174. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
This device consists of six D flipflops with common Clock and
Reset inputs. Each flipflop is loaded with a lowtohigh transition of
the Clock input. Reset is asynchronous and activelow.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 162 FETs or 40.5 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
http://onsemi.com
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
1
16 PDIP16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC174AN
AWLYYWWG
1
16
HC174AG
AWLYWW
HC
174A
ALYWG
G
1
16
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G= PbFree Package
(Note: Microdot may be in either location)
MC74HC174A
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2
Figure 1. Pin Assignment
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
Q4
D4
D5
Q5
VCC
CLOCK
Q3
D3
D1
D0
Q0
RESET
GND
Q2
D2
Q1
Figure 2. Logic Diagram
PIN 16 = VCC
PIN 8 = GND
3
4
6
11
13
14
2
5
7
10
12
15
D0
D1
D2
D3
D4
D5
Q0
Q1
Q2
Q3
Q4
Q5
CLOCK 9
RESET 1
DATA
INPUTS
NONINVERTING
OUTPUTS
FUNCTION TABLE
Inputs Output
Reset Clock D Q
L X X L
H H H
H L L
H L X No Change
H X No Change
DESIGN/VALUE TABLE
Design Criteria Value Units
Internal Gate Count* 40.5 ea.
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0 mW
Speed Power Product 0.0075 pJ
*Equivalent to a twoinput NAND gate.
ORDERING INFORMATION
Device Package Shipping
MC74HC174ANG PDIP16
(PbFree)
500 Units / Rail
MC74HC174ADG SOIC16
(PbFree)
48 Units / Rail
MC74HC174ADR2G SOIC16
(PbFree)
2500 / Tape & Reel
MC74HC174ADTR2G TSSOP16
(PbFree)
2500 / Tape & Reel
NLV74HC174ADG* SOIC16
(PbFree)
55 Units / Rail
NLV74HC174ADR2G* SOIC16
(PbFree)
2500 / Tape & Reel
NLV74HC174ADTR2G* TSSOP16
(PbFree)
2500 / Tape & Reel
NLV74HC174ANG* PDIP16
(PbFree)
25 Units / Rail
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AECQ100 Qualified and PPAP
Capable
MC74HC174A
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3
MAXIMUM RATINGS
Symbol Parameter Value Unit
VCC DC Supply Voltage (Referenced to GND) *0.5 to )7.0 V
VIN DC Input Voltage (Referenced to GND) *1.5 to VCC )1.5 V
VOUT DC Output Voltage (Referenced to GND) (Note 1) *0.5 to VCC )0.5 V
IIN DC Input Current, per Pin $20 mA
IOUT DC Output Current, per Pin $25 mA
ICC DC Supply Current, VCC and GND Pins $50 mA
TSTG Storage Temperature Range *65 to )150 _C
TLLead Temperature, 1 mm from Case for 10 Seconds PDIP, SOIC, TSSOP 260 _C
TJJunction Temperature Under Bias )150 _C
qJA Thermal Resistance PDIP
SOIC
TSSOP
78
112
148
_C/W
PDPower Dissipation in Still Air at 85_C PDIP
SOIC
TSSOP
750
500
450
mW
MSL Moisture Sensitivity Level 1
FRFlammability Rating Oxygen Index: 30% 35% UL 94 V0 @ 0.125 in.
VESD ESD Withstand Voltage Human Body Model (Note 2)
Machine Model (Note 3)
Charged Device Model (Note 4)
u2000
u100
u500
V
ILATCHUP Latchup Performance Above VCC and Below GND at 85_C (Note 5) $300 mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. IO absolute maximum rating must be observed.
2. Tested to EIA/JESD22A114A.
3. Tested to EIA/JESD22A115A.
4. Tested to JESD22C101A.
5. Tested to EIA/JESD78.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Supply Voltage (Referenced to GND)
ÎÎÎÎÎ
ÎÎÎÎÎ
2.0
ÎÎÎÎ
ÎÎÎÎ
6.0
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VIN,
VOUT
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
DC Input Voltage, Output Voltage (Referenced to GND) (Note 6)
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VCC
ÎÎÎ
ÎÎÎ
ÎÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
TA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Operating Temperature, All Package Types
ÎÎÎÎÎ
ÎÎÎÎÎ
*55
ÎÎÎÎ
ÎÎÎÎ
)125
ÎÎÎ
ÎÎÎ
_C
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
CLOCK Input Rise and Fall Time (Figure 4) VCC = 2.0 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6.0 V
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
0
0
0
0
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
1000
700
500
400
ÎÎÎ
ÎÎÎ
ÎÎÎ
ns
6. Unused inputs may not be left open. All inputs must be tied to a high or lowlogic input voltage level.
MC74HC174A
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4
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
VCC Guaranteed Limit
Symbol Parameter Test Conditions V*55_C to 25_Cv85_Cv125_CUnit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VIH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Minimum HighLevel Input
Voltage
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| v 20 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1.5
3.15
4.2
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.5
3.15
4.2
1.5
3.15
4.2
ÎÎ
ÎÎ
ÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VIL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum LowLevel Input
Voltage
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VOUT = 0.1 V or VCC – 0.1 V
|IOUT| v 20 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
0.5
1.35
1.8
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.5
1.35
1.8
0.5
1.35
1.8
ÎÎ
ÎÎ
ÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VOH
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Minimum HighLevel Output
Voltage
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIN = VIH or VIL
|IOUT| v 20 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
1.9
4.4
5.9
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1.9
4.4
5.9
1.9
4.4
5.9
ÎÎ
ÎÎ
ÎÎ
ÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIN = VIH or VIL
|IOUT| v 4.0 mA
|IOUT| v 5.2 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
3.98
5.48
ÎÎÎ
ÎÎÎ
ÎÎÎ
3.84
5.34
3.7
5.2
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
VOL
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum LowLevel Output
Voltage
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIN = VIH or VIL
|IOUT| v 20 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
0.1
0.1
0.1
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.1
0.1
0.1
0.1
0.1
0.1
ÎÎ
ÎÎ
ÎÎ
V
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIN = VIH or VIL
|IOUT| v 4.0 mA
|IOUT| v 5.2 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
0.26
0.26
ÎÎÎ
ÎÎÎ
ÎÎÎ
0.33
0.33
0.4
0.4
ÎÎ
ÎÎ
ÎÎ
ÎÎÎÎ
ÎÎÎÎ
IIN
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum Input Leakage Current
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIN = VCC or GND
ÎÎÎ
ÎÎÎ
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
$0.1
ÎÎÎ
ÎÎÎ
$1.0
$1.0
ÎÎ
ÎÎ
mA
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ICC
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
Maximum Quiescent Supply
Current (per Package)
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎ
VIN = VCC or GND
IOUT = 0 mA
ÎÎÎ
ÎÎÎ
ÎÎÎ
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
4.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
40
160
ÎÎ
ÎÎ
ÎÎ
mA
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)
VCC Guaranteed Limit
Symbol Parameter V *55_C to 25_Cv85_Cv125_CUnit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
fmax
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Clock Frequency (50% Duty Cycle)
(Figures 4 and 7)
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
6.0
30
35
ÎÎÎ
ÎÎÎ
ÎÎÎ
4.8
24
28
4.0
20
24
ÎÎ
ÎÎ
ÎÎ
MHz
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPLH
tPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Clock to Q
(Figures 5 and 7)
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
110
22
19
ÎÎÎ
ÎÎÎ
ÎÎÎ
140
28
24
165
33
28
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tPLH
tPHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Propagation Delay, Reset to Q
(Figures 2 and 7)
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
110
21
19
ÎÎÎ
ÎÎÎ
ÎÎÎ
140
28
24
160
32
27
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tTLH
tTHL
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Output Transition Time, Any Output
(Figures 4 and 7)
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
75
15
13
ÎÎÎ
ÎÎÎ
ÎÎÎ
95
19
16
110
22
19
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
Cin
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Input Capacitance
ÎÎÎ
ÎÎÎ
ÎÎÎÎÎÎ
ÎÎÎÎÎÎ
10
ÎÎÎ
ÎÎÎ
10
10
ÎÎ
ÎÎ
pF
Typical @ 25_C, VCC = 5.0 V
CPD Power Dissipation Capacitance, per Enabled Output (Note 7) 62 pF
7. Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC.
MC74HC174A
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5
TIMING REQUIREMENTS (CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
VCC *55_C to 25_Cv85_Cv125_C
Symbol Parameter Figure V Min Max Min Max Min Max Unit
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tsu
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Minimum Setup Time, Data to Clock
ÎÎÎ
ÎÎÎ
ÎÎÎ
6
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
50
10
9.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
65
13
11
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
75
15
13
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
th
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Minimum Hold Time, Clock to Data
ÎÎÎ
ÎÎÎ
ÎÎÎ
6
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
trec
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Minimum Recovery Time,
Reset Inactive to Clock
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
5.0
5.0
5.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tw
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Minimum Pulse Width, Clock
ÎÎÎ
ÎÎÎ
ÎÎÎ
4
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
75
15
13
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
95
19
16
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
110
22
19
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tw
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Minimum Pulse Width, Reset
ÎÎÎ
ÎÎÎ
ÎÎÎ
5
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
75
15
13
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
95
19
16
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
110
22
19
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ns
ÎÎÎÎ
ÎÎÎÎ
ÎÎÎÎ
tr, tf
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
Maximum Input Rise and Fall Times
ÎÎÎ
ÎÎÎ
ÎÎÎ
4
ÎÎÎ
ÎÎÎ
ÎÎÎ
2.0
4.5
6.0
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1000
500
400
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1000
500
400
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
ÎÎÎ
1000
500
400
ÎÎ
ÎÎ
ÎÎ
ns
CLOCK 9
D0 3
RESET 1
D1 4
D2 6
D3 11
D4 13
D5 14
CQ
DR
2
5
7
10
12
15
Q0
Q1
Q2
Q3
Q4
Q5
Figure 3. Expanded Logic Diagram
CQ
DR
CQ
DR
CQ
DR
CQ
DR
CQ
DR
MC74HC174A
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6
50%
VCC
GND
VCC
GND
50%
CLOCK
Q
RESET
tPHL
Figure 4. Switching Waveform
50%
DATA
CLOCK
VCC
VCC
GND
Figure 5. Switching Waveform
VALID
GND
tsu th
1/fmax
CLOCK
Q
trtfVCC
GND
90%
50%
10%
90%
50%
10%
tPLH tPHL
tTLH tTHL
tw
*Includes all probe and jig capacitance
CL*
TEST POINT
DEVICE
UNDER
TEST
OUTPUT
Figure 6. Switching Waveform Figure 7. Test Circuit
tw
trec
50%
MC74HC174A
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7
PACKAGE DIMENSIONS
PDIP16
CASE 64808
ISSUE T
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE
MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
A
B
FC
S
H
GD
J
L
M
16 PL
SEATING
18
916
K
PLANE
T
M
A
M
0.25 (0.010) T
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.770 18.80 19.55
B0.250 0.270 6.35 6.85
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.040 0.70 1.02 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.110 0.130 2.80 3.30
L0.295 0.305 7.50 7.74
M0 10 0 10
S0.020 0.040 0.51 1.01
____
MC74HC174A
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8
PACKAGE DIMENSIONS
SOIC16
CASE 751B05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
18
16 9
SEATING
PLANE
F
J
M
RX 45_
G
8 PLP
B
A
M
0.25 (0.010) B S
T
D
K
C
16 PL
S
B
M
0.25 (0.010) A S
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.80 10.00 0.386 0.393
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.229 0.244
R0.25 0.50 0.010 0.019
____
6.40
16X
0.58
16X 1.12
1.27
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
16
89
8X
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC174A
http://onsemi.com
9
PACKAGE DIMENSIONS
TSSOP16
CASE 948F01
ISSUE B
ÇÇÇ
ÇÇÇ
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A4.90 5.10 0.193 0.200
B4.30 4.50 0.169 0.177
C−−− 1.20 −−− 0.047
D0.05 0.15 0.002 0.006
F0.50 0.75 0.020 0.030
G0.65 BSC 0.026 BSC
H0.18 0.28 0.007 0.011
J0.09 0.20 0.004 0.008
J1 0.09 0.16 0.004 0.006
K0.19 0.30 0.007 0.012
K1 0.19 0.25 0.007 0.010
L6.40 BSC 0.252 BSC
M0 8 0 8
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH. PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE W.
____
SECTION NN
SEATING
PLANE
IDENT.
PIN 1
18
16 9
DETAIL E
J
J1
B
C
D
A
K
K1
H
G
ÉÉÉ
ÉÉÉ
DETAIL E
F
M
L
2X L/2
U
S
U0.15 (0.006) T
S
U0.15 (0.006) T
S
U
M
0.10 (0.004) V S
T
0.10 (0.004)
T
V
W
0.25 (0.010)
16X REFK
N
N
7.06
16X
0.36 16X
1.26
0.65
DIMENSIONS: MILLIMETERS
1
PITCH
SOLDERING FOOTPRINT*
*For additional information on our PbFree strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
MC74HC174A
http://onsemi.com
10
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